International Journal of Electrical, Electronics and Computer Systems (IJEECS)

BEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC

FOR USE IN SAR ADC DESIGN

1
P C.SHILPA, 2M.H PRADEEP
1
P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur
2
Asst Professor, Dept. of ECE, BITIT College of Engineering, Anantapur
Email: 1pc.shilpa31@gmail.com, 2mhpradeepk@gmail.com

Its non-idealities were previously discussed by

Abstract—A model of a switched capacitor digital-to-
analog converter (DAC) based on a split capacitor
array is presented for use during the design of a
successive approximation register (SAR) analog-to-
digital converter (ADC). The model takes the effects of
parasitic capacitors into account, and the values of these
parasitic capacitors can be extracted from the circuit
topology by using Calibre by Mentor Graphics or a
similar tool. The influence of the two main parasitic
capacitor types (those parallel to and those common to
the capacitors in the arrays) on the DAC characteristics
is analyzed. We provide expressions for fast manual
calculation of the integral non-linearity (INL) and
differential non-linearity (DNL) errors according to the
value of the parasitic capacitors. Simulation results
from a Verilog-A module based on this model are given.
The model provides higher simulation speeds with
accuracy close to that of a transistor-level model by
using the extracted parasitic parameters.
I. INTRODUCTION
The use of the top-down methodology can
dramatically speed up the IC design process because
it avoids the difficulties of transistor-level simulation
of the whole system [1], [2]. As shown in [3], [4], this
approach involves behavioral modeling at different
levels of abstraction. The use of behavioral models
describing the low-level effects that arise in real
circuits can save time while providing levels of
accuracy close to that of transistor-level simulations.
Use of such a model gives designers the opportunity
to analyze how these low-level effects affect the
whole chip on a system level [5] and also to find the
possible range of low-level effects (for example,
parasitic capacitance) that is acceptable for the
design. The split capacitor array, used as both a DAC
and a sampleand- hold circuit, is an important
element of the SAR ADC.
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84
several authors [6], [7], [8]. A theoretical expression
for the capacitor array’s output voltage, involving the
effects of common parasitic capacitors, is given in
[6]. Unlike the analysis of [6], wealso analyze the
impact of the parasitic capacitors that are parallel to
the capacitors in the array. The dependence of
theoutput voltage from a unity capacitor capacitance
distributionis analyzed in [7]. A Matlab model for the
DAC’s transfer function computing is also proposed
in [7]. The distribution is considered to be normal.
However, the actual value of the unity capacitor is
determined by the values of the parasitic capacitors,
which are binary weighted. Similarly, [8] considers
only the errors in unity capacitor values, which are
Gaussian random variables.
The proposed model is intended to account for the
impact of systematic errors introduced by the binary-
weighted parasitic capacitances and parasitic
capacitances related to the C-array’s top-plate rail, on
the INL and DNL of ADC. We provide a behavioral
model of a split capacitor array, which takes into
account the parasitic capacitors related to the circuit
topology. The parasitic capacitor values can be
extracted using Mentor Graphics Calibre or a similar
tool. We also provide expressions for fast manual
calculation of INL and DNL errors relative to the
values of the different kinds of parasitic capacitance.
A Verilog-A module based on this model provides
increased simulation speed while having accuracy
close to a transistor-level simulation by using the
extracted parasitic parameters. The other expressions
for the DAC’s INL and DNL errors provided by the
model can be used to determine the parasitic values
of a real circuit. The rest of this paper is organized as
follows. Section 2 analyzes the influence of the DAC
on the SAR ADC’s parameters. Section 3 considers
the effects of common parasitic capacitors on the
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 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
output voltage of a capacitor array. Section 4
considers the effects of parasitic capacitors that are
parallel to the capacitors in the array. Section 5
describes the Verilog-A module based on our
proposed model. Section 6 proposes the simulation
results.
II. DAC IMPACT ON SAR ADC
TRANSFER FUNCTION
A well-known architecture for the SAR ADC with a
split capacitor array is shown in Fig. 1. An attenuator
capacitor Ca is used to split the array into two
subarrays. After the sampling phase, the output
voltage at the array output is Vin Vref , where Vin is
the ADC input voltage of and Vref is a reference
voltage. Then, during the approximation phase, the
output voltage reaches a value of Vref + Vqe, where
Vqe is the quantization error. The combination of the
DAC’s inputs leading to this value is considered to be
the conversion result. Thus, the following relationship
can be written:
where Vin is the input voltage, σ is the amplification
error, N is the number of bits used by the DAC, βi =
0, 1 is the value of the corresponding DAC bit, VLSB
is the least significant bit (LSB) voltage of an
appropriate ideal DAC, V err i is the error voltage of
the corresponding DAC bit, and Voffset is the offset
error. The ADC’s output code can thus be expressed
as: where D is the ADC’s output code, K = 1/σ is the
gain and Err(D) is the code dependent error, which
can be expressed as:
Thus, according to equations (1 - 3), the code
dependent errors of the DAC can easily be converted
into ADC errors.
Thus, according to equations (1 - 3), the code
dependent errors of the DAC can easily be converted
into ADC errors.
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III. INFLUENCE OF PARASITIC
CAPACITORS COMMON TO ARRAY
CAPACITORS ON DAC PERFORMANCE
First, we consider the influence of the parasitic
capacitors CpL and CpM, which are connected as
shown in Fig. 1. We consider these capacitors as top
plates connected to the supply voltage Vp, but we
show later that the value of this voltage does not
matter. It can be shown that the parasitic capacitance
to ground has no influence on the DAC performance.
From the charge conservation law, we can write (for
simplicity, we assume that all bottom plates of the
array capacitors are connected to ground):
QM = (Vref − Vp)CpM,
QL = (Vref − Vp)CpL, (4)
where Vp is the voltage on the top plates of the
capacitors in the array. (4) can be rewritten as
follows:
where C0 is the unity capacitor value, βM 0i = 0, 1 is
equal to 1 if the corresponding DAC bit on the most
significant bit (MSB) half of the array is set to NULL
(the bottom plate of the corresponding capacitor is
connected to ground) and 0 if it is not, and βM 1i = 0,
1 is equal to 1 if the corresponding DAC bit on the
MSB half of the array is set to ONE (the bottom plate
of the corresponding capacitor is connected to Vref )
and 0 if it is not. Similar behavior applies for the LSB
half of the array. Vx is the voltage at the top plates of
the capacitors in the LSB half of the array, and Vout
is the output voltage (the voltage at the top plates of
the capacitors in the MSB half of the array). Thus,
from equations (4 - 5), we can write:
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 International Journal of Electrical, Electronics and Computer Systems (IJEECS)

which is the output voltage of a corresponding ideal

DAC (without any errors, including offset, gain and
code dependent errors),

We can see from (6) that the output voltage is

independent of the voltage at the bottom plates of the
parasitic capacitors. The output voltage of the DAC
can be calculated as follows: w
hich is code dependent error of DAC. Thus, we can
see that only CpL has an influence on the DAC
output voltage. Also, from equation (8), it follows
that a nonlinearity in the transfer function occurs only
when a capacitor in the MSB half of the array is
switched. We calculate the DNL based on the work of
[9]:

where LSBe = VFS/2N, and VFS is the voltage

corresponding to the maximum DAC input code
where CsumL is the total capacitance of the LSB half value. From (8):
of the array and CsumM is the total capacitance of the
MSB half of the array. By rewriting equation (7) as a
function of the DAC’s input code j, we obtain:
Vout(j)=σ(VoutIdeal(j)+Voffset+VNonLinear(j)) .(8)
In (8), we introduced the following notations:

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 International Journal of Electrical, Electronics and Computer Systems (IJEECS)

IV. INFLUENCE OF PARASITIC

CAPACITORS PARALLEL TO ARRAY
CAPACITORS ON DAC PERFORMANCE
With proper design of the capacitor array (if all of the
capacitors in the array are identical unit capacitors),
the parasitic capacitors in parallel to the array
capacitors are binary weighted. In other words,
parallel parasitic capacitors affect the unity capacitor
value, so that the value of the attenuation capacitor
deviates from the required value. The attenuation
capacitor is usually chosen according to the
following:

However, if the real unity capacitor value is C0 = C0

+ _C0, where _C0 is the change in capacitance
because of binary weighted parasitic capacitors
parallel to the array capacitors, the choice of Ca as
defined in equation (18) will cause an error, which is
analyzed below. The following notation is introduced:

Taking equation (20) into account, the expression for

the ideal output voltage in equation (11) can be
rewritten as follows:

Then, the differential non-linearity arising from the

wrong choice of Ca value (not taking into account
_C0) is:

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 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
V. VERILOG-A MODEL
A Verilog-A model is based on the expressions (8 -
12). The model allows to enable and disable some
features through OffsetError, GainError and
NonLinearity control parameters. The values of CpL,
χ and Ca are also the parameters of the model. They
can be extracted from the layout by using the
software tools such as Mentor Graphics Calibre. All
transistors are replaced by ideal switches. The
expressions (8 - 12) take C′0 from (19) instead of C0
VI. SIMULATIONS RESULTS
The accuracy of the model was proved during the
design of a 14-bit SAR ADC, fabricated in a 0.35 μm
standard CMOS technology. The model was also used
for fast simulation of the INL and DNL according to
the current capacitor array topology. The results for
one of the design iterations are shown in Fig. 2. Table
I compares the simulation results from the proposed
Verilog-A module with those extracted from the
topology view. We used the Cadence Virtuoso
platform for the design flow and Cadence Spectra as
the circuit simulator.
VII. CONCLUSION
In this work, a model of a split capacitor array for a
DAC that is usually used in SAR ADC design was
presented. This model provides simple expressions
for fast manual calculations of the DAC’s INL and
DNL. This model can also be used for fast simulation
of the DAC in a top-down design flow, saving
simulation time. This model gives the designer an
opportunity to see the impact of device physics on the
system behavior on the higher steps of the top-down
methodology.
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