DIGITAL ELECTRONICS

SYLLABUS

UNIT I- MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem - Principle of

Duality - Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum
of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions
– Quine - Mc Cluskey method of minimization.

Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations
of Logic Functions using gates, NAND–NOR implementations – Multi level gate implementations-
Multi output gate implementations. TTL and CMOS Logic and their characteristics – Tristate gates

UNIT II - COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary
adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor -
BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder –
parity checker – parity generators – code converters - Magnitude Comparator.

UNIT III - SEQUENTIAL CIRCUITS

Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application
table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial
adder/subtractor- Asynchronous Ripple or serial counter – Asynchronous Up/Down counter -
Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of
Synchronous counters: state diagram- State table –State minimization –State assignment - Excitation
table and maps-Circuit implementation - Modulo–n counter, Registers – shift registers - Universal
shift registers – Shift register counters – Ring counter – Shift counters - Sequence generators.

TEXT BOOK:
1. M. Morris Mano, “Digital Design”, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:
1. John F.Wakerly, “Digital Design”, Fourth Edition, Pearson/PHI, 2008
2. John.M Yarbrough, “Digital Logic Applications and Design”, Thomson Learning, 2006.
3. Charles H.Roth. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013.
4. Donald P.Leach and Albert Paul Malvino, “Digital Principles and Applications”, 6th Edition, TMH,
2006.
5. Thomas L. Floyd, “Digital Fundamentals”, 10th Edition, Pearson Education Inc, 2011
6. Donald D.Givone, “Digital Principles and Design”, TMH, 2003.
UNIT – I
MINIMIZATION TECHNIQUES & LOGIC GATES
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 QUESTION BANK
CLASS/SEM: II / III SEM TOTAL MARKS: 100
Part – A (10x2=20MARKS)

1. Express F(a,b,c,d) = (A+B)(A+C)(B+C) in standard POS form. (Nov/Dec 2012)

= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C) = A B C + A C C + A B B + A B C + B B C + B C C
=ABC

2. Simplify the Boolean expression F = C(B + C)(A + B + C). (Nov/Dec 2012)

F = C (B+C) (A+B+C)
= CB + CC [(A+B+C)]
= CB + C [(A+B+C)] (since CC = C)
= CBA + CBB + CBC + CA + CB + CC
= ABC + CB + CB + CA + CB + CC (since CBB =CB & CBC = CB)
= ABC + CB + CA + C (since CB+CB+CB = CB; CC = C)
= ABC + BC + C (1+A)
= ABC + BC + C (since 1+A = 1)
= ABC + C (1+B)
= ABC + C (since 1+B = 1)
= C (1+AB)
= C {since (1+AB) =1}

3. Perform 2’s complement subtraction: 01000 – 01001. (Apr/May 2011)

Subtraction of 01000-01001: 1’s complement of 01001 is 10110 and 2’s complement is

4. Convert [734]8 into equivalent hexadecimal number. (Apr/May 2011)

(734)8 = (1 D C) 16
111 011 100 = 0001 1101 1100
1 D C

5. Define duality property. (Nov/Dec 2010)

Duality property states that every algebraic expression deducible from the postulates of
Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual
of an algebraic expression is desired, we simply interchange OR and AND operators and replace
1's by 0's and 0's by 1's.
6. Convert the expression Y = AC + AB + BC into standard SOP form. (Nov/Dec 2008)
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]

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7. State advantages and disadvantages of TTL. (Apr/May 2011)
Adv: Easily compatible with other ICs \
Low output impedance
Dis-adv: Wired output capability is possible only with tri-state and open collector types Special
circuits in Circuit layout and system design are required.

8. What are called don’t care conditions? (Apr/May 2011)

In some logic circuits certain input conditions never occur, therefore the corresponding output
never appears. In such cases the output level is not defined, it can be either high or low. These
output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditions or
incompletely specified functions.

9. What are the types of TTL logic? (Nov/Dec 2008)

1. Open collector output
2. Totem-Pole Output
3. Tri-state output.

10. Simplify the following using De Morgan's theorem [((AB)'C)'' D]'. (Apr/May 2011)
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)'
= A' + B'] = (AB)' C + D'
= (A' + B’) C + D'

PART –B (5x16=80MARKS)

11. a) i) State and prove De-Morgan’s theorem. (NOV/DEC 2012)(6)

ii) Simplify and draw the logic diagram Y= AB+AC+BD+CD. (NOV/DEC 2012)(6)
iii) Convert (2142.53)10 to its equivalent octal number. (NOV/DEC 2012)(4)
(Or)
b) i) Perform the following operations:
Subtract 1010100-1000011 in 2’s complement. (NOV/DEC 2013)(4)
Express decimal 570 in BCD and excess 3 (NOV/DEC 2013)(4)
ii) Simplify the Boolean function F(W,X,Y,Z)=Σ(0,1,2,4,5,6,8,9,12,13,14) using Karnaugh
map. (NOV/DEC 2013)(8)

12. a) i) Simplify Y= ΠM(0,1,4,5,6,8,9,12,13,14) and draw the logic circuit. (Nov/Dec 2012) (8)
ii) Minimize a) F = AB+A’C+AB’C (AB+C), b) F= A’BCD’+BCD’+BC’D’+BC’D.
(NOV/DEC 2012)(8)
(Or)
b) i) Demonstrate the validity of the associative law, and Boolean theorem for two variables.
(NOV/DEC 2013)(8)
ii) Consider the Boolean expression F= A’C+A’B+AB’C+BC. Express this function as a sum
of minterms. Find the minimal sum of products expression. (NOV/DEC 2013)(8)

13. a) Perform the following arithmetic operation. (APR/MAY 2011) (16)

i)111111102 + 101010102
ii) 111111102 – 101010102
(Or)
b) Use tabulation method to simplify the Boolean function. (MAY/JUNE 2013)(16)
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 F(A,B,C,D)=Σ (1,2,3,5,7,9,10,11,13,15)

14. a) Simplify using K-Map and draw the logic circuit (NOV/DEC 2010)(16)
i)f= ∑m (1,3,5,6,8,10,12,16,24,31) + ∑d(4,11,25,30).
ii) f= πM(1,3,5,6,8,10,12) + πd(4,11)
(Or)
b) i) Simplify the following Boolean equation function using 4-variable k-map
F=(A,B,C,D)=Π(0,1,2,3,4,10,11) (MAY/JUNE 2013)(8)
ii) Draw the logic diagram using only 2-input NAND gates to implement the expression
(AB+A’B) (CD’+C’D). (MAY/JUNE 2013)(8)

15. a) Reduce using Tabular Method. (NOV/DEC 2010)(16)

i)f=∑m(0,2,3,6,7,8,10,13)
ii) f=∑m(1,3,4,5,6,7,10,12,13) + ∑d(2,9,15)
(Or)
b) Minimize the following function using Quine McClusky method. Implement the minimized
function using. (MAY/JUNE 2009)(16)
i) NAND gates only
ii) NOR gates only.
f=∑m (1,3,4,6,8,10,12,13,14) + ∑d (0,15)

UNIT –II
COMBINATIONAL CIRCUITS
QUESTION BANK
CLASS/SEM: II / III SEM TOTAL MARKS: 100
Part – A (10x2=20MARKS)

1. What is programmable logic array? How it differs from ROM? (Nov/Dec 2012)
In some cases the number of don’t care conditions is excessive, it is more economical to use a
second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it
does not provide full decoding of the variables and does not generates all the minterms as in the
ROM.

2. What is a decoder? (Nov/Dec 2012)

A decoder is a multiple - input multiple output logic circuit that converts coded inputs into
coded outputs where the input and output codes are different.
3. Define a combinational logic. (Apr/May 2011)
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables, with no storage involved, the resulting circuit is called
combinational logic.
4. Define Multiplexer and Demultiplexer. (Apr/May 2011)
Multiplexer is a digital switch. If allows digital information from several sources to be routed
onto a single output line.
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 Demultiplexer is the inverse of the multiplexing. A Demultiplexer by pass the binary input
data to one of its many output lines.
5. Draw the truth table of a priority encoder. (Apr/May 2011)
Truth Table of 4:2 Priority encoder

Inputs Outputs
F0 F1 F2 F3 A B
0 0 0 0 X X
X X X 1 1 1
X X 1 0 1 0
X 1 0 0 0 1
1 0 0 0 0 0

6. Write the logic equation and draw the internal logic diagram for a 4 to 1 MUX.
(Apr/May 2011)
Y=D0S1’S0’+ D1S1’S0+ D2S1S0’+ D3S1S0
7. What is priority encoder? (Apr/May 2010)
A priority encoder is an encoder circuit that includes the priority function. In priority encoder,
if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence.

8. How many select lines are required to design 32 lines to 1 line MUX? (Nov/Dec 2010)
Five selection lines (S0,S1,S2,S3,S4) are required to design 32 lines to 1 line MUX.

9. Write down the truth table of half subtractor. (Nov/Dec 2010)

Inputs Outputs
Minuend (A) Subtracted (B) Difference (D) Borrow (B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

10. What is a encoder and difference between encoder and decoder? (Nov/Dec 2008)
An encoder has 2n input lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.

PART-B (5x16=80MARKS)

11. a) i) Design a 3:8 decoder using basic gates. (Nov/Dec 2012) (8)
ii) implement the Boolean function F(A,B,C,D) = ∑m(0,1,2,4,6,9,12,14) using 4:1 MUX.
(Nov/Dec 2012) (8)
(Or)
b) i)Design a Full adder circuit using basic gates. (Nov/Dec 2012) (8)
ii) Design a BCD to Excess-3 code convertor. (Nov/Dec 2012) (8)

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12. a) i) Design and implement a full subtractor circuit. (Apr/May 2011) (8)
ii) Design and implement a 8 to 1 Multiplexer circuit. (Apr/May 2011) (8)
(Or)
b) i) By using a minimum number of NAND gates design a Excess-3 to BCD code converter.
(Apr/May 2011) (10)
ii) Implement the expression using a multiplexer. F(A,B,C,D) = ∑m(0,2,3,6,8,9,12,14)
(Apr/May 2011) (6)

13. a) i) What is an encoder? Draw the logic symbol for decimal to BCD encoder and give its truth
table. (Nov/Dec 2010) (10)
ii) Draw the circuit of 4-bit parallel adder/subtractor and explain its operation.
(Nov/Dec 2010) (6)
(Or)

b) i) Draw the truth table for full adder and obtain the expression for SUM and CARRY and draw
the full adder circuit using logic gates. (Nov/Dec 2010) (8)
ii) Design and implement the following function with a multiplexer.
F(A,B,C,D) = ∑m(0,1,3,4,8,9,15). (Nov/Dec 2010) (8)

14. a) i) Design and implement the Full subtractor circuit. (Nov/Dec 2008) (8)
ii) Design the 4 to 1 multiplexer and 2x4 de-multiplexer. (Nov/Dec 2008) (8)
(Or)
b) i) Design a binary to gray code converter. (Nov/Dec 2008) (8)
ii) Design a 2-bit comparator using gates. (Nov/Dec 2008) (8)

15. a) Write in detail about the adder and subtractor. ( Apr/May 2011) (16)
(Or)
b) Construct the 16x1 multiplexer with two 8x1 multiplexer and one 2x1 multiplexer and brief its
operation. (Apr/May 2011) (16)

UNIT – III
SEQUENTIAL CIRCUITS
QUESTION BANK
CLASS/SEM: II / III SEM TOTAL MARKS: 100

Part – A (10x2=20MARKS)

1. Differentiate between combinational and sequential circuits. (Nov/Dec 2012)

(Keywords: Memory, Parallel and Serial)
Combinational Circuits Sequential circuits
Memory unit is not required Memory unity is required
Parallel adder is a combinational circuit Serial adder is a sequential circuit

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2. Give the truth table for clocked SR flip-flop. (Nov/Dec 2012)
(Keywords: Truth table, Set and Reset)
Inputs Outputs
Comments
Clock S R Q Q’
0 0 Q Q’ No Change
0 1 0 1 Reset
1 0 1 0 Set
1 1 ? ? Invalid

3. How many flip-flops are necessary at the minimum to realize a mod-13 counter?
(Keywords: Four, Mod-13)
Four Flip Flops are necessary to realize a mod- 13 counter. (Apr/May 2011)

4. What is edge-triggered flip-flop? (Apr/May 2011)

(Keywords: Edge Triggering, Positive and Negative)
The problem of race around condition can solved by edge triggering flip flop. The term edge
triggering means that the flip-flop changes state either at the positive edge or negative edge of the
clock pulse and it is sensitive to its inputs only at this transition of the clock.

5. Define race around condition. (Nov/Dec 2010)

(Keywords: Clock Pulse, Toggles)
In JK flip-flop output is fed back to the input. Therefore change in the output results change in the
input. Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously. This condition is called ‘race around condition’.

6. What is meant by shift register? (Nov/Dec 2009)

(Keywords: Shifting, Arithmetic and Logic)
The binary information in a register can be moved from stage to stage within the register or
into or out of the register upon application of clock pulses. This type of bit movement or shifting
is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to
group of registers called shift registers.

7. What is a counter? (Nov/Dec 2008)

(Keywords: Cascade, Counting)
When a group of flip-flops are connected in cascade, the counting operation is performed.
Then, this sequential circuit is most commonly used for counting purpose, and this circuit is
called as counter.

8. How flip-flop differ from a latch? (Nov/Dec 2009)

(Keywords: Clock Pluse, Sensitive)
LATCH
Latch is an asynchronous device and it has
no clock input.
Latch holds a bit value and it remains
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FLIP-FLOP
Flip-Flop has clock input and its output is
synchronized with clock pulse
Flip-Flop holds a bit value and it remains
 constant until new inputs force it to change constant until a trigger pulse is received.
Latches are Level – Sensitive Flip-Flops are Edge - Sensitive

9. Write the truth table for JK flip-flop. (Nov/Dec 2008)

(Keywords: Truth Table, Toggle)
Inputs Outputs
J K Q Q’
0 0 Latch Latch
0 1 0 1
1 0 1 0
1 1 Toggle Toggle

10. Give the comparison between synchronous & Asynchronous sequential circuits?
(Keywords: Memory, Design) (Nov/Dec 2010)
Synchronous sequential circuits Asynchronous sequential circuits
Memory elements are clocked flip-flops Memory elements are either unlocked flip -
flops or time delay elements
Easier to design More difficult to design

Part – B (5x16=80MARKS)
11. a. i) Convert SR flip-flop to T flip-flop and explain its operation. (Nov/Dec 2012) (6)
Keywords:
1. Block Diagram.
2. Graphical Symbol.
3. Characteristic Table.
4. Waveform.
5. State Diagram.
6. Excitation Table.
ii) Draw the logic diagram of a Parallel in Serial Out shift register and explain.
(Nov/Dec 2012) (10)
Keywords:
1. Sequential Logic.
2. Flip Flops.
3. Data Process.
4. Logic Diagram.
5. Parallel Form.
6. Serial Form.
Or
b. Design a synchronous counter to count the sequence 4  6  7  3  1  4. Avoid lockout
condition. Use JK flip-flop for the design. (Nov/Dec 2012) (16)
Keywords:
1. State Diagram.
2. Present State – Next State Table.
3. State Table.

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 4. Excitation Table.
5. Schematic Diagram.

12. a. i) Design a mod-12 counter. Explain its working with a timing diagram. (Apr/May 11) (10)
Keywords:
1. State Diagram.
2. State Table.
3. State Assignment.
4. Excitation Table.
5. Excitation Maps.
6. Schematic Diagram.
7. Timing Diagram.
ii) Convert a SR flip-flop into a T flip-flop. Explain its working. (Apr/May 2011) (6)
Keywords:
1. Truth Table.
2. Logic Expression.
3. Conversion Diagram.
Or
b. i) Explain the working of a master – slave JK flip-flop. (Apr/May 2011) (8)
Keywords:
1. Clock.
2. Complementary Output.
3. Propagation Delay.
4. Race Around.
5. Cascade.
6. Logic Diagram.
7. Waveform Diagram.
ii) Design and implement 4 – bit binary counter suing D flip-flop which counts all possible
odd numbers only. (Apr/May 2011) (8)
Keywords:
1. State Diagram.
2. State Table.
3. State Minimization.
4. State Assignment.
5. Excitation Table.
6. Circuit Implementation.

13. a. i) Design and explain the working of a 4 bit synchronous binary counter. (Nov/Dec 10) (8)
Keywords:
1. State Diagram.
2. State Table.
3. State Minimization.
4. State Assignment.

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 5. Excitation Table.
6. Circuit Implementation.

ii) Design a mod-5 synchronous counter using JK flip-flop and implement it.
(Nov/Dec 2010) (8)
Keywords:
1. State Diagram.
2. State Table.
3. State Assignment.
4. Excitation Table.
5. Excitation Maps.
6. Schematic Diagram.
7. Timing Diagram.
Or

b. i) Show that the characteristic equation for the complement output of a JK flip-flop is
Q’(t+1) = J’Q’+KQ. (Nov/Dec 2008) (10)
Keywords:
1. Truth Table.
2. Clocked JK FF.
3. State Transition.
4. Excitation Table.
ii) Draw the logic diagram and timing diagram of a 4-bit binary ripple counter and explain the
counting sequence. (Nov/Dec 2008) (6)
Keywords:
1. State Diagram.
2. State Table.
3. State Minimization.
4. State Assignment.
5. Excitation Table.
6. Circuit Implementation

14. a. Explain in detail about flip-flop and its types with neat diagram. (Apr/May 2011) (16)
Keywords:
1. S-R Flip Flop.
2. Truth Table.
3. Clocked S-R FF.
4. J-K Flip Flop.
5. Truth Table.
6. Clocked J-K FF.
7. D Flip Flop.
8. Truth Table.
9. T Flip Flop.

10
 10. Truth Table.
Or
b.i) Explain the working of a SR flip-flop with neat diagram. (Apr/May 2011) (6)
Keywords:
1. Clocked S-R FF.
2. Using Gates.
3. Positive edge.
4. Negative edge.
5. Truth Table.
6. Cascading.
7. Waveform.
8. Master-Slave Type.
ii) Explain in detail Serial in Serial Out and Serial In Parallel Out shift registers with neat logic
diagram. (Nov/Dec 2008) (10)
Keywords:
1. Sequential Logic.
2. Flip Flops.
3. Data Process.
4. Logic Diagram.
5. Parallel Form.
6. Serial Form.

15. a. With the neat diagram explain about the (Apr/May 2009)
i) Synchronous up/down counters. (8)
Keywords:
1. Flip Flop Diagram.
2. State Sequence Table Up counter.
3. State Sequence Table Down counter.
4. Timing diagram.
ii) Asynchronous down counter. (8)
Keywords:
1. Ripple Counter.
2. State Sequence Table.
3. State Transition Diagram.
4. Timing Diagram.
Or
b. i) Explain the universal shift register in detail. (Apr/May 2009) (8)
Keywords:
1. Pin Diagram.
2. Logic Symbol.
3. Logic Diagram.
4. Functional Table.
5. Mode Control.

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 6. Low Transition.
ii) Explain the design procedure of synchronous sequential circuit with an example.
Keywords: (Apr/May 2009) (8)
1. Specification.
2. Block Diagram.
3. Timing Diagram.
4. State Diagram.
5. State Table.
6. State Reduction.
7. State Assignment.
8. Revised State Table.
9. Next State Equation.
10. Output Equation.

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