)$$1 -ADE %ASY

#-/3 )$$1 4EST -ETHODOLOGY

&UNDAMENTAL #ONCEPTS

6$$
DEFECT

6IN
6IN
6OUT
6OUT
DEFECT
)$$1 NO DEFECT

633
$EFECT CAUSES HIGH )$$1

3934%-3
SSI 3#)%.#%
 #OPYRIGHT  BY 3YSTEMS 3CIENCE )NC
!LL RIGHTS RESERVED

&IRST %DITION *UNE  

2EVISED *ANUARY  

3YSTEMS 3CIENCE )NC

 %MBARCADERO 2OAD
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0ALO !LTO #! 
   6OICE
   &AX
INFO SYSTEMSCOM \ IDDQ SYSTEMSCOM
HTTPWWWSYSTEMSCOM

0OWER&AULT 6ERA )3$" AND 6ERITY ARE TRADEMARKS OF 3YSTEMS 3CIENCE )NC
0OWER3IM -AGELLAN AND 3IM7AVE ARE REGISTERED TRADEMARKS OF 3YSTEMS 3CI
ENCE )NC !LL OTHER TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS
 )$$1 -ADE %ASY
#-/3 )$$1 4EST -ETHODOLOGY
&UNDAMENTAL #ONCEPTS

"OB $UELL
3YSTEMS 3CIENCE )NC
 %MBARCADERO 2OAD 3UITE 
0ALO !LTO #! 
*ANUARY  

 7HAT IS )$$1

)$$1 IS THE )%%% SYMBOL FOR THE QUIESCENT POWER SUPPLY CURRENT IN A -/3 CIRCUIT
)$$1 OR )$$1 FOR OUR PURPOSES REFERS TO THE QUIESCENT CURRENT IN #-/3 INTE
GRATED CIRCUITS

)$$1 TESTING IS A COST EFFECTIVE TEST STRATEGY FOR DIGITAL #-/3 )#S WITH THE PO
TENTIAL TO IMPROVE THE AVERAGE QUALITY LEVEL OF YOUR )# PRODUCTION WITH LITTLE EXTRA
EFFORT OR COST 4HE PURPOSE OF THIS BOOKLET IS TO EXPLAIN )$$1 TESTING ITS BENEFITS
AND HOW TO USE IT TO IMPROVE #-/3 )# QUALITY AND RELIABILITY

 2EVIEW OF #OMMON $IGITAL 4EST 3TRATEGIES

4O FULLY UNDERSTAND THE IMPACT THAT )$$1 TESTING HAS ON FINAL PRODUCT QUALITY A
REVIEW OF SOME TEST PROGRAM STRATEGIES USED FOR !4% !UTOMATIC 4EST %QUIPMENT
TEST PROGRAM DEVELOPMENT IS HELPFUL

 4EST 0ROGRAM $EVELOPMENT

4EST PROGRAM DEVELOPMENT ENCOMPASSES THE PLANNING ENGINEERING AND IMPLEMEN
TATION OF A TEST STRATEGY RESULTING IN A TEST PROGRAM THAT ASSURES SATISFACTORY PRODUCT
QUALITY LEVEL 4HERE ARE THREE BASIC TEST DEVELOPMENT STRATEGIES THAT ARE OFTEN
COMBINED

3934%-3 3#)%.#% 
 &UNCTIONAL 4EST $EVELOPMENT
&UNCTIONAL TEST DEVELOPMENT IS USUALLY PERFORMED BY THE CIRCUIT DESIGNER ORIGINAT
ING WITH THE DESIGN VERIFICATION SIMULATION 4HE PURPOSE OF THE FUNCTIONAL TEST IS TO
CAUSE THE DESIGN TO BEHAVE THE SAME WAY THAT THE DESIGNER EXPECTS THAT THE END
USER WILL USE IT ,OGIC SIMULATION DATA ARE TRANSLATED TO !4% FORMAT FOR USE BY THE
!4% &UNCTIONAL TESTS ARE USUALLY CREATED BY CAPTURING THE VALUES OF A LOGIC SIMU
LATION AT THE PRIMARY )/ PINS 4HEY CAN ALSO BE CREATED DIRECTLY IN THE !4% S
TESTER LANGUAGE WITHOUT ANY LOGIC SIMULATION ALTHOUGH THIS IS RARELY DONE &AULT
SIMULATION IS OPTIONAL

 3TRUCTURAL 4EST $EVELOPMENT

3TRUCTURAL TEST DEVELOPMENT RELIES ON A COMPUTERIZED MODEL OF LOGICAL CIRCUIT
FAULTS 4HE GOAL OF THESE TESTS IS TO DETECT AS MANY OF THE MODELED FAULTS AS POSSI
BLE WITHOUT REGARD FOR THE FUNCTIONALITY OF THE CIRCUIT ! FAULT SIMULATOR GRADES THE
EFFECTIVENESS OF THE TEST S STIMULUS 4HE MOST PREVALENT FAULT MODEL IS THE SINGLE
STUCK AT MODEL EACH CIRCUIT NODE IS MODELED AS BEING CONNECTED TO A CONSTANT 
OR   )T ASSUMES THAT MOST CIRCUIT DEFECTS ARE DETECTED BY TEST SETS THAT DETECT A
HIGH PERCENTAGE OF THESE FAULTS /THER FAULT MODELS INCLUDE BRIDGING FAULTS STUCK
OPEN FAULTS DELAY FAULTS AND LEAKAGE FAULTS 4HESE TESTS ARE IMPLEMENTED WITH
"OUNDARY SCAN  &ULL SCAN  0ARTIAL SCAN  AND .ON SCAN TESTABILITY METHOD
OLOGIES AND OFTEN BEGIN WITH FUNCTIONAL TEST SETS THAT ARE ENHANCED WITH MANUALLY
ALGORITHMICALLY OR AUTOMATICALLY !40' GENERATED TEST PATTERNS 3INCE THESE FAULT
MODELS DO NOT REPRESENT ALL OF THE POSSIBLE CIRCUIT DEFECTS SOME DEVICES PASS THESE
TESTS BUT FAIL IN ACTUAL USE 3TRUCTURAL TEST DEVELOPMENT IS NORMALLY PERFORMED BY
$ESIGN 4EST %NGINEERS IN COLLABORATION WITH $ESIGN %NGINEERS 4EST SETS ARE
TRANSLATED TO THE !4% S LANGUAGE FROM FAULT GRADED LOGIC SIMULATIONS OF THE DESIGN
-OST OF TODAY S TEST DEVELOPMENT IS STRUCTURAL BECAUSE THE FAULT SIMULATOR S REPORT
PROVIDES A MEANS TO QUANTIFY THE EFFECTIVENESS OF THE TEST 3TRUCTURAL TEST DEVELOP
MENT USUALLY BEGINS WITH FUNCTIONAL LOGIC SIMULATIONS THAT ARE FAULT GRADED AND EN
HANCED FOR HIGHER FAULT COVERAGE 4HE GRADED SIMULATION RESULTS ARE CONVERTED TO
MAKE &UNCTIONAL 4EST 3ETS THE !4% STIMULATES THE CIRCUIT INPUTS AND MONITORS THE
VOLTAGE ON THE CIRCUIT S OUTPUT PINS ANDOR )$$1 4EST 3ETS THE !4% STIMULATES
THE CIRCUIT INPUTS AND MONITORS THE )$$1 POWER SUPPLY CURRENT 

 0HYSICAL $EFECT 4EST $EVELOPMENT

0HYSICAL DEFECT TEST DEVELOPMENT CONSISTS OF LISTING POSSIBLE REAL PHYSICAL DEFECTS
THAT OCCUR IN A CIRCUIT THEN CREATING SPECIFIC TESTS DESIGNED TO DETECT EACH DEFECT
 3934%-3 3#)%.#%
4HESE TESTS ARE NORMALLY DEVELOPED TO COVER FAILURES OF DEVICES THAT HAVE PASSED
TEST BUT FAIL IN SERVICE 4HE FAILING DEVICE IS ANALYZED AND THE DEFECT IS IDENTIFIED
7HILE THIS IS THE ONLY SURE METHOD TO GUARANTEE ZERO DEFECTS IT IS UNLIKELY THAT ALL
OF THE POSSIBLE PHYSICAL DEFECTS WILL BE IDENTIFIED &ORTUNATELY )$$1 TESTS OFTEN
DETECT FAULTS THAT ARE NOT PREDICTED MODELED OR SIMULATED THEREBY REDUCING THE
AMOUNT OF POST MORTEM ANALYSIS REQUIRED TO MAINTAIN A LOW DEFECT LEVEL

 !4% 4EST 4YPES

 #OMPARISON 4ESTS

#OMPARISON TESTS COMPARE THE $54 $EVICE 5NDER 4EST TO A KNOWN GOOD REFER
ENCE DEVICE 4WO PROBLEMS WITH THIS TECHNIQUE ARE OBVIOUS  HOW DO YOU PROVE
THAT THE REFERENCE DEVICE IS GOOD  HOW DO YOU KNOW THAT YOU HAVE PROVIDED
ADEQUATE STIMULUS TO COMPLETELY EXERCISE THE REFERENCE DEVICE #OMPARISON TESTS
ARE RARELY USED IN MODERN TEST PROGRAMS

 &UNCTIONAL 4ESTS AKA 6OLTAGE 4ESTS

4HE WORD FUNCTIONAL  WHEN USED TO REFER TO !4% 4EST 0ROGRAMS DESCRIBES A
STIMULUSRESPONSE TEST PROGRAM IN THE LANGUAGE OF THE TARGET !4% 4HIS DIFFERS
FROM THE USE OF THE TERM WHEN IT DESCRIBES 4EST $EVELOPMENT A SIMULATION PER
FORMED TO SIMULATE THE FUNCTIONALITY OF THE $54 WITHOUT REGARD TO ITS STRUCTURE 
4HE TESTER S SOFTWARE USES A &UNCTIONAL 4EST 3ET TO DRIVE THE $54 S INPUTS AND
COMPARE ITS OUTPUT PIN VOLTAGES TO THE TEST SET S STORED VALUES 4HE TESTER S PINS ARE
WIRED TO THE $54 AND THE TESTER SOFTWARE MAPS THE TESTER S PINS TO THE $54 S )/
PINS 4HESE TEST SETS ARE DERIVED FROM &UNCTIONAL AND 3TRUCTURAL 4EST $EVELOPMENT
LOGIC SIMULATIONS

 3CAN
3CAN TESTS ARE A VARIATION OF FUNCTIONAL TESTS 4HEY REQUIRE A PROCEDURE IN THE
!4% S TEST SET TO READ FROM AND WRITE TO THE $54 S SCANNED FLIP FLOPS AND LATCHES
3CAN IS A DESIGN FOR TESTABILITY METHODOLOGY THAT MODIFIES THE DESIGN S FLIP FLOPS
AND LATCHES TO INCLUDE A TEST MODE THAT ENABLES TEST SIGNALS TO BE LOADED OR LATCHED
DATA TO BE READ DIRECTLY BY THE TEST PROGRAM 3CANNED SEQUENTIAL ELEMENTS ARE
STITCHED TOGETHER TO FORM A SERIAL SHIFT REGISTER WHEN IN TEST MODE
3CAN MAKES SEQUENTIAL CIRCUITS MORE OBSERVABLE AND CONTROLLABLE FROM THE !4%
&ULL SCAN SIMPLIFIES !40' AUTOMATIC TEST PATTERN GENERATOR PROGRAM OPERATION BY

3934%-3 3#)%.#% 
REPLACING SEQUENTIAL DEVICES WITH SCAN )/ THEREBY ALLOWING THE !40' TO OPERATE
AS IF ONLY COMBINATIONAL CELLS ARE PRESENT

 "OUNDARY SCAN *4!' )%%% 

"OUNDARY SCAN METHODOLOGY TREATS THE SCAN LATCHES THAT SURROUND A SUB CIRCUIT
PARTITION AS TESTER )/ 4EST SETS CAN BE DEVELOPED THAT TEST EACH PARTITION SEPA
RATELY AND PARTITION TO PARTITION CONNECTIVITY %ACH SUB CIRCUIT S BOUNDARY SCAN
LATCHES ARE ACCESSED BY THE TESTER THROUGH A 4!0 4EST !CCESS 0ORT CONTROLLER

 )$$1 4ESTS

.ORMALLY )$$1 TESTING ON !4% CONSISTS OF A FUNCTIONAL TEST SET WITH OR WITHOUT
SCAN TO STIMULATE THE $54 !T TEST STEPS PREDETERMINED TO BE SUITABLE FOR )$$1
TESTS THE TESTER IS HALTED AND THE $54 S POWER SUPPLY CURRENT IS MEASURED BY THE
!4% 4HE RESULTING VALUE IS COMPARED TO A REFERENCE VALUE FOR A GONO GO TEST RE
SPONSE )$$1 TEST METHODOLOGY IS THE MOST SUCCESSFUL METHOD FOR DETECTING
#-/3 PHYSICAL DEVICE DEFECTS

 )$$1 4EST #ONCEPT

)$$1 TESTING IS BASED ON THE PREMISE THAT #-/3 CIRCUITS DRAW EXTREMELY LOW
LEAKAGE CURRENT WHEN NO TRANSISTORS ARE SWITCHING 4HE IDEAL )$$1 TESTABLE CIRCUIT
IS A FULLY COMPLEMENTARY AND FULLY STATIC #-/3 DESIGN 4HE CONCEPT OF USING
COMPLEMENTARY P -/3&%4 AND N -/3&%4 TRANSISTOR PAIRS IN THE #-/3 CON
FIGURATION WAS DESIGNED EXPRESSLY BECAUSE NO CURRENT IS CONSUMED BY THE CIRCUIT
EXCEPT WHEN SWITCHING 4HIS ATTRIBUTE OF #-/3 IMPLIES  )$$1 TESTABILITY
BY ITS VERY DEFINITION

)N PRACTICE DESIGNS THAT ARE NOT IDEAL ARE )$$1 TESTED BUT DEVIATION FROM IDEAL
#-/3 ALWAYS HAS A NEGATIVE IMPACT ON THE MAXIMUM )$$1 TEST COVERAGE THAT IS
POSSIBLE FOR THE DESIGN %VEN SO )$$1 TESTS HAVE PROVEN EFFECTIVE IN DETECTING
MANY FAULTS THAT OTHERWISE WOULD REMAIN UNDETECTED

 3934%-3 3#)%.#%
 6$$ 6$$

A B

633 633

&ULLY COMPLEMENTARY #-/3 .ON COMPLEMENTARY 2 IN PLACE OF P -/3&%4

&IGURE 

 (OW $OES -EASURING )$$1 $ETECT #-/3 $EFECTS

! #-/3 INTEGRATED CIRCUIT IN QUIESCENT STATE TYPICALLY DRAWS LESS THAN  MICRO
AMPS !NY DEFECT THAT CAUSES HIGHER )$$1 THAN THE ASSUMED THRESHOLD VALUE CAN
BE DETECTED BY MONITORING )$$1

6$$
DEFECT

6IN
6IN
6OUT
6OUT
DEFECT
)$$1 NO DEFECT

633
$EFECT CAUSES HIGH )$$1
&IGURE 

3934%-3 3#)%.#% 
 )$$1 4EST !TTRIBUTES

 %VERY TRACE IS OBSERVABLE

)$$1 TESTS DIFFER FROM FUNCTIONAL TESTS IN THAT THEY SENSE CURRENT RATHER THAN VOLT
AGE 4HIS FEATURE ENABLES THE $54 S POWER SUPPLY PINS TO SERVE AS ULTRA SENSITIVE
TEST OBSERVATION POINTS CAPABLE OF SENSING EVERY CIRCUIT TRACE AND VIA !LL )$$1
FAULTS PROPAGATE TO THE POWER SUPPLY
&UNCTIONAL TESTS SENSE VOLTAGE AND ARE SOMETIMES REFERED TO AS 6OLTAGE 4ESTS 
6OLTAGE IS TESTED AT THE $54 S OUTPUT PINS &AULTS MUST PROPAGATE TO THE $54 S
OUTPUT PINS FOR THE TESTER TO DIFFERENTIATE BETWEEN A GOOD OR BAD $54

 (IGH FAULT COVERAGE WITH FEW TEST VECTORS

.ORMALLY OVER  OF A CIRCUIT CAN BE TESTED WITH ONE OR TWO )$$1 TEST VECTORS
&IGURE  ILLUSTRATES THAT THE FIRST FEW VECTORS DETECT THE MAJORITY OF FAULTS










&AULT #OVERAGE 

          
6ECTOR NUMBER

&IGURE  4YPICAL )$$1 &AULT #OVERAGE VS  OF 4EST 6ECTORS

$ERIVED FROM -AXWELL 0# 2# !ITKEN 6*OHANSEN ) #HIANG 4HE %FFECTIVENESS OF )$$1
&UNCTIONAL AND 3CAN 4ESTS (OW -ANY &AULT #OVERAGES $O 7E .EED  0ROC  )NTERNATIONAL
4EST #ONF PP  &IGURE  AND MODIFIED TO AVERAGE FAULT MODEL TYPES

 )$$1 &AULT "EHAVIOR

! PAPER PRESENTED AT )4# 4 0OWELL ET AL #ORRELATING $EFECTS TO &UNCTIONAL
AND )$$1 4ESTS  0ROC  )NTERNATIONAL 4EST #ONFERENCE PP   DE
SCRIBES A 4) STUDY AND CONCLUDES
 3934%-3 3#)%.#%
 )$$1 DEFECTS CAN BE CLASSIFIED AT TWO TYPES )$$1 PATTERN SENSITIVE TYPES AND
)$$1 PATTERN INSENSITIVE TYPES WHICH MEANS THAT ANY CURRENT MEASUREMENT PATTERN
WILL SCREEN THE DEFECT "Y FAR THE MAJORITY OF )$$1 DEFECTS ARE THE )$$1 PATTERN
INSENSITIVE TYPE 'ATE OXIDE DEFECTS TEND TO BE PATTERN SENSITIVE DEFECTS WHILE THE
METAL SHORTS TO '.$ OR 6$$ TEND TO BE PATTERN INSENSITIVE DEFECTS
7HEN SELECTING )$$1 TESTS TO APPLY IT IS MOST IMPORTANT TO TARGET THE PATTERN
SENSITIVE TYPE SINCE THE OTHER TYPE WILL BE SCREENED NO MATTER WHICH TESTS ARE AP
PLIED 4HE METHOD FOR SELECTING THE PATTERNS WHETHER IT IS A PSEUDO STUCK AT FAULT
CURRENT GRADE OR A TRANSISTOR SHORT MODEL DID NOT MATTER IN SELECTING THE MORE EF
FECTIVE TESTS "OTH TYPES WERE EQUALLY EFFECTIVE ALTHOUGH THE GRADES GIVEN WERE
SLIGHTLY DIFFERENT )T IS IMPORTANT HOWEVER TO USE AN )$$1 FAULT GRADING TOOL TO
SELECT THE CRITICAL PATTERNS TO EFFECTIVELY SCREEN THE LARGEST NUMBER OF DEFECTS 
3YSTEMS 3CIENCE S 0OWER&AULT )$$1 IS ESPECIALLY WELL SUITED FOR FINDING THE
PATTERN SENSITIVE FAULT TYPES SINCE IT OPTIMIZES TEST VECTOR SELECTION FOR MAXIMUM
FAULT COVERAGE OVER SINGLE OR MULTIPLE TEST BENCHES 4HE ABOVE GRAPH INDICATES THAT
MANY FAULTS ARE COVERED IN THE FIRST FEW VECTORS 4HESE ABUNDANT FIRST FAULTS CAN BE
DETECTED WITH MOST OF THE QUALIFIED )$$1 TEST VECTORS WHEREAS THE FAULTS FOUND ON
THE RIGHT SIDE OF THE GRAPH REQUIRE SPECIFIC TEST VECTORS TO DETECT SPECIFIC FAULTS
0OWER&AULT )$$1 S CELL BOUNDARY FAULT MODEL IS ESPECIALLY WELL SUITED TO INSURE
OPTIMAL FAULT COVERAGE

 $EFECTS $ETECTABLE BY )$$1 4ESTS

 .ODE "RIDGES

7HEN A BRIDGE CONNECTS TWO NODES THAT ARE DRIVEN BY CONFLICTING VOLTAGES AFTER
PASSING THROUGH ONE LOGIC GATE PROPAGATES A STRONG LOGIC STRENGTH (IGH )$$1
OCCURS IN AT LEAST ONE OF THE LOGIC STATES .ODE BRIDGES ARE DETECTED BY SETTING THE
ADJACENT NODES TO OPPOSITE LOGIC STATES 4HESE FAULTS ARE EASILY DETECTED BY FUNC
TIONAL TEST SETS PROVIDED THAT THE NODES ARE EASILY OBSERVABLE AND THE BRIDGE IS LOW
IMPEDANCE

 'ATE /XIDE 3HORTS

'ATE OXIDE SHORTS USUALLY CAUSE WEAKENED LOGIC VOLTAGES BUT THEY DO NOT GENERALLY
CAUSE LOW FREQUENCY LOGIC ERRORS 4HESE FAULTS ARE LIKELY TO PASS FUNCTIONAL TESTS
BUT MAY CAUSE THE DEVICE TO FAIL IN SERVICE AS IT AGES &AULTS ARE DETECTED BY PLAC
ING THE GATE S INPUT NODE IN BOTH  AND  STATES

3934%-3 3#)%.#% 
 ,EAKY PN *UNCTIONS
,EAKY PN JUNCTIONS DRAIN OR SOURCE TO BULKWELL LEAKS ARE RARELY DETECTED BY
FUNCTIONAL TESTS BUT ARE EASILY DETECTED BY )$$1 TESTS

 0OWER 3UPPLY "RIDGES

-OST POWER SUPPLY BRIDGE FAULTS ARE DETECTED BY BOTH FUNCTIONAL AND )$$1 TESTS

 0UNCHTHROUGH
0UNCHTHROUGH DRAIN TO SOURCE LEAKS ARE SELDOM DETECTED BY FUNCTIONAL TESTS BUT
THEY ARE EASILY DETECTED BY )$$1 TESTS

 0ARASITIC ,EAKS

0ARASITIC LEAKS ARE SELDOM DETECTED BY FUNCTIONAL TESTS BUT THEY ARE READILY DE
TECTED BY )$$1 TESTS

 /PEN 4RANSISTOR 'ATES $RAIN AND 3OURCES

/PEN GATES OFTEN APPEAR AS TIMING FAULTS $RAIN AND SOURCE OPENS CAN CAUSE A
COMBINATIONAL CIRCUIT TO EXHIBIT MEMORY CHARACTERISTICS /PEN TRANSISTOR ELEMENT
FAULTS MAY OR MAY NOT CAUSE ELEVATED )$$1 LEVELS

 $EFECTS 5NTESTABLE BY )$$1 4ESTS

)$$1 TESTS ARE NOT RELIABLE FOR OPEN TRANSISTOR FAULTS

 $EFECTS 4HAT !RE 5NTESTABLE BY &UNCTIONAL 4ESTS

 2EDUNDANT ,OGIC

&UNCTIONAL TESTS CANNOT DISCERN AMONG REDUNDANT LOGIC ELEMENTS SINCE THEY ARE
CONSTRAINED TO OBSERVING OUTPUTS COMMON TO THE REDUNDANT LOGIC )$$1 TESTS OB
SERVE REDUNDANT LOGIC ELEMENTS INDEPENDENTLY WITHOUT REGARD TO THEIR COMMON
OUTPUT

 3HORTS
2ESISTIVE SHORTS ARE ESPECIALLY DIFFICULT FOR FUNCTIONAL TESTS TO DETECT BUT ARE QUITE
SUSCEPTIVE TO DETECTION BY )$$1 TESTS ,OW IMPEDANCE SHORTS ARE NORMALLY DE
TECTABLE BY EITHER METHOD

 3934%-3 3#)%.#%
 "URN IN &AILURES
)$$1 TESTS HAVE PROVED TO BE AN EFFECTIVE PRE SCREEN FOR BURN IN FAILURES -ANY
DEVICES THAT PASS FUNCTIONAL TESTS BUT FAIL )$$1 TESTS ALSO FAIL BURN IN TESTS )$$1
TESTS ARE NOT GENERALLY RECOGNIZED AS A REPLACEMENT FOR BURN IN TESTS BUT ARE USEFUL
IN IMPROVING BURN IN TEST THROUGHPUT AND IN REDUCING POST BURN IN FAILURES (OW
EVER A PAPER 4 (ENRY 4 3OO "URN IN %LIMINATION OF A (IGH 6OLUME -ICRO
PROCESSOR 5SING )$$1  0ROC  )NTERNATIONAL 4EST #ONFERENCE PP 
OFFERS A TECHNICAL AND ECONOMIC CASE STUDY BY ).4%, WHERE BURN IN TESTS ARE
ELIMINATED BY )$$1 TESTING

 $ELAY &AULTS

$ELAY OR TIMING FAILURES FREQUENTLY ORIGINATE WITH FAULTS THAT ARE DETECTABLE BY
)$$1 TESTS 7HILE )$$1 TESTS DO NOT DETECT ALL DELAY FAULTS THEY CAN SIGNIFICANTLY
IMPROVE THE ODDS THAT SUCH FAULTS ARE DETECTED
)$$1 TESTS ALONG WITH VERY LOW VOLTAGE FUNCTIONAL TESTS * #HANG % -C#LUSKEY
$ETECTING $ELAY &LAWS BY 6ERY ,OW 6OLTAGE 4ESTING  0ROC  )NTERNATIONAL
4EST #ONFERENCE PP  CAN DETECT MOST DELAY FAULTS WITHOUT SPECIFIC DELAY
FAULT MODELING

 0OTENTIAL $ETECTS

! POTENTIALLY OR PARTIALLY DETECTED FAULT IS DEFINED IN THE CONTEXT OF THE TRADITIONAL
STUCK AT FAULT SIMULATION )T REFERS TO THE CASE WHERE A FAULT FREE NODE IS A KNOWN
 OR  VALUE BUT THE FAULTED NODE IS 8 UNKNOWN  )$$1 TESTS CANNOT GENER
ATE POTENTIALY DETECTABLE FAULTS MOREOVER THEY SOLIDLY DETECT THOSE THAT ARE GENER
ATED BY TRADITIONAL FAULT SIMULATORS

 2ELATIVE %FFECTIVENESS OF THE 4EST 4YPES

&IGURE  ILLUSTRATES THE PUBLISHED RESULTS OF A STUDY PERFORMED AT (EWLETT 0ACKARD
WHERE THREE WAFER LOTS CONSISTING OF  DIE WERE TESTED AND BINNED )T GRAPHI
CALLY ILLUSTRATES THE RELATIONSHIP AMONG FUNCTIONAL TESTS SCAN TESTS AND )$$1 TESTS
)T SHOWS THAT EACH TEST TYPE IS CAPABLE OF DETECTING FAULTS UNDETECTABLE BY OTHER
MEANS !LTHOUGH NOT THE SPECIFIC INTENT OF THE PAPER THIS GRAPHICALLY ILLUSTRATES
THAT THE ADVANTAGE OF )$$1 TESTING IS TOO IMPORTANT TO IGNORE

3934%-3 3#)%.#% 
 4HE (0 4EST 4RIAD

&AIL FUNCTIONAL



 

&AIL SCAN
&AIL )$$1
 


-AXWELL 0# 2# !ITKEN 6*OHANSEN ) #HIANG 4HE %FFECTIVENESS OF )$$1 &UNCTIONAL
AND 3CAN 4ESTS (OW -ANY &AULT #OVERAGES $O 7E .EED  0ROC  )NTERNATIONAL 4EST
#ONF PP  

&IGURE 

 #OMPARISON OF 4EST -ETHOD 3UCCESS FOR #-/3 )#S

0  0OOR &  &AIR '  'OOD
$EFECT &UNCTIONAL 3TRUCTURAL )$$1
'ATE /XIDE 3HORT 0 0 '
"RIDGE & & ' '
0ARASITICS 0 0 '
PN LEAKAGE 0 0 '
0UNCHTHROUGH & & '
/PEN DRAIN 0 & ' &
/PEN GATE & ' &
4ABLE 
#ONDENSED FROM *- 3ODEN AND #& (AWKINS #URRENT -ONITORING )$$1 4ESTING FOR %FFI
CIENT $ETECTION OF #-/3 )# $EFECTS AND &AULTS  ! 4EXAS )NSTRUMENTS 0RESENTATION -ARCH 
 (OUSTON 48

 3934%-3 3#)%.#%
 %FFICIENT 4EST $EVELOPMENT

 3IMPLIFY 4EST $EVELOPMENT BY $EVELOPING )$$1 4ESTS &IRST

 3TART 7ITH $ESIGN 6ERIFICATION 4EST 3UITE

5SE THE FUNCTIONAL TEST OR DESIGN VERIFICATION TEST SUITE FOR INITIAL )$$1 TEST DEVEL
OPMENT 4HIS TEST SUITE USUALLY STIMULATES THE DESIGN THOROUGHLY WITH FEWER TEST
VECTORS THAN TEST SUITES THAT TARGET SPECIFIC FAULTS

 !UGMENT DESIGN VERIFICATION TESTS TO TOGGLE ALL NODES

)T IS A GOOD IDEA TO RUN THE LOGIC SIMULATOR S TOGGLE TEST TO VERIFY THAT THE DESIGN
VERIFICATION TEST SUITE HAS EXERCISED ALL OF THE DESIGN S NODES 7HILE COMPLETE
TOGGLE COVERAGE DOES NOT ASSURE THAT DESIGN VERIFICATION IS COMPLETE IT IS A GOOD
STARTING POINT FOR BOTH DESIGN VERIFICATION AND FOR THE FOLLOWING $54 TEST DEVEL
OPMENT

 -INIMIZE THE TIME THAT BI DIRECTIONAL PADS ARE AT :

$RIVE BI DIRECTIONAL PADS FROM INPUTS OR INSURE THAT THEY ARE DRIVEN TO A KNOWN
VALUE 4HIS MINIMIZES CONTENTION PROBLEMS AND INSURES GREATER SUCCESS IN LATER
TEST DEVELOPMENT ACTIVITIES

 3ELECT THE MAXIMUM ALLOWABLE NUMBER OF )$$1 TEST VECTORS

 )$$1 TEST VECTOR OPTIMIZATION

$UE TO THE RELATIVELY LONG TIME PERIOD REQUIRED FOR A STABLE HIGH PRECISION )$$1
CURRENT MEASUREMENT TO BE MADE USUALLY ONLY A FEW )$$1 TEST VECTORS ARE AL
LOWED 4HEREFORE IT IS CRUCIAL THAT THE SELECTED VECTORS COVER AS MANY )$$1 FAULTS
AS IS POSSIBLE -OST )$$1 VECTOR SELECTION TOOLS SELECT THEIR VECTORS ON THE BASIS
OF THE PERCENTAGE OF REMAINING UNDETECTED FAULTS DETECTED BY EACH VECTOR CANDI
DATE -ORE ADVANCED TOOLS SUCH AS 3YSTEM 3CIENCE S 0OWER&AULT )$$1 ACTUALLY
OPTIMIZE BY ANALYZING THE COVERAGE OF EACH OF THE VECTOR CANDIDATES TO SELECT THE
VECTOR SET WITH THE HIGHEST POSSIBLE OVERALL FAULT COVERAGE 0OWER&AULT )$$1 CAN
OPTIMIZE VECTOR SELECTION OVER SINGLE OR MULTIPLE TEST BENCHES

 &OR )$$1 !40' ALONE MAY BE INEFFECTIVE

7HEN ONLY A FEW )$$1 TEST VECTORS ARE ALLOWED IT IS IMPORTANT THAT THERE BE AS
MUCH )$$1 FAULT ACTIVITY WITH AS FEW VECTORS AS POSSIBLE !40'S ARE FAULT
3934%-3 3#)%.#% 
DIRECTED  MEANING THAT THE !40' ATTEMPTS TO GENERATE A TEST VECTOR SEQUENCE FOR
EACH FAULT THAT IT ENCOUNTERS 4HIS METHODOLOGY MAY CREATE SPARSE TEST SETS LOW
FAULT ACTIVITY PER TEST PATTERN 
3OME !40'S CAN GENERATE RANDOM TEST PATTERNS 7HILE FOR SOME DESIGNS RANDOM
STIMULUS YIELDS GOOD RESULTS RANDOM TEST STIMULUS GENERATION CAN BE ACCOMPLISHED
EASILY WITHOUT EXPENSIVE !40' PROGRAMS

 2EMOVE DETECTED STUCK AT FAULTS FROM SUBSEQUENT FAULT SIMULATION

&UNCTIONALSTRUCTURAL TESTS ARE USUALLY BASED ON THE STUCK AT FAULT MODEL )$$1
STUCK AT FAULTS ARE A SUPERSET OF STRUCTURAL STUCK AT FAULTS )$$1 TESTS DETECT
HIGH IMPEDANCE DEFECTS THAT FUNCTIONAL TESTS DO NOT (OWEVER LOW IMPEDANCE
STUCK AT DEFECTS ARE DETECTED BY BOTH METHODS 4HEREFORE IT IS VALID TO REMOVE THE
STUCK AT FAULTS DETECTED BY )$$1 TESTS FROM CONSIDERATION IN SUBSEQUENT FAULT
SIMULATIONS

 $EVELOP AND %NHANCE &UNCTIONAL 4ESTS

5SE A COMBINATION OF MANUAL ALGORITHMIC OR !40' GENERATED TEST VECTORS TO
ACHIEVE THE DESIRED STUCK AT FAULT COVERAGE

 4HE 3TUCK AT &AULT 3IMULATOR

7ITH THE )$$1 STUCK AT FAULTS REMOVED THE FAULT SIMULATOR S WORKLOAD IS REDUCED
&AULT SIMULATION WORKLOAD CAN BE FURTHER REDUCED IF IT IS POSSIBLE TO USE UNIT DELAY
SIMULATION RESULTS OF UNIT DELAY AND FULL TIMING SIMULATIONS ARE EQUAL 

 )$$1 4EST -EASUREMENT 3TRATEGIES

"EFORE )$$1 TESTS CAN BE IMPLEMENTED ON !4% A THRESHOLD PASSFAIL REFERENCE
VALUE MUST BE ESTABLISHED 4HIS VALUE REPRESENTS THE QUIESCENT )$$ VALUE FOR THE
DEVICE /NCE THIS VALUE IS ESTABLISHED THERE ARE SEVERAL METHODS OF PERFORMING THE
ACTUAL )$$1 MEASUREMENTS AND COMPARING THEM TO THE REFERENCE VALUE

 4HRESHOLD $ETERMINATION

/NE OF THE MOST CONTROVERSIAL ASPECTS OF )$$1 TESTING IS DETERMINING THE PASSFAIL
REFERENCE VALUE THAT WILL BE USED TO TEST AN )# /NE METHOD IS TO SAMPLE REPRESEN
TATIVE )#S TO ARRIVE AT A PRACTICAL THRESHOLD VALUE !NOTHER METHOD IS TO RUN 30)#%
TO DETERMINE LEAKAGE VALUES FOR EACH CELL TYPE THEN MULTIPLY THOSE VALUES BY THE

 3934%-3 3#)%.#%
NUMBER OF EACH CELL TYPE IN THE DEVICE 9ET ANOTHER METHOD IS TO SIMPLY GUESS
BASED ON PREVIOUS EXPERIENCE
4YPICAL REFERENCE VALUES ARE BETWEEN  AND  MICRO AMPS 4HE RISK OF SETTING
THIS VALUE TOO LOW IS THAT POSSIBLY GOOD DEVICES MAY BE REJECTED 4HE RISK OF SET
TING THE THRESHOLD VALUE TOO HIGH IS THAT BAD DEVICES ESCAPE DETECTION 3OME DE
VICES WILL FAIL )$$1 BUT PASS FUNCTIONAL TESTS

 /FF #HIP #URRENT -ONITORING

3LOW TEST TIMES ARE A REAL DISADVANTAGE TO THE )$$1 TEST STRATEGY 4O PARTIALLY
OVERCOME THIS PROBLEM SOME TEST FACILITIES HAVE DEVISED )$$1 MEASURING AND
THRESHOLD DETECTING HARDWARE THAT ALLOWS THE !4% TO PERFORM )$$1 TESTS AT HIGHER
SPEEDS 4HESE HARDWARE IMPLEMENTATIONS USUALLY CONSIST OF DIFFERENTIAL AMPLIFIERS
WITH THRESHOLD REFERENCE CIRCUITRY ALL OF WHICH IS MOUNTED ON THE TESTER S LOAD
BOARD /NE SUCH EXAMPLE IS EXPLAINED AND ILLUSTRATED IN THE (EWLETT 0ACKARD
!PPLICATION .OTE   -EASURING #-/3 1UIESCENT 0OWER 3UPPLY #URRENT WITH
THE (0   &IGURE  AND &IGURE 
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3934%-3 3#)%.#% 
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4HE 14!' 1UALITY 4EST !CTION 'ROUP BEGAN AT THE )4#  )NTERNATIONAL 4EST
#ONFERENCE  )T IS SUPPORTED BY BOTH THE SEMICONDUCTOR INDUSTRY AND THE ACADEMIC
COMMUNITY )T IS CHARGED WITH DEVELOPING A STANDARD METHOD FOR )$$1 TESTING
14!' IS DEVELOPING A STANDARD OFF CHIP CURRENT MONITORING DEVICE $OCUMENTS
RELATING TO THE ACTIVITIES OF 14!' CAN BE FOUND IN THE PROCEEDINGS OF THE )4#

 ")#3
"UILT IN CURRENT SENSING CIRCUITS HAVE BEEN DESCRIBED IN SEVERAL )4# PAPERS 7HILE
THE IDEA IS ATTRACTIVE THERE ARE SEVERAL TECHNICAL ISSUES THAT ARE UNRESOLVED IN ITS
IMPLEMENTATION SUCH AS CROSSTALK ROUTING ETC  .O COMMERCIAL APPLICATIONS OF
THIS TECHNOLOGY ARE NOTED AT THE PRESENT TIME

 0-5
4HE TESTER S PARAMETERIC MEASURING UNIT IS BY FAR THE MOST COMMON TNSTRUMENT FOR
MEASURING )$$1 )T HAS THE ADVANTAGE OF BEING READILY AVAILABLE TO TEST PROGRAM
MERS WITHOUT MODIFING HARDWARE

 3934%-3 3#)%.#%
 )$$1 4EST 0ROGRAM #ONSIDERATIONS

 3ELECT &UNCTIONAL 6ECTORS THAT 1UALIFY FOR )$$1

. O 3 TRO B E S 7 H E N . O T )$ $ 1 1 U A LIFIE D
# O N TE N TIO N
7 AIT M S FOR )$ $ 1 3TROBE
0 U LL U P A CTIVE
& UNCTIONAL # YCLES NS
5 N IN ITIA LIZE D

FUNCT STROBES
) $$1 STROBES

&IGURE  &UNCTIONAL 6ECTORS WITH )$$1 )NTERSPERSED

$ETERMINE WHICH FUNCTIONAL TEST VECTORS QUALIFY FOR )$$1 4HIS CAN BE DONE
MANUALLY ON THE TESTER BY STOPPING TO MEASURE )$$1 AT EACH FUNCTIONAL TEST VECTOR
4HIS METHOD IS VERY USEFUL TO DETERMINE IF THE $54 IS )$$1 TESTABLE )F ANALOG
CIRCUITS OR 2!- CURRENTS CANNOT BE DISABLED THERE WILL BE NO VECTORS THAT EXHIBIT
LOW CURRENT )T IS ALSO POSSIBLE TO CREATE )$$1 TEST SETS IN THIS MANNER BUT WHEN
THE NUMBER OF )$$1 VECTORS IS LIMITED IT IS WASTEFUL IN TERMS OF TEST COVERAGE
)$$1 TEST GENERATOR TOOLS FAULT GRADE EACH )$$1 TEST VECTOR "ESIDES THE CONFI
DENCE INSTILLED BY HAVING TEST COVERAGE NUMBERS FAULT GRADING PROVIDES THE POS
SIBILITY OF OPTIMIZING VECTOR SELECTION FOR HIGHER TEST COVERAGE !DVANCED TOOLS
SUCH AS 0OWER&AULT )$$1 ARE ABLE TO ANALIZE THE RESULTS OF MULTIPLE SIMULATIONS
TEST BENCHES AND OPTIMIZE )$$1 TEST VECTOR SELECTION FOR HIGHEST FAULT COVERAGE
)$$1 TEST TOOLS DO NOT HAVE ACCESS TO ACTUAL )$$1 CURRENT VALUES 7ITH THE EX
CEPTION OF GROSS )$$1 TESTABILITY VIOLATIONS ACTUAL CURRENT VALUES ARE NOT NECES
SARY TO DETERMINE WHICH FUNCTIONAL TEST VECTORS QUALIFY FOR )$$1 TESTING )$$1
TOOLS SORT FUNCTIONAL TEST VECTORS BY 1UALIFIED OR .OT QUALIFIED STATUS 4HIS IS
DONE BY MONITORING THE LOGIC SIMULATION TO IDENTIFY  UNITIALIZED NODES  FLOAT
ING NODES  NODES VALUES IN CONTENTION AND  PULLUPPULLDOWN RESISTORS ACTIVE
!NY OF THESE CONDITIONS DISQUALIFY A FUNCTIONAL TEST VECTOR FOR )$$1 TESTS BECAUSE
QUIESCENCE CANNOT BE GUARANTEED )$$1 TOOLS RUN FROM DIGITAL LOGIC OR FAULT
SIMULATORS AND DO NOT HAVE ACCESS TO ANALOG INFORMATION

3934%-3 3#)%.#% 
 )$$1 4EST 3TROBE AT THE %ND OF THE 4EST #YCLE
)$$1 TEST STROBES WILL ALWAYS BE AT THE VERY END OF THE SELECTED FUNCTIONAL TEST
VECTOR !N )$$1 TEST IS IMPLEMENTED BY HALTING AT THE END OF A FUNCTIONAL TEST
VECTOR BEFORE THE NEXT FUNCTIONAL TEST VECTOR IS APPLIED WAIT FOR SETTLING TIME THEN
MEASURE )$$1 4HE )$$1 STROBE THEREFORE WILL ALWAYS BE THE LAST POSSIBLE TIME
BEFORE THE NEXT FUNCTIONAL TEST CYCLE

 4EST AT (IGH 6OLTAGE

4ESTING AT HIGH VOLTAGE LIMITS INCREASES THE CURRENT THROUGH HIGH IMPEDANCE SHORTS

 4EST AT (IGH 4EMPERATURE

4ESTING AT HIGH TEMPERATUE STRESSES THE $54 AND IS MORE EFFECTIVE AT DETECTING
FAULTS

 &AULT -ODELS FOR )$$1 4EST 4OOLS

" 
3  6$$
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&IGURE  .!.$ %XAMPLE OF -ODEL TYPES

)N THE TABLES THAT FOLLOW

$  $ETECTED
5  5NDETECTABLE
.  15)%4%34 DETECTED FAULTS THAT MAY NOT BE DETECTED BY #ELL -ODEL

 3934%-3 3#)%.#%
 4OGGLE -ODEL
4HE TOGGLE FAULT MODEL IS THE SIMPLEST AND LEAST COMPREHENSIVE OF ALL OF THE )$$1
DEFECT MODELS &OR A TWO INPUT .!.$ GATE THERE ARE SIX FAULTS EACH INPUT AND
THE OUTPUT STUCK AT BOTH  AND   4HE RULE FOR COUNTING A FAULT DETECTED IS THAT
THE FAULTED NODE WHEN TESTED MUST BE IN THE STATE OPPOSITE ITS STUCK VALUE 
FAULT DETECTION IS REPORTED WITH INPUT VECTOR SETS [] [] [ 
AND [] %ACH CIRCUIT NODE IS A FAULT OBSERVATIONDETECTION POINT FOR FAULT
GRADING 4HE 4OGGLE MODEL REQUIRES ONLY A LOGIC SIMULATOR TO GRADE )$$1 FAULTS
4OGGLE TESTING IS A GOOD STARTING POINT BEFORE ANY EFFORT IS MADE TO FAULT SIMULATE A
TEST BENCH 4HIS MODEL HAS THE SAME FAULTS AS THE 0SEUDO 3TUCK AT MODEL BUT DIF
FERS IN THAT IT DOES NOT REQUIRE THAT FAULTS BE PROPAGATED TO GATE OUTPUTS

)N /UT FAULT
!" : !3 !3 "3 "3 :3 :3
  $ $ $
  $ $ $
  $ $ $
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4ABLE  4OGGLE $ETECTION -AP  &AULTS

3934%-3 3#)%.#% 
 0SEUDO 3TUCK AT &AULT -ODEL
4HE 0SEUDO 3TUCK AT DEFECT MODEL IS A CARRY OVER FROM THE FUNCTIONAL TEST STUCK AT
MODEL &OR A TWO INPUT .!.$ GATE THERE ARE SIX FAULTS EACH INPUT AND THE OUTPUT
STUCK AT BOTH  AND   4HE RULE FOR COUNTING AN INPUT FAULT DETECTED IS THAT
WHEN TESTED ITS NODE BE IN THE STATE OPPOSITE ITS STUCK AT VALUE AND THAT THE GATE S
OUTPUT BE THE VALUE OPPOSITE ITS VALUE WHEN NO FAULT IS PRESENT 'ATE OUTPUTS ARE
DETECTED JUST BY THE OUTPUT BEING AT THE STATE OPPOSITE THE STUCK AT VALUE 
FAULT DETECTION IS ACHIEVED WITH THE INPUT VECTOR SET [] )$$1 TOOLS THAT
USE THIS MODEL REQUIRE A FAULT SIMULATOR %ACH GATE OUTPUT IS A FAULT OBSERVA
TIONDETECTION POINT FOR FAULT GRADING !LL CELLS MUST BE MODELED AT THE GATE LEVEL
OTHERWISE ACCURACY IS ADVERSELY AFFECTED -ODEL ACCURACY FOR SIMPLE COMBINA
TIONAL LOGIC CELLS IS EQUIVALENT TO THE 15)%4%34 MODEL 4ABLE   .OTICE THAT
BOTH INPUT STUCK AT  FAULTS ARE ./4 DETECTED WITH INPUT VECTOR  DIFFERENT THAN
TOGGLE MODEL 

)N /UT FAULTS
!" : !3 !3 "3 "3 :3 :3
  $
  $ $
  $ $
  $ $ $
4ABLE  0SEUDO 3TUCK AT $ETECTION -AP  &AULTS

 3934%-3 3#)%.#%
 15)%4%34 &AULT -ODEL
4HE 15)%4%34 -ODEL WAS INTRODUCED IN A PAPER BY 7 -AO 2+ 'ULATI $
'OEL AND - #ILETTI ENTITLED 15)%4%34 ! QUIESCENT CURRENT TESTING -ETHODOL
OGY FOR DETECTING LEAKAGE FAULTS )NT #KT #OMP !ID $ES )##!$   3EV
ERAL )$$1 TEST TOOLS ARE MODELED AFTER THIS WORK
! SPECIAL FAULT MODEL MUST BE MADE FOR EACH CELL TYPE %ACH NODE AT THE TRANSISTOR
IMPLEMENTATION LEVEL IS ANALYZED FOR EACH VECTOR OF THE SET OF POSSIBLE INPUT VEC
TOR COMBINATIONS TO DETERMINE WHICH FAULTS ARE TESTED &OR A TYPICAL TWO INPUT
.!.$ GATE THERE ARE TWENTY FOUR FAULTS 4HE RULE FOR COUNTING A FAULT DETECTED IS
THAT IT EXISTS IN THE FAULT LOOK UP TABLE ENTRY TRANSISTOR LEVEL FAULT MAPPING TABLE
THAT CORRESPONDS WITH THE INPUT VECTOR FOR THE CELL  FAULT DETECTION IS
ACHIEVED WITH THE INPUT VECTOR SET [] %VERY TRANSISTOR NODE IS A FAULT OB
SERVATIONDETECTION POINT FOR FAULT GRADING 15)%4%34 REQUIRES ONLY A LOGIC
SIMULATOR TO GRADE )$$1 FAULTS !LSO IT REQUIRES MAPPING FAULTS FROM THE TRANSIS
TOR IMPLEMENTATION OF EACH CELL TYPE IN THE $54 TO A FAULT LOOK UP TABLE 4HE
GREATEST DISADVANTAGE TO THIS MODEL IS THE EXTRAORDINARY EFFORT REQUIRED TO DEVELOP
AND MAINTAIN AN ACCURATE FAULT MODEL LIBRARY /FTEN 15)%4%34 TOOLS ARE USED
WITH LIBRARIES THAT HAVE NOT BEEN MAPPED FOR THE SPECIFIC LIBRARY USED BY THE $54
A PRIMARY SOURCE OF INACCURACY
3EE &IGURE  FOR AN EXAMPLE OF MAPPING 15)%4%34 FAULTS %ACH TRANSISTOR ELE
MENT IS CONSIDERED SHORTED GATE TO SOURCE '3  GATE TO DRAIN '$  SOURCE TO
DRAIN 3$  GATE TO BULKWELL '"  SOURCE TO BULKWELL 3"  AND DRAIN TO
BULKWELL $"  %ACH INPUT COMBINATION IS PROPAGATED THROUGH THE TRANSISTOR
MODEL OF THE GATE AND WHEN TWO NODES ARE AT OPPOSITE STATES   OR   THE CORRE
SPONDING SHORTED NODE OR NODES ARE MARKED AS TESTED FOR THAT INPUT VECTOR
FAULTS
). / 1 1 1 1
!" : '3'$3$'"3"$"'3'$3$'"3"$"'3'$3$'"3"$"'3'$3$'"3"$"
  $ $ $ 5 $ $ $ 5 $ $ 5
  $ $ $ 5 5 $ . $ $ . 5 $
  5 $ $ $ 5 $ . $ $ $ $ 5
  $ $ 5 $ $ $ 5 $ $ $ $ $ $ $ 5
4ABLE  15)%4%34 $ETECTION -AP  &AULTS

3934%-3 3#)%.#% 
 #ELL "OUNDARY &AULT -ODEL
4HE #ELL "OUNDARY -ODEL MODELS INPUT AND OUTPUT STUCK AT FAULTS INPUT TO INPUT
BRIDGES AND INPUT TO OUTPUT BRIDGES &OR A TWO INPUT .!.$ GATE THERE ARE NINE
FAULTS 4HEY COVER MOST OF THE FAULTS COVERED BY THE 15)%4%34 MODEL 4HE RULE
FOR COUNTING A FAULT DETECTED FOR THE STUCK AT FAULTS IS THAT THE FAULTED NODE WHEN
TESTED MUST BE IN THE STATE OPPOSITE ITS STUCK VALUE &OR BRIDGING FAULTS THE IN
VOLVED NODES MUST BE AT OPPOSITE STATES  FAULT DETECTION IS ACHIEVED WITH IN
PUT VECTOR SETS [] [] AND [] %ACH CIRCUIT NODE IS A
FAULT OBSERVATIONDETECTION POINT FOR FAULT GRADING 4HE #ELL "OUNDARY -ODEL RE
QUIRES ONLY A LOGIC SIMULATOR TO GRADE )$$1 FAULTS )T DOES NOT USE SPECIAL FAULT LI
BRARY MODELS
#OMPARED TO THE 15)%4%34 MODEL THE #ELL "OUNDARY IS VERY SLIGHTLY MORE LENI
ENT &ORTUNATELY THE WORST CASE POSSIBILITY OF UNCOVERED 15)%4%34 FAULTS 1
3$ 1 3" AND 1 3$ NOT BEING DETECTED IS  WHILE ALL OF THE TRANSISTOR INTER
CONNECT FAULTS ARE COVERED 4ABLE   7ITH TESTS LIMITED TO JUST A FEW )$$1 VEC
TORS THE CHANCE OF HAVING THREE UNIQUE INPUT VECTORS FOR ANY ONE GATE IS LOW

!DVANTAGES OF THE CELL MODEL ARE  .O )$$1 LIBRARY REQUIREMENTS IT IS UNNECES
SARY TO KNOW THE INTERNAL STRUCTURE OF A CELL   !BILITY TO OPTIMIZE TEST VECTOR SE
LECTION MORE SIGNIFICANT FOR HIGH FAULT COVERAGE WITH FEW VECTORS THAN THE FAULT
MODEL TYPE  AND  #ELL BRIDGING FAULTS HAVE A HIGH PROBABILITY OF CORRELATING TO
REAL DEVICE DEFECTS

). / FAULTS
!" : ! ! " " : : !" :! :"
  $ $ $ $ $
  $ $ $ $ $
  $ $ $ $ $
  $ $ $ $ $
4ABLE  #ELL -ODEL &AULT -AP  &AULTS

 3934%-3 3#)%.#%
 $ESIGN #ONSIDERATIONS FOR )$$1 4ESTABILITY

(ERE ARE SOME COMMON )$$1 TESTABILITY PROBLEMS WITH OPTIONS TO OVERCOME SOME
OF THE LIMITATIONS

 -IXED 3IGNAL $ESIGNS

0ROVIDE SEPARATE POWER SUPPLY PINS AND RAILS FOR #-/3 ANALOG AND BIPOLAR SEC
TIONS OF THE DESIGN 4HIS ALLOWS )$$1 TO BE MEASURED ON THE #-/3 SECTION INDE
PENDENTLY OF THE OTHER SECTIONS !NALOG AND "IPOLAR CIRCUITS THAT CANNOT BE ISO
LATED FROM #-/3 CAN RENDER THE ENTIRE CIRCUIT )$$1 UNTESTABLE
6$$ 6 6#

#-/3 !NALOG "IPOLAR

&IGURE 

 3EPARATE #ORE ,OGIC FROM )/

4O AVOID LEAKAGE CURRENT FROM THE TESTER S LOADS SEE &IGURE  THROUGH THE $54 S
OUTPUT PINS TURN OFF THE TESTER S LOADS ADD BUFFERS TO $54 S OUTPUT PADS OR DIS
CONNECT $54 S OUTPUTS VIA RELAYS FOR )$$1 TESTS )NPUT PIN LEAKAGE IS INSIGNIFI
CANT )T IS GOOD PRACTICE TO HAVE SEPARATE 6$$ PINS TO SUPPLY CORE LOGIC AND )/
PADS

 !VOID 0ULLUPS0ULLDOWNS

7HENEVER POSSIBLE USE KEEPER LATCHES INSTEAD OF PULLUPSPULLDOWS 7HEN THEIR
USE IS UNAVOIDABLE
• #ONNECT THE PULL RESISTOR THROUGH A PASS TRANSISTOR THAT IS CONTROLLED BY A TEST
MODE SIGNAL

3934%-3 3#)%.#% 
• !T PRIMARY INPUT PINS TRY TO HAVE ONLY PULLUPS OR PULLDOWNS IN THE DESIGN &OR
NON COMPLEMENTARY INPUTS IMPLEMENTED WITH ONLY PULLUPS IT MAY BE POSSIBLE
TO TEST )331 THE RETURN SIDE OF THE 6$$ SUPPLY WITHOUT LOSS OF COVERAGE &OR
PULLDOWNS TEST )$$1 4HE CURRENT SINKSOURCE IN BOTH CASES IS FROM OUTSIDE OF
THE $54 AND BY MEASURING THE SUPPLY RAIL OPPOSITE THE RESISTOR SOURCE THE RE
SISTOR CURRENT IS BYPASSED 7HERE PULLUPS OR PULLDOWNS CANNOT BE EFFECTIVELY
DISABLED )$$1 CAN BE MEASURED ONLY WHEN THE PULLED NET IS IN THE SAME STATE
AS THE PULL RESISTOR IE FOR PULLUPS )$$1 CAN BE MEASURED ONLY WHEN THE
PULLED NET IS  

 #ONTROL &REE RUNNING /SCILLATORS

0ROVIDE TEST MODE ACCESS TO DISABLE FREE RUNNING OSCILLATORS

 !VOID #ONTENTION

• )F YOU MUST USE INTERNAL TRI STATE BUSES DESIGN A TEST MODE WITH WHICH THESE
BUSES CAN BE HELD IN A DRIVEN CONFIGURATION FOR )$$1 $O NOT DESIGN A CASE
WHERE MULTIPLE SEPARATE INTERNAL TRI STATE BUSSES ARE MUTUALLY EXCLUSIVE
• $O NOT ALLOW NODES TO FLOAT DUE TO ALL DRIVERS ON A TRI STATED BUS BEING TURNED
OFF $O USE BUS REPEATERS  KEEPER LATCHES TO HOLD VALUES WHEN THE BUS IS NOT
DRIVEN
• $O NOT ALLOW INTERNAL DRIVE FIGHTS DUE TO MULTIPLE ENABLED DRIVERS ON ONE BUS
$O MULTIPLEX THE DRIVER ENABLE PORTS TO INSURE THAT ONLY ONE DRIVER IS ACTIVE AT
ANY GIVEN TIME
• $O NOT ALLOW DEGRADED VOLTAGES SUCH AS THE RESULT OF USING AN N TRANSISTOR
SERVING AS A PASS GATE

 2!-
0ROVIDE TEST MODE TO DISABLE 2!- SPEED UP CURRENTS OR TO PUT 2!- IN STANDBY
MODE

 -ODELING )SSUES

• -ODEL PULLUPS STRUCTURALLY $O NOT USE BEHAVIORAL ASSIGNMENTS
• )DENTIFY LEAKY CONDITIONS FOR BEHAVIORAL MODELS

 3934%-3 3#)%.#%
 $EEP 3UB MICRON

 3CALING
2EDUCTION OF POWER SUPPLY VOLTAGES CAUSES REDUCED THRESHOLD VOLTAGES 4HIS RE
SULTS IN INCREASED OFF CURRENT 4HE OVERALL SCALING PROBLEMS CAUSE PROBLEMS BOTH
IN THE ABILITY TO TEST FOR )$$1 AND IN PRODUCT RELIABILITY 4ECHNOLOGY THAT EN
HANCES PRODUCT RELIABILITY ALSO TENDS TO ENHANCE )$$1 TESTABILITY SUCH AS 3/) 
$543S LESS THAN  MICRON AND WELL ABOVE - TRANSISTORS ARE SUCCESSFULLY )$$1
TESTED

 $ENSITY
&OR DESIGNS ABOVE - TRANSISTORS THE SUM OF EACH TRANSISTOR S LEAKAGE COULD AP
PROACH THE VALUE OF THE )$$1 TEST S THRESHOLD VALUE 0ARTITIONING THE DESIGN INTO
SMALLER SECTIONS EACH WITH SEPARATE POWER PINS CAN HELP TO AVOID THE LOSS OF
)$$1 SENSITIVITY

3934%-3 3#)%.#% 
 3UMMARY

 )$$1 IS A #OST %FFECTIVE -ETHOD FOR 4ESTING #-/3 #IRCUITS

4HIS METHODOLOGY CAN USE $ESIGN 6ERIFICATION SIMULATION RESULTS TO GENERATE HIGH
QUALITY TEST SETS 4HESE TESTS CAN EASILY BE DEVELOPED IN TIME TO TEST PROTOTYPE DE
VICES !S ILLUSTRATED IN &IGURE  )$$1 TESTS ARE CAPABLE OF DETECTING MORE DEFECTS
THAN ANY OTHER SINGLE TEST METHODOLOGY )DEALLY ALL OF THE TEST METHODS DISCUSSED
WILL BE IMPLEMENTED BUT SINCE THEIR ACTUAL IMPLEMENTATION MAY BE A SERIAL PROC
ESS OVERALL QUALITY IS ENHANCED BY STARTING WITH )$$1

 &EW 6ECTORS

-OST !3)# VENDORS WILL TEST   )$$1 TEST VECTORS FOR THEIR CUSTOMERS 4HE LONG
TEST TIME ASSOCIATED WITH )$$1 TESTS TENDS TO RESTRICT THE NUMBER OF TEST VECTORS
ALLOWED &ORTUNATELY )$$1 TESTS ARE CAPABLE OF ACHIEVING HIGH COVERAGE WITH FEW
VECTORS AS ILLUSTRATED IN &IGURE 

 !LL 6ECTORS

3OME CRITICAL APPLICATIONS REQUIRE ZERO DEFECT TEST METHODOLOGY &OR THESE AP
PLICATIONS WHERE TEST TIME IS NOT AN ISSUE ALL )$$1 QUALIFIED FUNCTIONAL TEST VEC
TORS ARE TESTED FOR )$$1

 4WO )$$1 6ECTOR 3ETS

3OME TEST PROGRAMS CONSIST OF TWO SETS OF )$$1 TESTS /NE HAS ONLY A FEW VECTORS
AND IS USED FOR PRODUCTION TESTS 4HE SECOND TEST USES MANY OR ALL VECTORS AND IS
USED FOR FAILURE ANALYSIS AND FAULT ISOLATION

 3UPPLEMENTAL 6ECTORS

)$$1 TEST VECTOR SETS ARE OFTEN SUPPLEMENTED BY TESTS GENERATED SPECIFICALLY TO
DETECT DEVICE FAILURES THAT HAVE ESCAPED ALL MANUFACTURING TEST !FTER DIAGNOSTIC
ANALYSIS THAT ISOLATES AND LOCATES THESE FAILURES TEST ENGINEERS CREATE SUPPLEMENTAL
TEST VECTORS

 3934%-3 3#)%.#%
 3YSTEMS 3CIENCE S 0OWER&AULT )$$1Ì
0OWER&AULT )$$1 IS A PUSH BUTTON )$$1 SOLUTION FOR 6ERILOG DESIGNS )T FINDS
NEAR OPTIMAL )$$1 VECTORS AND GENERATES DETAILED FAULT COVERAGE INFORMATION

0OWER&AULT )$$1 MODELS FAULTS AT THE CELL LEVEL ALLOWING IT TO WORK WITH 6ERILOG
LIBRARIES NETLISTS AND TESTBENCHES WITHOUT MODIFICATION )T IS ABLE TO BOTH READ AND
WRITE 6ERIFAULT OR :YCAD SEED FAULT LISTS )T USES THE SAME 6ERILOG SIMULATOR AS IS
USED FOR SIGN OFF VERIFICATION AND THE SAME SIGN OFF 6ERILOG !3)# LIBRARIES

+%9 "%.%&)43
• )NCREASE FAULT COVERAGE AND QUALITY
• &AST AND ACCURATE
• %ASY TO USE SIMPLY RUN THE 6ERILOG SIMULATOR
• (ANDLES ANY 6ERILOG CIRCUIT
• .O NEW LIBRARIES USES !3)# VENDOR S 6ERILOG LIBRARY

+%9 &%!452%3
• !UTOMATIC SEEDING OF STUCK AT AND BRIDGING FAULTS
• 3EEDS POST LAYOUT BRIDGING FAULTS
• 7ORKS WITH 3CAN AND .ON 3CAN DESIGNS
• .EW ALGORITHMS FIND NEAR OPTIMAL SET OF )$$1 VECTORS QUICKLY
• /PTIMAL TEST VECTOR SELECTION OVER SINGLE OR MULTIPLE TEST BENCHES
• #AN INCREASE COVERAGE BEYOND THAT OF OTHER )$$1 TOOLS
• ,INKS WITH 6ERILOG 8, AND MANY CLONES
• 'ENERATES DETAILED COVERAGE REPORTS
• #AN GENERATE HIERARCHICAL COVERAGE REPORTS
• )NTERACTIVE OR BATCH ANALYSIS MODE
• 2OBUST 6ERIFAULT AND :YCAD INTERFACES

3934%-3 3#)%.#% 
 /VERVIEW OF 0OWER&AULT )$$1
0OWER&AULT )$$1 IS LINKED WITH 6ERILOG 8, OR COMPATIBLE CLONES THROUGH THE
0,) 3INCE IT DOES NOT REQUIRE THAT ANOTHER SIMULATOR BE INTRODUCED TO THE DESIGN
ENVIRONMENT IT ELIMINATES THE NEED TO COMPARE RESULTS WITH ANOTHER SIMULATOR
4HIS SCHEME ASSURES ACCURACY IN SIMULATION AND ASSURES THE HIGHEST PROBABILITY
THAT THE )$$1 TOOL CAN PROPERLY IDENTIFY QUIESCENT TEST VECTORS
0OWER&AULT )$$1 IS EASY TO USE )T IS EXECUTED IN TWO STAGES
 )NSERT SSI?IDDQ SYSTEMS TASKS INTO A TOP LEVEL 6ERILOG MODULE 2UN YOUR
6ERILOG SIMULATION WITH THE NORMAL 6ERILOG TESTBENCH
 !FTER SIMULATION RUN THE )$$1 PROFILER )$$10RO )T CAN BE EXECUTED INTERAC
TIVELY OR IN BATCH MODE 4HE PROFILER ANALYZES OUTPUT PRODUCED BY THE
SSI?IDDQ TASKS AND SELECTS NEAR OPTIMAL )$$1 TEST VECTORS 4HE PROFILER
ALSO PRODUCES HIERARCHICAL FAULT COVERAGE REPORTS

!3)# OR #US
TOM ,IBRARY

SRPT
)$$10RO
$54 .ETLIST 3TROBES
6ERILOG 3IMULATOR 3TROBE
SELECTION AND
FAULT
COVERAGE
ANALYSIS FRPT
4EST "ENCHS &LT #OVERAGE
6ERILOG 4ASKS
SSI?IDDQ
3EED &AULTS AND
3TROBE 4IMING

0OWER&AULT )$$1 $ATA &LOW

 3934%-3 3#)%.#%
0OWER&AULT )$$1 IS %ASY TO 5SE
*UST ADD A FEW SYSTERMS TASKS
MODULE IDDQ
INITIAL BEGIN
SSI?IDDQ DUT TBENCHMBLOCK 
SSI?IDDQ SEED 3! TBENCHMBLOCK 
END

ALWAYS TBENCHSTROBE SSI?IDDQ STROBE?TRY 

ENDMODULE
2ICH SET OF OPTIONS INCLUDE
• #ELL BRIDGING FAULTS
• ,AYOUT BRIDGING FAULTS
• 3ELECTIVE HIERARCHICAL FAULT SEEDING
• 5SE 6ERILOG OR :YCAD FAULT SEED LISTS

0OWER&AULT )$$1 IS #OST EFFECTIVE

/THERS 0OWER&AULT )$$1

)NSTALL .EW 3IMULATOR  DAYS .O
,IBRARY $EVELOPMENT  -ONTHS .O
4RAINING  7EEKS 3ELF 4EACH
5SEABLE 2ESULTS  -ONTHS &IRST $AY

3934%-3 3#)%.#% 
V ERIFICATION & T EST S OLUTIONS
Are You Sure Your Design Is Verified For Tape Out?
ATTN: All Verilog, ASIC and Systems Designers, Foundries, and IP Developers...
Verify Correctness. Develop Testbenches Quickly. Catch Design Problems Early. Cycle
Based and Regular Timing. Avoid Verilog Re-Compiles Between Testbenches. Object
VERA Oriented Options. Mix and Match Verilog, Vera, C and C++.

Can You Afford Field Failures?

ATTN: All ASIC Designers, Test Engineers and Foundries...
Use Standard Verilog Libraries and Standard Verilog Simulators. “Bridging” and
“Stuck-At”Faults. Easy to Use. Unmodified Netlists and
POWERFAULT-IDDQ Libraries. Optimal Test Vectors. Increase Quality. Verifault
and Zycad Compatible.

Do You Have Too Many Waveform Displays?

ATTN: All EDA and Test Vendors and Internal CAD Groups...
Displays Digital, Mixed-Signal and Analog Data. Most Powerful Waveform Tool in EDA.
OEM’d and Supported by Industry Leaders such as Cadence, Mentor
SIMWAVE Graphics, Epic, Zycad, Precedence, Meta Software and Others. Standardize
Using SimWave with ISDB.

Does Your Simulator Crawl When You Dump Results?

ATTN: All EDA and Test Vendors and Internal CAD Groups...
Fastest and Most Compact Database. Support for Verilog, VHDL, Analog and
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