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Process Development and Optimization for 3 High Aspect Ratio Via-Middle

Through-Silicon Vias at Wafer Level

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DOI: 10.1109/TSM.2015.2485079

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454 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
Process Development and Optimization for 3 µm
High Aspect Ratio Via-Middle Through-Silicon
Vias at Wafer Level
Dingyou Zhang, Daniel Smith, Member, IEEE, Gopal Kumarapuram, Rudy Giridharan, Shinichiro Kakita,
Mohamed A. Rabie, Peijie Feng, Holly Edmundson, and Luke England
Abstract—This paper presents challenges encountered in the
fabrication of high aspect ratio (AR) via middle, through-silicon
vias (TSVs), of 3 µm top entrant critical dimension and 50 µm
depth. Higher AR TSV integration is explored due to the lower
stress and copper pumping influence of TSVs observed in adja-
cent CMOS devices. The key process improvements demonstrated
in this paper include 3 µm TSV etch, dielectric liner coverage,
metal barrier and seed layer coverage, and copper electroplating.
Index Terms—TSV, high aspect ratio, etch, electroplating,
KOZ, 3D.
I. I NTRODUCTION
HE USE of 3D stacking technology addresses the sus-
T tainability of higher bandwidth and lower latency by
maintaining both signal and power integrity of the dies when
stacked by Through-Silicon Vias (TSVs); thermal mechani-
cal and electrical impact on both dies and front end devices
are key criteria in determining AR of the integrated TSVs.
The stress impact of TSVs on front end devices, NFET and
PFET, is addressed in the industry when integrating TSVs
into a manufacturing baseline flow. Stress builds up in Si and
copper (Cu) during the additional thermal cycles in back end
of line (BEOL) as a coefficient of thermal expansion (CTE)
mismatch exists between Cu in the TSV and the silicon
substrate. This stress build up may propagate in the silicon
and the BEOL layers, impacting the performance of transis-
tors through mobility shifts as well as fracturing of the top
ULK and metal layers with TSV Cu pumping. TCAD sim-
ulations were performed to find an effective TSV diameter
that minimized the stress gradient between the TSV metal-
lization and oxide dielectric interface; 3μm diameter TSV
resulted in the minimum stress gradient between the Ta and Cu
interface. Reduced stress was observed with the 3um CD,
which allows for both increased density of TSVs, as well as
a lower Keep Out Zone (KOZ) for placement of front end
devices in the vicinity of the TSVs. This work demonstrates
Manuscript received June 22, 2015; accepted July 28, 2015. Date of
publication October 1, 2015; date of current version November 13, 2015.
(Corresponding author: Dingyou Zhang).
D. Zhang, D. Smith, G. Kumarapuram, R. Giridharan, S. Kakita,
M. A. Rabie, P. Feng, and L. England are with GlobalFoundries, Malta,
NY 12020 USA (e-mail: dingyou.zhang@globalfoundries.com).
H. Edmundson is with Nanometrics, Hillsboro, OR 97124 USA.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TSM.2015.2485079
0894-6507 c 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
successful gap fill of TSVs of 3μm entrant CD and 50um
depth with existing PVD Ta barrier and Cu seed metallization
processes.
3x50μm TSV introduced several processing challenges over
the current 6μm standard TSV. Since the TSV depth is main-
tained at 50μm, the higher AR causes difficulties in achieving
continuous TSV metallization and void free bottom-up filling.
These challenges were overcome through several experimen-
tal iterations using a test vehicle with < 0.1% TSV density,
which will be described in the following sections.
Cu pumping of the TSVs is another major reliability con-
cern. It is determined by the step height of the TSV Cu
compared to the field, measured after the TSV CMP step
(or potentially after BEOL processing). As Cu volume is
directly related to the extent of Cu pumping, TSV CD
is one of the key variables that can be adjusted to mini-
mize Cu pumping, and also reduce the overall stress applied
to the silicon. In the current example, a reduction in CD
from 6μm to 3μm results in a Cu volume decrease of
approximately 75%.
II. TSV M ODULE
A. TSV Formation and Metrology
Etch patterning to define the overall TSV layout was done
using a standard photoresist at roughly 4μm thickness. This
photoresist needs to provide sufficient resist margins during
the TSV etch and prevent any erosion of the underlying hard-
mask (HM) or middle of line (MOL) layer.
The TSV etch profile was developed on the Lam
Syndion C R
platform; the etching of the high AR TSV profile
was done using transformer coupled plasma. The DRIE (Deep
Reactive Ion Etch) was done using the Rapidly Alternating
Process (RAP) of etch and deposition, based on the BOSCH
method. The immediate result, when using the best known
method (BKM) process for the larger 6μm diameter TSV with
this higher aspect ratio via, showed that there were consider-
able barriers to its immediate use. Challenges to overcome
included etch stop, via striations, mask undercut, resist bud-
get, and HM erosion. These issues are highlighted in the cross
sections shown in Fig. 1.
To establish a baseline etch process for 3μm TSV, the
main factor in the evolution of the sidewall profile improve-
ment (targeting a straight profile) was optimizing the RAP
ZHANG et al.: PROCESS DEVELOPMENT AND OPTIMIZATION FOR 3 µm HIGH AR VIA-MIDDLE TSVs AT WAFER LEVEL
Fig. 1. Cross section images of the 3x50μm TSV at the top, middle, and
bottom areas highlighting initial defects seen using the existing BKM recipes
for larger TSV diameters.
phases with the right combination of etch, deposition, and clear
phases. The optimized combination eliminated undercut, Si
overhang, and via striations. A series of etches were conducted
from 3:1 to 20:1 AR. During these progressive iterations top
bowing was observed for profiles greater than 10:1 AR, which
can be observed in the series of cross sections shown in Fig. 2.
This was due to the reduction of the passivation as a function
of depth. The top bow was improved by decreasing the SF6
flow and peak pressure in the RAP cycles. The tapering of the
TSV sidewall was improved by linearly ramping the voltage
bias during the etch phase through the RAP cycles. The scal-
lop size after the RAP process was reduced by a post treatment
smoothening step.
Another two design of experiments (DOEs) were also car-
ried out to further improve 3μm TSV etch process. Table I
shows the DOE conditions for 3μm TSV post etch resist
retaining improvement. Four major factors including voltage
bias during RAP phase 1 (clear) and 3 (deposition), voltage
linear ramping conditions as well as C4 F8 gas flow during
RAP phase 2 (etch), were investigated. It has been found that
adding a C4 F8 gas flow during the etch phase helps to reduce
the resist erosion due to its polymerizing nature. In addition,
higher bias voltage gives ions more energy and assists the
ions in reaching the bottom of the TSV during both the clear
455
Fig. 2. Series of etch depths from 3:1 to 20:1 AR with 3μm diameter opening
using the 3μm BKM recipe. A gradual increase in bowing in the top entrant
of the TSV with increased depth was observed. Also notice the increase in
resist consumption with increased depth.
TABLE I
DOE FOR 3μm TSV P OST E TCH R ESIST R ETAINING I MPROVEMENT
and deposition phases. The optimized combination of 33%
higher bias voltage during clear phase, additional C4 F8 gas
flow during etch phase under voltage ramp up condition A,
and 25% higher bias voltage during deposition phase (DOE
condition #4) resulted in the most remaining resist, which was
used as a fixed baseline condition for the 2nd DOE to improve
3μm TSV post etch notch entrance and depth uniformity.
Table II shows the 2nd DOE conditions in which pre-coat
time and TCP power were explored as two major tuning factors
for post etch notching entrance and depth uniformity improve-
ment. The results showed that increasing pre-coat time after
HM opening before silicon etch can effectively help retain
photoresist on wafer surface during etch. However, increasing
TCP power resulted in less residual resist and a wider range
of TSV depths and final CD across the wafer. Fig. 3 shows
SEM images of TSV top entrance after etch without resist ash-
ing. With increased bias voltages, additional C4 F8 gas flow
and a longer pre-coat time (DOE condition #13), the full
FEOL/MOL film stack as well as more than 700nm thick
photoresist were retained, as shown in Fig. 3(b).
Silicon fin defects were also previously found at the TSV
bottom after DRIE, which may cause process and mechanical
failures during downstream processing and backside reveal-
ing. An example of the Si fin defect is shown in Fig. 4(a).
The presence of bulk micro defects (BMD) in the Si wafers
456 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
TABLE II
DOE FOR 3μm TSV P OST E TCH N OTCH E NTRANCE AND D EPTH
U NIFORMITY I MPROVEMENT
Fig. 3. Example SEM images of TSV top entrance (a) DOE condition
#4 with no photoresist remaining after etch, and (b) DOE condition #13 with
improved photoresist retaining and notch entrance after etch.
has been identified as a key root cause, as it serves as a micro
mask during etch and results in silicon fin defects at TSV
bottom [4]. A substrate with lower bulk micro defect (BMD)
density has been used in this work to eliminate the defect.
TSVs devoid of the Si fin defects at the bottom of the
TSV have been successfully obtained, which is desirable for
a robust 3μm TSV integration flow [4]. An example is shown
in Fig. 4(b).
The critical challenge in sub 3μm via measurement can be
best understood when considering the limits of the structure:
Fig. 4. Cross sections showing 3x50μm deep TSV bottom with (a) the
presence of a Si fin defect and (b) lack of Si fin defects due to use of lower
BMD Si.
at 3μm, the object is effectively under resolved optically.
Further, light returned from the system (effectively, a very
small aperture) is dramatically reduced compared to a lower
AR TSV. In this work, the metrology recipe was optimized
on the UniFireTM platform from Nanometrics. In lieu of stan-
dard phase analysis and optical processing methods, per pixel
height mapping is done using the intensity and phase compo-
nents of the reflected white light to a reference signal (where
reference signal is an ideal white light signal). The position
and strength of this correlation are extracted, and fit against
simplified assumptions of the via shape and size, this results
in a coarse map of the TSV profile. This map of correlation
location is iteratively optimized to find the best depth of fit.
The BCD and depth is similarly optimized against the correla-
tion strength at the nominal depth location. This iterative and
fit approach improved the robustness of the fit, extending our
capability to 3μm and aspect ratios greater than 16:1.
B. TSV Isolation Dielectric
The existing POR for 6μm TSV liner uses a CVD TEOS
liner. It includes two steps: an SACVD TEOS for liner process
with >80% step coverage and a PECVD cap to block moisture
absorption. This significantly aids in reducing the downstream
degas time for the PVD seed layer process. The following
points are key considerations for meeting the aggressive 3μm
TSV targets:
• An additional clean process prior to TSV isolation liner
deposition was integrated as a surface treatment of the TSV.
A hydrophilic surface was achieved by this pre-clean step
resulting in the improvement of TSV liner step coverage.
ZHANG et al.: PROCESS DEVELOPMENT AND OPTIMIZATION FOR 3 µm HIGH AR VIA-MIDDLE TSVs AT WAFER LEVEL
Fig. 5. Cross-sectional SEM images for a 3x50μm TSV after ALD dielec-
tric liner deposition: (a) ∼95nm thick film on TSV top, (b) ∼91nm thick
film on TSV middle sidewall, (c) ∼93nm thick film on TSV bottom corner,
and (d) ∼95nm thick film on TSV bottom.
• Due to the 3um diameter TSV opening, the risk for oxide
pinch-off is increased. To mitigate this risk, the TSV iso-
lation liner thickness was reduced, which was enabled by
the lack of sidewall scalloping in the dry etch process.
An alternative dielectric liner process was also developed
for 3μm TSV using an atomic layer deposition (ALD) pro-
cess. It was conducted in a batch furnace tool, which can load
up to 100 production wafers in addition to dummy wafers to
ensure processing uniformity at room temperature. The batch
ALD dielectric liner provides several advantages over existing
processes, including higher throughput, lower thermal budget,
inherently better step coverage and scalability which does not
require the additional surface treatment step prior to isolation
liner deposition. As a result, a thinner ALD dielectric liner
is needed compared to a CVD process, in order to achieve
the same film thickness at the TSV bottom. Fig. 5 shows the
conformal coverage of 100nm ALD dielectric liner for 3μm
TSV: the dielectric film thickness on TSV top field, sidewall
and bottom are all around 95nm. In addition, the batch ALD
process allows for a significant cost reduction of the overall
TSV module, which mainly attributes to the higher deposi-
tion throughput, reduced CMP processing time, and material
consumptions for the thinner dielectric liner removal, as well
as elimination of the additional clean process [5].
C. TSV Metallization
The TSV barrier and liner layers are typically deposited
using a PVD process for the current 6μm standard
457
TSV diameter. The barrier layer’s main purpose is to impede
the diffusion of Cu into the liner and Si substrate, and to pro-
vide a wetting surface for the seed layer. The seed layer’s
primary role is to provide an electrical contact, and provide
wetting for the plating solution during the electroplating TSV
fill process. Due to the reduced diameter of the TSV, the
atomic/ion flux at the TSV surface is lower, thereby reducing
sidewall and bottom coverage of the barrier and seed layers.
Ta is a widely used barrier for copper (Cu) diffusion, how-
ever the default bulk form of Tantalum (Ta) thin film (β phase)
is highly stressed and can cause warpage and manifest as
cracks post TSV CMP . To circumvent this, a thin layer of TaN
is laid prior to Ta film deposition to promote a lower stressed
α phase in the Ta layer. The nitrogen concentration was opti-
mized to allow for the best α phase formation in the Ta. A Cu
seed is then deposited over the Ta barrier with a thickness that
is tuned to accommodate void free plating parameters.
In addition to acting as a diffusion barrier, the barrier layer
also seems to impart a certain amount of resistance that affects
the plating process. Since the amount of sidewall and bottom
coverage by the barrier is grossly reduced for PVD deposition
with increasing AR, the resistance increases drastically, which
may slow or impede the plating process. Partial fill defects
were observed when the barrier thickness at the bottom corner
of the TSV was too low, as shown in Fig. 6. The thin barrier
and seed films could easily get dissolved into the high acid
concentration Cu bath used for TSV plating, which leads to
those filling failures. However when the barrier thickness was
increased, the TSVs exhibited complete fill.
Both the Ta and Cu layers were successfully deposited using
standard PVD processing techniques, effectively scaling the
current process technology to a smaller TSV diameter and
higher AR.
For the current 3x50μm TSV size, the existing electro-
chemical plating (ECP) process for the 6μm diameter TSV
was used with no special adjustments made to either the tool
parameters or Cu chemistry components. In a high volume
manufacturing scenario, this is critical as a single ECP bath
can be maintained for multiple TSV sizes, lowering overall
processing costs. An example of a void free 3x50μm TSV
can be seen in Fig. 7. It should also be mentioned that the
successful bottom-up fill was achieved using the 2 times thick
barrier and seed layers, in order to provide the required cur-
rent density and sufficient chemical resistance in high acid Cu
plating bath for ECP processing.
Following the electroplating fill process, a standard anneal
was performed at 430◦ C for 30min. These processing condi-
tions have been shown as ideal for minimizing Cu pumping
following the planarization and BEOL processing [6].
D. TSV Planarization
As previously described, in order to ensure sufficient side-
wall coverage at the TSV bottom, both the Ta barrier and
Cu seed thicknesses were increased. The result is a potential
negative impact on CMP removal of these layers; increased
polish times and wafer level stress. The longer polish times
act to induce a higher temperature during the CMP processing,
effectively causing an increase in the removal rate of the
materials. This, in turn, can result in increased dishing and
458 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
Fig. 6. TSV voids observed prior to optimization of the Ta barrier layer PVD
deposition. Voids typically occur roughly 10% from bottom of TSV depth,
which is a typical “blind spot” for the PVD processing.
Fig. 7. Cross section showing successful bottom-up filling of multiple
3x50μm TSVs in a dense pattern of 10μm pitch.
higher chance for across wafer non-uniformity, or other Cu
etching defects (cracks, voids, side slits, recess, etc.).
To achieve successful TSV seed and barrier layer planariza-
tion, the following points must be considered:
• Longer polish time may increase the possibility of
scratching.
Fig. 8. Cross section of TSV post TSV CMP showing successful landing
on hardmask with no erosion.
• Ta/Cu removal rate will become higher due to increased
temperature during processing.
• Oxide and Nblok removal rate will result in no change,
resulting in a selectivity shift between the dielectric and
Cu materials.
In order to meet the final planarization requirements with the
additional challenges imparted by the 3μm TSV dimensions,
the CMP process was optimized. Processing parameter adjust-
ments were made that minimized the effects of increased tem-
perature and dielectric/Cu selectivity issues with no changes
in hardware as shown in Fig. 8.
III. TSV S TRESS I MPACT
TCAD simulations were conducted to understand the effect
of reduction of the TSV diameter on copper pumping as well
as on the probability of delamination between Cu and the
surrounding diffusion barrier following a high temperature
annealing process. In the simulations, copper was assumed
to be a nonlinear material where both plastic and creep effects
were taken into account. Other materials in the structure were
considered to be elastic. The simulated anneal conditions were
430◦ C temperature for a time of 20 min.
Additional simulations were conducted to understand the
effect of diffusion barrier material on delamination. The
amount of strain energy released due to a crack between
the Cu and barrier material can be represented by the J inte-
gral (energy release rate). A higher J integral value predicts
that a higher amount of strain energy will be released due to
a delamination event. Therefore, as the J integral increases, the
likelihood that delamination between the materials will occur
also increases. Since Ti is also a common barrier/adhesion
material in the semiconductor industry, it was compared to
Ta in these simulations.
Results predict a higher vertical stress for the 6x55μm TSV
compared to the 3x50μm TSV, as shown in Fig. 9(a) and (b)
respectively. This is indicated by the wider spread of the
red color (stress >300MPa) in the 6x55μm TSV case. Final
TSV integration with a minimal stress impact on NFET and
PFET device performance is desired for final yield, which
ZHANG et al.: PROCESS DEVELOPMENT AND OPTIMIZATION FOR 3 µm HIGH AR VIA-MIDDLE TSVs AT WAFER LEVEL
Fig. 9. Mechanical simulation results for (a) 6x55μm TSV and (b) 3x50μm
TSV structures.
Fig. 10. Cu pumping simulation results and schematic comparing 6x55μm
and 3x50μm TSV structures.
translates into a low KOZ for improved layout capabilities.
These TCAD simulations for a 6x55μm TSV structure predict
negligible effect on threshold voltages and drain currents for
20nm devices, and match well with measured transistor perfor-
mance values [6]. The 3x50μm TSV structure is predicted to
have a similarly negligible impact on device performance, and
the final transistor characterization measurements to validate
are ongoing.
459
TABLE III
S UMMARY OF M ECHANICAL S IMULATION R ESULTS
The severity of Cu pumping is expected to be lower for the
3μm diameter TSV due to a reduction in overall Cu volume
present. Simulations predict a roughly 36% reduction in Cu
pumping height by moving from a 6x55μm to 3x50μm TSV
structure with a Ta barrier, which is illustrated in Fig. 10.
When comparing to the results of the Ti barrier simulations,
an increase in Cu pumping is predicted for a Ti barrier of
equivalent thickness.
In contrast to the increased Cu pumping for a Ti bar-
rier material, the propensity for delamination is decreased
for a Ti barrier when compared to a Ta barrier. When com-
paring the calculated J integral value, the Ti barrier case
has a 10-12% lower probability of delamination. The overall
simulation results are summarized in Table III.
IV. C ONCLUSION
Using a 3x50μm TSV test vehicle, we have successfully
demonstrated key processing aspects of a high AR TSV to
support further scaling from the current POR of 6x55μm TSV
dimensions. Although there were several processing challenges
to overcome, the existing 3D TSV toolset was able to be
used. Results of this series of evaluations showed no negative
impacts of the TSV diameter scaling. The following points
highlight key enabling adjustments that were made:
• A higher bias voltage was used during both clear and
deposition phases, an additional C4 F8 gas flow was used
during etch phase, and a longer pre-coat time was used
after HM opening for 3x50μm TSV etch for the consid-
eration of photoresist retaining, notch entrance, and depth
uniformity improvement.
• The TSV dielectric liner field thickness was reduced
to prevent pinch-off at the opening during ECP filling.
Even with the reduced thickness, there was good side-
wall coverage at the TSV bottom. An alternative ALD
dielectric liner process was also developed for 3x50μm
TSV, which allows for a thinner film due to its conformal
coverage.
• Barrier and liner metal layer field thicknesses were
increased (i.e., longer deposition time) to compensate
for reduced PVD sidewall coverage at the bottom of
high aspect ratio features. Overall sidewall thickness was
lower, however.
• No change was made to the ECP filling process. Current
delivery was sufficient with the thinner barrier and seed
layers.
460 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 4, NOVEMBER 2015
•
CMP processing parameters were adjusted to compensate
for new dielectric and barrier/seed layer thicknesses on
the wafer surface.
Mechanical stress simulations were also completed that
predict a reduction in Cu pumping and stress applied to
the surrounding transistors with a shift to 3μm diameter
TSV. The replacement of Ta barrier metal with Ti barrier metal
was included in the simulations, and results suggest a larger
severity of Cu pumping, but lower propensity for sidewall
delamination. This combination of increased and decreased
benefits will require further investigation to determine if Ti is
a more appropriate barrier metal than Ta.
ACKNOWLEDGMENT
The authors would like to thank the physical failure analysis
group at GlobalFoundries for their supports on cross-sectional
SEM and FIB imaging.
R EFERENCES
[1] A. Redolfi et al., “Implementation of an industry compliant, 5 × 50μm,
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pp. 1348–1388.
[2] E. Beyne, “Electrical, thermal and mechanical impact of 3D TSV
and 3D stacking technology on advanced CMOS devices—Technology
directions,” in Proc. 3DIC, Osaka, Japan, 2012, pp. 1–6.
[3] W. Guo et al., “Copper through silicon via induced keep out zone
for 10nm node bulk Fin-FET CMOS technology,” in Proc. IEDM,
Washington, DC, USA, 2013, pp. 12.8.1–12.8.4.
[4] D. Zhang et al., “BMD impact on silicon fin defect at TSV bottom,”
Electron. Lett., vol. 50, no. 13, pp. 954–956, Jun. 2014.
[5] D. Zhang et al., “Room temperature ALD oxide liner for TSV
applications,” in Proc. IEEE Electr. Compon. Technol. Conf. (ECTC),
San Diego, CA, USA, 2015, pp. 59–65.
[6] M. A. Rabie et al., “Novel stress-free keep out zone process develop-
ment for via middle TSV in 20nm planar CMOS technology,” in Proc.
IEEE Int. Interconnect Technol. Conf. Adv. Metall. Conf. (IITC/AMC),
San Jose, CA, USA, 2014, pp. 203–206.
Dingyou Zhang received the B.S. degree in
electronic engineering from Tsinghua University,
Beijing, China, in 2008, and the M.S. and Ph.D.
degrees in electrical engineering from Rensselaer
Polytechnic Institute, Troy, NY, USA, in 2010 and
2013, respectively. Since 2013, she has been with
GlobalFoundries packaging development organiza-
tion, where she is currently a Principal Engineer,
focusing on 3-D/TSV development for advanced
technology nodes.
Daniel Smith (M’01) received the B.S. degree
in computer and electrical engineering from the
Georgia Institute of Technology in 2004, and the
M.S. degree in microelectronic engineering from
the Rochester Institute of Technology in 2012.
From 2004 to 2010, he was an Electrical Engineer
with Phillips-Gradick Engineer and Merrick &
Company, working on architectural and construc-
tion electrical design. From 2010 to 2012, he
was a Research Assistant on integrated multide-
vice MEMS fabrication and testing. Since 2012, he
has been a Process Integration Engineer with GlobalFoundries, Malta, NY,
USA. His focus is with TSV module integration and process development for
both manufacturing readiness at the 28, 20, and 14 nm, as well with devel-
opment for TSV scaling into advanced nodes. He also works on 3-D-CPI,
bumping processing, and packaging reliability for overall 3-D packaging
applications.
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Gopal Kumarapuram received the B.E. degree in
electronics and telecommunications from Mumbai
University in 2009 and the M.S. degree in electrical
engineering from Boston University in 2012.
He spent the summer of 2010 with Stanford
University, pursuing courses in macroeconomics
and international finance. From 2011 to 2012,
he was a Research Assistant with the Photonics
Center, Boston University, focusing on develop-
ing a digital processing system. Since 2012, he
has been a Process Engineer of Etch Module with
GlobalFoundries, Malta, NY, USA. He has been developing the high aspect
ratio etch for the through silicon via process for different nodes of the
technology. He also works on BEOL etch specializing in aluminum etch.
Rudy Giridharan, photograph and biography not available at the time of
publication.
Shinichiro Kakita received the B.S. and M.S.
degrees in electrochemistry from Keio University,
Japan, in 1994 and 1996, respectively.
From 1996 to 2000, he was a CVD Process
Engineer with NEC Corporation, Japan, working
mainly on the development of DRAM capaci-
tance films. From 2000 to 2013, he was a CMP,
Electro Plating, and Wet Etch Process Engineer with
RENESAS Electronics, working on 40–130 nm pro-
cess development. During that time, his focus was
STI, Cu interconnect, and UBM process develop-
ment. Since 2013, he has been a CMP Process Engineer with GlobalFoundries,
Malta, NY, USA. His focus is process development and improvement for
CuCMP including TSV CMP for 20 and 14 nm process.
Mohamed A. Rabie received the B.Sc. degree
(Hons.) in computer engineering from Ain Shams
University, Cairo, Egypt, in 2000, and the M.A.Sc.
degree in electrical engineering from McMaster
University, Hamilton, ON, Canada, in 2005.
From 2005 to 2008, he was a Teaching Assistant
with the Electrical and Computer Engineering
Department, McMaster University. He joined
Synopsys Inc., as a Technology Computer Aided
Design (TCAD) Engineer in 2008. Since 2012, he
has been with GlobalFoundries, where is currently
a TCAD Engineer and a member of the Thermo-Mechanical Modeling
Team. He has authored one book, ten articles, and two inventions. His
research interests include kinetics of semiconductor reaction (e.g., oxidation,
silicidation, and germanidation) and the electrical and the mechanical
behavior of through silicon vias.
Mr. Rabie was a recipient of the Best Paper Award of the IEEE
International Interconnect Technology Conference in 2015, the Outstanding
Team Award from Synopsys Inc., in 2011, and the Outstanding Thesis Award
from McMaster University in 2005.
Peijie Feng, photograph and biography not available at the time of publication.
Holly Edmundson, photograph and biography not available at the time of
publication.
Luke England received the B.S. degree in materials
engineering and the M.S. degree in materials science
and engineering from Iowa State University in 2002
and 2004, respectively. He has developed packaging
technologies encompassing a wide range of disci-
plines for companies including Micron Technology
and Fairchild Semiconductor. In 2012, he began
working for GlobalFoundries, Malta, NY, USA, as
an on-site assignee to IMEC, Belgium, as part of
the 3-D development program, where his current
responsibility is leading the TSV and 3-D packaging
development team.