PART A:

1. State duality property

2. Find the complements for the following functions F1 =xy'+x'y F2 =(xy+y'z+xz)x
3. Reduce the Boolean Expression AB'C+A'BC+ABC
4. State Demargan’s Theorem.
5. Simplify F=A'B'C+BC+AC
6. Complement the following expression F=(x+y'+z)(x'+z')(x+y)
7. What is priority encoder?
8. Design a single bit magnitude comparator to compare two words A and B.
9. Write any four applications of multiplexer.
10. Design the combinational circuit with 3 inputs and 1 output. The output is 1 when the
binary value of the inputs is less than 3.The output is 0 otherwise.
11. What is the difference between decoder and demultiplexer.
12. Draw the truth table for full subtractor.
13. Differentiate Flip-Flop from Latches.
14. Draw the excitation table and state diagram for JK and SR Flip-Flop.
15. Draw the timing diagram showing the output of a 2 stage synchronous counter with
respect to its clock signal.
16. What is the drawback of SR flipflop. How is this minimized?
17. Distinguish between combinational and sequential logic circuits.
18. What is race around condition? How it is eliminated it?
19. What are the models used to represent clocked sequential circuits. Mention their
differences.
20. What is universal shift register?
PART B & PART C
UNIT I:
1. If AB'+A'B=C, Show that AC'+A'C=B
2. Express the Boolean Function as (i) POS Form (ii) SOP form.
D = (A'+B) (B'+C)
3. Using K map method, obtain the minimal Sum of Product Expression
F(A,B,C,D) = ∑m(0,2,4,5,8,14,15) + ∑d(7,10,13)

4. convert (i) (5C8)16 = (??)2 (ii) (54A)16 = (??)10

(iii) (1AF)16 = (??)8 (iv) (1275)8 = (??)16

5. Realize the following switching function using a multilevel gate network. Also, obtain
the logically equivalent multilevel NAND-NAND gate circuit
Y=A + (B+C') . (D'E+F)
6. Find the minimal Sum of Product for the Boolean Expression
Y=∑(1,2,3,7,8,9,10,11,14,15) using Quine MC cluskey method.
7. Using tabulation method to simplify the Boolean function
F(A,B,C,D)=∑(1,2,3,5,9,12,14,15) which has the don’t care conditions d(4,8,11)
8. Simplify ABC+A'BC+AB'C+ABC'+AB'C'+A'BC'+A'B'C'
9. Using K map method, obtain the minimal Sum of Product Expression
Y=∑m(0,2,4,5,6,7,8,10,11,12,14,15)
10. Using K map method, obtain the minimal Product of Sum Expression
Y=∏M(0,2,3,5,7,8,10,11,14,15)
Implement Boolean expression for EXOR gate using NAND and NOR gates.

11. Realize the following function using K-map and implement with NAND gates
Y = ∑m(0,1,2,5,6,7,8,9,10,14)
12. Simplify the expression F(A,B,C,D)=∑m(0,2,3,5,7,8,10,11,15)+ ∑d(1,4,9) using Quine
Mc-Cluskey method.
13. What is the advantage of using Tabulation method? Determine the prime implicants of
the following function using Tabulation method F(A,B,C,D)=∑(1,4,6,7,8,9,10,11,15)

UNIT II:

1. Design half adder and Full adder circuits with necessary diagram.
2. Implement the Boolean function using 8:1 Multiplexer.
F(W, X, Y, Z)= ∑m (0,2,6,10,11,12,13)+∑d(3,8,14)
3. Write short notes on 4 bit ripple carry adder with neat sketch.
4. Explain the operation and need of Priority Encoder.
5. Design a 4 bit Magnitude Comparator to compare two 4 bit numbers.
6. Design a 4 bit BCD adder using full adder and explain its structure and compute the
circuit to add 1001 and 0101. Write the sum and carry output of the given binary
number.
7. With neat circuit diagram, explain the working principle of octal to binary encoder
8. Analyse the combinational circuit shown in figure below to determine the truth table
and the Boolean expressions governing the outputs of the circuit.

9. Construct a 16 x 1 multiplexer with two 8 x 1 multiplexer. Use block diagrams.

10. Explain the operation of 3:8 decoder with necessary diagrams.
11. Explain the operation BCD Adder with necessary diagrams.
12. Design half subtractor and Full subtractor circuits with necessary diagram.
13. Implement the Boolean function using 4:1 Multiplexer
F(A,B,C,D)=∑( 1,2,3,6,7,8,11,12,14)
14. Explain in detail about carry look ahead adder with necessary diagrams
15. Construct a 4 to 16 line decoder with five 2 to 4 line decoders with enable.
UNIT III

1. Design a synchronous counter using JK flipflops to count the following sequence.

1-3-15-5-8-2-0-12-6-9
2. Design the sequential circuit specified by the following state diagram using T
flipflop.

3. Explain the operation of T flip flop with necessary diagrams.

4. Realize JK flipflop using D flipflop.
5. Explain the different types of shift registers with neat diagram.
6. Design a decade counter using JK Flipflops .
7. Design a clocked sequential machine using JK flip flops for the state diagram shown
in figure. Use state reduction if possible and make proper state assignment.

8. Explain the operation of Ring counter

9. What is the idea behind master slave JK Flipflop?
10. Design a synchronous counter which counts in the sequence 0,2,6,1,7,5,0……using
JK flipflops. Draw the logic diagram and state diagram.