Department of Electronics and Communication Engineering

National Institute of Technology, Patna.

Effective from academic year 2016 -2017.
Specialization: M.Tech in Microelectronics & VLSI System Design
Course Structure
S.No Sem Course Course Name TH/ L T P Credit Cumm
Code PT Credit
1. 1 EC661 MOS Device Physics and Modeling TH 3 0 0 3
2. 1 EC662 Analysis and Design of Digital TH 3 0 0 3
Integrated Circuits
3. 1 EC6XX Elective - I TH 3 0 0 3
4. 1 EC6XX Elective - II TH 3 0 0 3
5. 1 EC6XX Elective - III TH 3 0 0 3
6. 1 EC663 Digital Design Lab PT 0 0 6 4
Total 15 0 6 19 19

7. 2 EC664 Analysis and Design of Analog TH 3 0 0 3

Integrated Circuits
8. 2 EC6XX Elective - IV TH 3 0 0 3
9. 2 EC6XX Elective - V TH 3 0 0 3
10. 2 EC6XX Elective - VI TH 3 0 0 3
11. 2 EC6XX Elective – VII TH 3 0 0 3
12. 2 EC665 Analog – Mixed Signal Lab PT 0 0 6 4
13. 2 EC691 Seminar 0 0 3 2
Total 15 0 9 21 40

14. 3 EC692 Seminar & Comprehensive Viva 0 0 3 2

15. 3 EC693 Dissertation (to be continued in 4th 0 0 0 8
sem.)
Total 0 0 0 10 50

16. 4 EC694 Seminar & Comprehensive Viva

Voce 0 0 3 2
17. 4 EC695 Dissertation 0 0 0 10
Total 0 0 0 12 62
Total Credits: 19 + 21 + 10 + 12 = 62. L: Lectures, T: Tutorials, P: Practical, C: Credits
List of Courses in Electives (Microelectronics & VLSI)
S.No Course Course Name TH/ L T P Credit
Code PT
1 EC671 VLSI and MEMS Technology T 3 0 0 3
2 EC672 Semiconductor Materials, Devices T 3 0 0 3
& Characterization
3 EC673 Low Power VLSI Design T 3 0 0 3
4 EC675 Clean Room Technology and T 3 0 0 3
Maintenance
5 EC676 ULSI Technology T 3 0 0 3
6 EC677 VLSI Physical Design T 3 0 0 3
7 EC678 VLSI Mixed Signal Design T 3 0 0 3
8 EC679 DSP in VLSI T 3 0 0 3
9 EC680 CAD for VLSI T 3 0 0 3
10 EC681 Testing and Testability T 3 0 0 3
11 EC682 VLSI DSP Architectures T 3 0 0 3
12 EC683 Hardware/Software Co-Design T 3 0 0 3
13 EC684 Hardware Description Languages T 3 0 0 3
14 EC685 FPGA Design T 3 0 0 3
15 EC686 Full Custom Design T 3 0 0 3
16 EC687 ASIC System Design T 3 0 0 3
17 EC688 GaAs Technology T 3 0 0 3
18 EC689 Formal Verification T 3 0 0 3
19 EC690 RF IC Design T 3 0 0 3
20 EC696 MEMS & Microsystems T 3 0 0 3
21 EC697 Organic Electronics T 3 0 0 3
22 EC698 Physical Design Automation T 3 0 0 3
23 EC699 Embedded System Design T 3 0 0 3
24 EC700 Nanoscale Devices T 3 0 0 3
25 EC701 Advanced VLSI Interconnects T 3 0 0 3
26 EC702 Semiconductor Device Modeling T 3 0 0 3
27 EC703 MEMS and NEMS Technology T 3 0 0 3
28 EC704 VLSI Architecture T 3 0 0 3
 Detailed Syllabus

1. EC661 MOS Device Physics and Modelling 3 0 0 3

Pre-requisite: Basic knowledge in Semiconductor physics/devices.

Objectives: The course will provide adequate understanding of semiconductor devices and
their modeling aspects, useful for designing devices in electronic, and optoelectronic
applications.

Sl. Contents Contact

No. Hours
1. MOS Capacitor: Energy band diagram of Metal-Oxide-Semiconductor
contacts, Mode of Operations: Accumulation, Depletion, and Inversion,
1D Electrostatics of MOS, Depletion Approximation, CV characteristics 5
of MOS, LFCV and HFCV.
2. Non-idealities in MOS, oxide fixed charges, interfacial charges, Midgap 5
gate Electrode, Poly-Silicon contact, inversion layer quantization,
quantum capacitance.
3. Physics of MOSFET: Energy Band Diagram(E-K) of Silicon, Concept of
effective mass, fermi and quasi-fermi levels, Drift-Diffusion Approach for
IV, Gradual Channel Approximation, Sub-threshold current and slope, 10
Body effect, Detail 2D effects in MOSFET, High field and doping
dependent mobility models, High field effects and MOSFET reliability
issues (SILC, TDDB, & NBTI).
4. Leakage mechanisms in thin gate oxide, High-K-Metal Gate MOSFET 6
devices and technology issues, MOSFET capacitances and resistances,
properties of junction and ohmic & schottky contact, tunneling, fowler-
nordheim tunneling, direct tunneling
5. MOS Scaling: Basic physics of MOS transistors scaling, charge sharing
effect (CSE), narrow and reverse narrow width effect, SCE, DIBL, GIDL, 6
mobility degradation due to gate field, hot electron effect and velocity
saturation, channel in-homogeneity, velocity overshoot, tunneling through
oxide.
6. SOI MOSFET: FDSOI and PDSOI, 1D Electrostatics of FDSOI MOS,
VT definitions, Back gate coupling and body effect parameter, IV 6
characteristics of FDSOI-FET, FDSOI-sub-threshold slope, Floating body
effect.
7. Advanced MOSFETs: Strain Engineered Channel materials, Mobility in 4
strained materials, Electrostatics of double gate, and Fin-FET devices
Total 42

Suggested Books:
Sl. Name of Books/ Authors Year of
No. Publication
1. S.M. Sze & Kwok K. Ng, Physics of Semiconductor Devices, Wiley 2007
Yuan Taur & Tak H. Ning, Fundamentals of Modern VLSI Devices,
2. Cambridge 2013
Mark Lundstrom & Jing Guo, Nanoscale Transistors: Device Physics,
3. Modeling & Simulation, Springer 2006
4. Yannis Tsividis, Operation and Modeling of the MOS Transistor, Oxford
University Press 2010
5. J. P. Colinge “FinFET and other multi-gate transistors” Springer 2008
5. Research papers from specific area

2. EC662 Analysis and Design of Digital Integrated Circuits 3 0 0 3

Pre-requisite: Knowledge of Digital Circuits.

Objectives: To acquaint the students with the fundamental concepts of digital VLSI circuit
design
Sr. No Contents Contact Hours

1 Review of MOSFET operation and CMOS process flow: RC model 4

for interconnects, transmission lines, CMOS process flow, Layout and
design rules.
2 CMOS inverter: Static characteristics, power consumption, dynamic 8
behavior, timing analysis, buffer design using the method of logical
effort, CMOS layout.
3 Combinational logic: Transistor sizing in static CMOS logic gates, 6
static CMOS logic gate sizing considering method of logical effort,
dynamic logic, pass-transistor logic, common mode and other cross-
coupled logic families.
4 Sequential logic: Static latches and flip-flops (FFs), dynamic latches 8
and Ffs, sense-amplifier based FFs, NORA-CMOS, Schmitt trigger,
monostable and astable circuits.
5 Memories and array structures: MOS-ROM, SRAM cell, memory 6
peripheral circuits, signal to noise ratio, power dissipation.
6 Course Project: SPICE based project on a digital VLSI sub-system 4
design.
7 Timing issues: Timing fundamentals, clock distribution, jitter, self- 6
timed circuit design, synchronizers and arbiters, basic building blocks
of PLLs, clock synthesis and synchronization using PLLs. Logic
synthesis for pipelining.
TOTAL 42

Sl. Name of Books/ Authors Year of

No. Publication
1 Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital 2016
Integrated Circuits: A Design Perspective,” Prentics Hall
2 Sung-Mo Kang, Yusuf Liblebici, “CMOS Digital Integrated Circuits,” 2003
Tata Mc Graw Hill
3 R. Jacob Baker, “CMOS Mixed-Signal Circuit Design,” Wiley India Pvt. 2009
Ltd.

4 Ivan Sutherland, R. Sproull and D. Harris, “Logical Effort: Designing 1999

Fast CMOS Circuits”, Morgan Kaufmann

6. EC663 Digital Design Lab 0 0 6 4

Pre-requisite: Nil
Objectives: To provide hands-on experience on circuit simulation and layout for digital
circuits.
Module 1: CMOS inverters -static and dynamic characteristics, CMOS NAND, NOR and XOR
Gates, Layout design and simulation.
Module 2: Static and Dynamic CMOS design- Domino and NORA logic – combinational and
sequential circuits, Method of Logical Effort for transistor sizing –power consumption in CMOS
gates.
Module 3: Arithmetic circuits in CMOS VLSI - Adders- multipliers- shifter –CMOS memory
design - SRAM using Hspice/VHDL/Verilog.
Module 4: Layout Design and Synthesis of Intel 4004 on HDL.
Module 5: Design and simulation of 32 bits MIPS processor.

Reading:
1. Jan M Rabaey, Digital Integrated Circuits, 2nd Edition, Pearson Education, 2003.
2. Sung-Mo Kang, CMOS Digital Integrated Circuits, 3rd Edition, McGraw-Hill, 2003.
3. Pedroni, Volnei A., Circuit Design and Simulation with VHDL 2nd Edition, MIT Press
4. R. Jacob Baker , Harry W. Li , David E. Boyce CMOS (Circuit Design, Layout, and Simulation)
Prentice-Hall of India Private Ltd. 2003.
5. J. Bhasker “A VHDL Primer” 3rd Edition, Pearson, 2015.
7. EC664 Analysis and Design of Analog Integrated Circuits 3 0 0 3

Pre-requisite: Analog Electronics

Objectives: To acquaint the students with basic CMOS analog building blocks and analog
sub-system design.
Sr. No Contents Contact Hours

1 Necessity and advantages of CMOS Analog Circuits; review of 3

MOSFETs; their characteristics and models; components available in
MOS technology: MOS capacitor.
2 Overview of MOS amplifiers and their analysis; analysis of typical 8
MOS circuits using square law; frequency response, bandwidth
enhancement; MOS bias circuits; various types of current mirrors
(Simple , Wilson, modified Wilson and cascode); differential amp:
linear range; diff amp with active load biased with current source: Gm,
Rout; Diff. To single ended converter; output stage and level shifting
stage.
3 Op-amp architectures: CMOS op-amps; two stage CMOS op-amp 8
architectures; calculation of overall gain and rout; determination of
dominants poles; compensation and relocation of poles and zeros;
other CMOS op-amp architectures. Gilbert cell.
4 CMOS OTAs and transconductors: CMOS OTA-linear range and 3
transconductance; linearized CMOS OTSs-single ended and
differential.
5 MOSFET-C integrated filters; MOS fully differential integrator, 3
derivation of MOSFET-C biquads based on conventional op-amp RC
biquads.
6 Nonlinearity cancellation in MOS Analog Circuits : basic topologies 7
for non-linearity cancellation using one, two and four matched
mosfets; exemplary circuits for realising linear grounded / floating
CMOS voltage- controlled oscillators.
7 Introduction to MOS translinear and square root domain circuits. 2

8 High performance CMOS op-amp LNLV op-amp/ Differential op- 8

amp. VCO: Architechture, basic function, Block Design.
Stability and frequency compensation, multipole systems, Phase
margin.
TOTAL 42
Reading:
1. Behzad Razavi, Design of Analog CMOS integrated circuits, McGraw Hill Co. Inc., 2013
2. Banu and Tsividis, MOS Analog Circuits for Telecommuunication and signal processing.
3. Douglas R. Holberg, Phillip E. Allen, CMOS Analog Design, 3rd Edition, 2013.
4. Paul R. Gray , Paul J. Hurst , Stephen H. Lewis , Robert G. Meyer Analysis and Design of Analog
Integrated Circuits, 5th Edition, 2009.

11. EC665 CMOS Analog Design Lab 0 0 6 4

Pre-requisite: Nil
Objectives: To provide hands-on experience on spice circuit simulation and layout for
analog circuits.

Cycle 1:
Lambda calculation for PMOS & NMOS, FT calculation, Transconductance plots, Single
transistor amplifier, Ideal current source, PMOS current source, NMOS saturated load,
Degenerative resistor, Cascade amplifier: Ideal current source, PMOS current source.
Cycle 2:
Current sinks: Basic current sink, Current sink with negative feedback, Bootstrap current sink,
Cascode current sink, Regulated cascode current sink.
Current sources: Basic current source, Current source with negative feedback, Bootstrap
current source, Cascade current source, Regulated cascade current source,
Current mirrors: Basic current mirror, Wilson current mirror, Cascode current mirror,
Regulated cascade current mirror, Widlar current source.
Differential amplifier, two stage Operational amplifier design
Op-amp design and various architectures

Reading:
1) Pr Gray and Rg Meyer, Analysis and Design of Analog Integrated Circuits, 5th Edition,
Wiley, 2009.
2) Mohammed Ismail and Terri Fiez, Analog VLSI: Signal and Information Processing,
McGraw-Hill, 1994.
3) Geiger, Allen and Stradder, VLSI Design Techniques for Analog and Digital Circuits, Tata
McGraw-HillEducation,2010.
4) David A johns, Ken Martin, Analog Integrated Circuit Design, Wiley, 2008.
5) R. Gregorian and G.C Ternes, Analog MOS Integrated Circuits for Signal Processsing, Wiley,
1986.
6) Roubik Gregorian, Introduction to CMOS OpAmp and Comparators, Wiley, 1999.
7) Alan Hastlings, The art of Analog Layout, Wiley, 2005.
 Detailed Syllabus of Electives

1. EC671 VLSI and MEMS Technology 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge of various processes and techniques for VLSI fabrication
technologies.

Sl. No. Contents Contact

Hours
1. Introduction to VLSI technology: Device scaling and Moore’s law, 4
basic device fabrication methods, alloy junction and planar process.
2. Crystal growth: Czochralski and Bridgman techniques, Characterization 5
methods and wafer specifications, defects in Si and GaAs.

3. Oxidation: Surface passivation using oxidation. Deal-Grove model, oxide 5

characterization, types of oxidation and their kinematics, thin oxide
growth models, stacking faults, oxidation systems.
4. Diffusion and ion-implantation: Solutions of diffusion equation, diffusion 7
systems, ion implantation technology, ion implant distributions,
implantation damage and annealing, transient enhanced diffusion and
rapid thermal processing.
5. Epitaxy and thin film deposition: Thermodynamics of vapor phase 6
growth, MOCVD, MBE, CVD, reaction rate and mass transport limited
depositions, APCVD/LPVD, equipments and applications of CVD,
PECVD, and PVD.
6. Etching: Wet etching, selectivity, isotropy and etch bias, common wet 4
etchants, orientation dependent etching effects; Introduction to plasma
technology, plasma etch mechanisms, selectivity and profile control
plasma etch chemistries for various films, plasma etch systems.
7. Lithography: Optical lithography contact/proximity and projection 5
printing, resolution and depth of focus, resist processing methods and
resolution enhancement, advanced lithography techniques for nanoscale
pattering, immersion, EUV,electron, X-ray lithography.
8. MEMS Processes: Surface micro-machining, bulk micro-machining, 6
LIGA, an-isotropic etching, MEMS Structures and devices.
Total Contact Hours 42

Suggested Books:
Sl. Name of Authors / Books / Publishers Year of
No. Publication/Reprint
1. Plummer, J.D., Deal, M.D. and Griffin, P.B., “Silicon VLSI 2000
 Technology: Fundamentals, Practice and Modeling”, 3rd Ed.,
Prentice-Hall.
2. Sze, S.M., “VLSI Technology”, 4th Ed., Tata McGraw-Hill. 1999
3. Chang, C.Y. and Sze, S.M., “ULSI Technology”, McGraw-Hill. 1996
4. Gandhi, S. K., “VLSI Fabrication Principles: Silicon and Gallium 2003
Arsenide”, John Wiley and Sons.
5 Campbell, S.A., “The Science and Engineering of Microelectronic 1996
Fabrication”, 4th Ed., Oxford University Press.

2. EC675 Clean Room Technology and Maintenance 3 0 0 3

Pre-requisite: Nil
Objectives: The course will provide understanding the cleanroom standards and ancillary
clean rooms.

Introduction, Cleanroom Classification Standards, Unidirectional air flow cleanroom,

Basis of Clean room standards, Federal Standards 209 ,ISO standard 14644-
1:1999,Cleanroom classification(Pharmaceutical, cleanrooms)
Design of Turbulently Ventilated and Ancillary Cleanrooms, Mini environments, isolators
and RABS, Containment zone, Construction and clean build, Design of Unidirectional
Cleanrooms.
High Efficiency Air filtration, Particle removal mechanisms, testing of high efficiency
filters.
Cleanroom Testing and Monitoring, Principles of cleanroom testing, Testing in relation
to room type and occupation state, Monitoring of cleanroom.
Measurement of Air Quantities and Pressure Differences, Air movement control,
Recovery test methods, Cleanroom containment leak testing.
Filter Installation leak testing, Operating a clean room, Materials, equipment and machinery,
Clothing, masks and gloves, cleaning a cleanroom.

Reading:
1. William White, Cleanroom Technology: Fundamentals of Design, Testing and
Operation, 2nd Edition, Wiley, 2010.
2. Matts Ramstorp, Introduction to Contamination Control and Cleanroom Technology,
Wiley, 2008.
3. Wani-Kai Chen (editor), The VLSI Hand book, CRI/IEEE press, 2000.
 3. EC676 ULSI Technology 3 0 0 3

Pre-requisite: Nil
Objectives: The course will provide understanding the transmission electron microscopy
and fabrication issues of ULSI devices.

Microelectronics and microscopy, ULSI process technology, Application of TEM for

construction analysis, TEM sample preparation techniques.
Ion implantation and substrate defects, Dielectrics and isolation, Silicides, polycide and
salicide, Metallization and interconnects.
TEM in failure analysis, Novel devices and materials, TEM in under bump metallization
and advanced electronics packaging technologies, High – resolution TEM in
microelectronics.
ULSI devices I: DRAM cell with planar capacitor, ULSI devices II: DRAM cell with
stacked capacitor, ULSI devices III: DRAM cell with trench capacitor, ULSI devices IV:
SRAM.

Reading:
1. C. Y. Chang, S.M. Sze, ULSI Technology, McGraw-Hill, 2000.
2. Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu, ULSI Semiconductor Process Technology
Atlas, John Wiley & Sons, 2003.

4. EC672 Semiconductor Materials, Devices & Characterization 3 0 0 3

Pre-requisite: Nil
Objectives: To provide a thorough knowledge of semiconductor materials, devices and
their characterization.

Pre-requisite: Nil
Objectives: To provide a thorough knowledge of semiconductor materials, devices and
their characterization.

Sl. Contents Contact

No. Hours
1. Semiconductor Material: Group III, Group IV, Group V, Crystal structure, 4
intrinsic and doped crystals, excess carriers and current transport.
2. Band structure of semiconductors: Band structure, carrier energy and 6
Fermi distributions for free carriers, donor and acceptor impurities,
determination of band gap, impurity ionization, and critical temperatures for
intrinsic ionization and onset of impurity deionization.
3. Inhomogeneous impurity distribution: Impurity diffusion processes and 4
profile derivations, built-in electric field and carrier profiles.
4. Junction diode: p-n junction, quasi Fermi levels, depletion width 6
capacitance and its application in doping profile determination, I-V
characteristics of narrow and wide base diodes and their equivalent circuits,
breakdown mechanisms, small signal ac impedance.
5. Bipolar transistor fundamentals: Formation of transistor, current gains, dc 6
and low frequency characteristics, base resistance and power gain, drift and
graded base transistors.
6 Surface field effect transistors: Surface states, measurement of surface 6
charge, Q-V/I-V characteristics and equivalent circuit models of MOS
capacitor and MOSFET. Four probe method, Study of CV at low and high
frequencies.
7 Metal-semiconductor junctions: Rectifying and ohmic contacts, role of 6
surface states, application in energy level characterization; Comparison of
p-n junction and Schottky diodes.

8 Pressure effects: Dependence of energy bandgap on pressure, evaluation of 4

energy pressure coefficients, direct-indirect conversion and identification of
defect levels.

Total 42

Sl. Name of Authors / Books / Publishers Year of

No. Publication/Reprint
1. Rabaey, J.M., Chandrakasan, A. and Nikolic B., “Digital 2016
Integrated Circuits: A Design Perspective”, 2nd Ed., Pearson.

2. Kang, S. and Leblebici, Y., “CMOS Digital Integrated Circuits: 2003

Analysis and Design”, Tata McGraw-Hill.
3. Pucknell, D.A. and Eshraghian, K., “Basic VLSI Design”, 3rd 1994
Ed., Prentice-Hall of India.

4. Eshraghian, K., Pucknell, D.A. and Eshraghian, S., “Essentials 2005

of VLSI Circuit and System”, 2nd Ed., Prentice-Hall of India.
5 Hodges, D.A., Jackson, H.G. and Saleh, R.A., “Analysis and 2005
Design of Digital Integrated Circuits in Deep Submicron
Technology”, 3rd Ed., Tata McGraw-Hill.

6 Uyemera, P.J., “Introduction to VLSI Circuits and Systems”, 2003

4th
Ed., John Wiley & Sons.
 5. EC677 VLSI Physical Design 3 0 0 3

Pre-requisite: EC662
Objectives: To develop understanding of state-of-the-art tools and algorithms, which
address design tasks such as floor planning, module placement and signal routing for VLSI
logic and physical level design.

Sl. Contents Contact

No. Hours
1. Introduction: Layout and design rules, materials for VLSI fabrication, basic
algorithmic concepts for physical design, physical design processes and 2
complexities.
2. Partition: Kernigham-Lin’s algorithm, Fiduccia Mattheyes algorithm, 6
Krishnamurty extension, hMETIS algorithm, multilevel partition techniques.
3. Floor-Planning: Hierarchical design, wirelength estimation, slicing and non- 10
slicing floorplan, polar graph representation, operator concept, Stockmeyer
algorithm for floorplanning, mixed integer linear program.
4. Placement: Design types: ASICs, SoC, microprocessor RLM; Placement 8
techniques: Simulated annealing, partition-based, analytical, and Hall’s
quadratic; Timing and congestion considerations.
5. Routing: Detailed, global and specialized routing, channel ordering, channel 12
routing problems and constraint graphs, routing algorithms, Yoshimura and
Kuh’s method, zone scanning and net merging, boundary terminal problem,
minimum density spanning forest problem, topological routing, cluster graph
representation.
6. Sequential Logic Optimization and Cell Binding: State based optimization, 4
state minimization, algorithms; Library binding and its algorithms, concurrent
binding
Total 42

Suggested Books:

Sl. Name of Books/ Authors Year of

No. Publication
1. Sarrafzadeh, M. and Wong, C.K., “An Introduction to VLSI Physical 1996
th
Design”, 4 Ed., McGraw-Hill.
2. Wolf, W., “Modern VLSI Design System on Silicon”, 2nd Ed., Pearson 2000
Education.
3. Sait, S.M. and Youssef, H., “VLSI Physical Design Automation: Theory and 1999
Practice”, World Scientific.
4. Dreschler, R., “Evolutionary Algorithms for VLSI CAD”, 3rd Ed., Springer 2002
5. Sherwani, N.A., “Algorithm for VLSI Physical Design Automation”, 2nd 1999
Ed., Kluwer.
6. Lim, S.K., “Practical Problems in VLSI Physical Design Automation”, 2008
Springer.

6. EC678 VLSI Mixed Signal Design 3 0 0 3

Pre-requisite: Nil
Objectives: To develop understanding of layout techniques with least interference among
digital and analog subsystems, should be able to design a complete mixed signal system that
includes efficient data conversion and RF circuits with minimizing switching and phase
noise, jitter.

Simple CMOS Current Mirror, Common-Source Amplifier, Source-Follower, Source-

Degenerated Current Mirrors, cascode Current Mirrors, MOS Differential Pair and Gain
StageProcess and temperature independent compensation, Ahuza’s compensation,
nested miller compensation, dynamic offset cancellation techniques. Basic Building
Blocks, OpAmp, Capacitors, Switches, Non-overlapping Clocks, Basic Operation and
Analysis, Resistor Equivalence of a Switched Capacitor, Parasitic-Sensitive Integrator ,
Parasitic-Insensitive Integrators, Signal-Flow-Graph Analysis, Noise in Switched-
Capacitor Circuit

Performance of Sample-and-Hold Circuits, Testing Sample and Holds, MOS Sample-

and-Hold Basics, Examples of CMOS S/H Circuits, Bipolar and BiCMOS Sample-and-
Holds, Translinear Gain Cell, Translinear Multiplier, Comparator Specifications Input
Offset and Noise , Hysteresis, ,Using an OpAmp for a Comparator, Input-Offset Voltage
Errors, Charge-Injection Errors, Making Charge-Injection Signal Independent ,
Minimizing Errors Due to Charge-Injection, speed of Multi-Stage Comparators, Latched
Comparators, Latch-Mode Time Constant, Latch Offset, Examples of CMOS and
BiCMOS Comparators, Input-Transistor Charge Trapping, Examples of Bipolar
Comparators,

Ideal D/A Converter, Ideal A/D Converter, Quantization Noise, Deterministic Approach,
Stochastic Approach, Signed Codes, Performance Limitations, Resolution, Offset and
Gain Error, Accuracy and LinearityIntegrating Converters, Successive-Approximation
Converters, DAC-Based Successive Approximation, Charge-Redistribution A/D,
Resistor-Capacitor Hybrid, Speed Estimate for Charge-Redistribution Converters, Error
Correction in Successive-Approximation Converters

Multi-Bit Successive-Approximation, Algorithmic (or Cyclic) A/D Converter, Ratio-

Independent Algorithmic Converter, Pipelined A/D Converters, One-Bit-Per-Stage
Pipelined Converter,1.5 Bit Per Stage Pipelined Converter, Pipelined Converter Circuits,

Basic Phase-Locked Loop Architecture, Voltage Controlled Oscillator, Divider

Phase Detector, Loop Filer, The PLL in Lock, Linearized Small-Signal Analysis,
Second-Order PLL Model , Limitations of the Second-Order Small-Signal Model, PLL
Design Example, Jitter and Phase Noise, Period Jitter , P-Cycle Jitter, Adjacent
Period Jitter, other Spectral Representations of Jitter, Probability Density Function
of Jitter, Ring Oscillators , LC Oscillators , phase Noise of Oscillators, jitter and
Phase Noise in PLLS

Reading:
1) David A Johns, Ken Martin: Analog IC design, Wiley 2008.
2) R Gregorian and G C Temes: Analog MOS integrated circuits for signal processing,
Wiley 1986
3) Roubik Gregorian: Introduction to CMOS Op-amps and comparators, Wiley, 2008

7. EC679 DSP in VLSI 3 0 0 3

Pre-requisite: EC 661
Objectives: To provide knowledge on transformations for high speed VLSI digital signal
processing using pipelining, retiming, and parallel processing techniques.

Sl. Contents Contact

No. Hours
1. Introduction to DSP Systems: Typical DSP programs, Area-speed-power 2
tradeoffs, Representation methods of DSP systems
2. Iteration Bound: Iteration, Iteration period, Iteration bound, Algorithms to 4
compute iteration bound – Longest path matrix, Minimum cycle matrix
3. Pipelining and Parallel Processing: Introduction to pipelining and parallel 5
processing, Pipelining of FIR digital filters, Parallel processing, Pipelining and
parallel processing for low power
4. Retiming: Retiming formulation, Retiming for clock period minimization, K- 4
slow transformation, Retiming 2-slow graph
5. Unfolding: Algorithm for unfolding, Properties of unfolding, Application of 6
unfolding, Sample period reduction, Word and bit-level parallel processing
6. Folding: Folding technique, Folding transformation, Retiming for folding 4
7. Fast Convolution: Introduction, Cook-Toom algorithm and modified Cook- 6
Toom algorithm, Winograd algorithm and modified Winograd algorithm,
Iterated convolution, Cyclic convolution, Design of Fast convolution
algorithm by inspection.
8. Algorithmic Strength Reduction in Filters and Transforms: Introduction, 6
Parallel FIR filters, Two-parallel and three-parallel low-complexity FIR filters,
3-parallel fast FIR filter, Parallel filter algorithms from linear convolutions,
Discrete Cosine Transform and Inverse DCT.
9. Pipelined and Parallel Recursive and Adaptive Filters: Introduction, Pipeling 5
in 1st order IIR digital filters, Pipelining in higher order IIR digital filters,
Parallel processing for IIR filters, Combined pipeling and parallel processing
for IIR filters.
Total 42

Suggested Books:

Sl. Name of Books/ Authors Year of

No. Publication
1. Parhi, Keshab K., “VLSI Digital Signal Processing Systems: Design and 1999
Implementation”, John Willey & Sons.
2. John G. Proakis, Dimitris Manolakis: Digital Signal Processing: 2006
Principles, Algorithms and Applications, 4th ed, Pearson.
3. Sen M. Kuo, Woon-Seng Gan: Digital Signal Processors: 2005
Architectures, Implementations, and Applications, Prentice Hall.

8. EC680 CAD for VLSI 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge on layout techniques in IC and algorithms required for
circuit simulators

Introduction: Evolution of design automation; CMOS realizations of basic gates.

Circuit and system representation: Behavioral, structural and physical models,
design flow.
Modeling techniques: Types of CAD tools, introduction to logic simulation and synthesis.
HDL: Syntax, hierarchical modeling, Verilog/VHDL construct, simulator directives,
instantiating modules, gate level modeling.
Delay modeling: Event based and level sensitive timing control, memory initialization,
conditional compilation, time scales for simulation.
Advanced modeling techniques: Static timing analysis, delay, switch level modeling,
user defined primitive (UDP), memory modeling.
Logic synthesis: Logic synthesis of HDL construct, technology cell library, design
constraints, synthesis of Verilog/VHDL construct.
Model optimization: Various optimization techniques, design size.
FPGAs based system design: Commercial FPGA architecture, LUT and routing
architecture, FPGA CAD flow; Typical case studies.
Suggested Books:

1. Weste, N. and Eshraghian, K., “Principles of CMOS VLSI Design –A Systems Perspective”, 2nd
Ed., Addison Wesley. 2006
Palnitkar, S., “Verilog HDL”, 2nd Ed., Pearson Education. 2004
Wolf, W., “Modern VLSI Design: System on Chip”, 2nd Ed., Prentice Hall of India. 2002

9. EC681 Testing and Testability 3 0 0 3

Pre-requisite: Nil
Objectives: Upon completion of this course, students will be able to understand the VLSI
chip testing mechanism, systems using existing test methodologies, equipments, and tools.

Sl. Contents Contact

No. Hours
1 Motivation for testing, Design for testability, the problems of digital and 5
analog testing, Design for test, Software testing.
Faults in Digital Circuits: Controllability, and Observability, Fault
models – stuck-at faults, Bridging faults, intermittent faults.
2 Digital Test Pattern Generation: Test pattern generation for 7
combinational logic circuits, Manual test pattern generation, Automatic
test pattern generation - Roth's D- algorithm, Developments following
Roth's D algorithm, Pseudorandom test pattern generation, Test
pattern generation for sequential circuits, Exhaustive, non-exhaustive
and pseudorandom 70 test pattern Generation, Delay fault testing.
3 Testability Techniques: Partitioning and ad-hoc methods and scan- 10
path testing, Boundary scan and IEEE standard 1149.1, Offline built in
Self Test (BIST), Hardware description languages and test.
4 Testing of Analog and Digital circuits: Testing techniques for Filters, 12
A/D Converters, Programmable logic devices and DSP, Test
generation algorithms for combinational logic circuits – fault table,
Boolean difference, Path sensitilization, D- algorithm, Podem, Fault
simulation techniques – serial single fault propagation,Deductive,
Parallel and concurrent simulation, Test generation for a sequential
logic, Design for testability – adhoc and structured methods, Scan
design, Partial scan, Boundary scan, Pseudo-random techniques for
test vector generation and response compression, Built–in-Self test,
PLA test and DFT.
5 Memory Design and Testing: Memory Fault Modeling, testing, And 8
 Memory Design For Testability And Fault Tolerance RAM Fault
Modeling, Electrical Testing, Peusdo Random Testing-Megabit DRAM
Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault
Modeling and Testing-Application Specific Memory Testing.

Reading:

Sl. Name of Books/ Authors Year of

No. Publication
1. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing 2005
for Digital, Memory,and Mixed-Signal VLSI Circuits, Kluwer
Academic Publishers.

A.K Sharma, Semiconductor Memories Technology, Testing and

2. Reliability, IEEE Press. 2002

10. EC682 VLSI DSP Architectures 3 0 0 3

Pre-requisite: Nil
Objectives: Upon completion of this course, students will be able to understand effective
algorithm design to integrated circuit implementations.

Essential features of Instruction set architectures of CISC, RISC and DSP processors
and their implications for Implementation as VLSI Chips, Micro programming
approaches for implementation of control part of the processor. Assessing
understanding performance: Introduction, CPU performance and its factors, evaluating
performance, real stuff: Two spec bench marks and performance of recent INTEL
processors, fallacies and pitfalls.
Data path and control: Introduction, logic design conventions, building a data path, a
simple implementation scheme, a multi cycle implementation, exceptions, micro
programming: simplifying control design, an introduction to digital design using
hardware description language, fallacies and pitfalls.
Enhancing performance with pipelining: An overview of pipelining, a pipe lined data
path, pipe lined control, data hazards and forwarding, data hazards and stalls, branch
hazards, using a hard ware description language to describe and model a pipe line,
exceptions, advanced pipelining: extracting more performance, fallacies and pitfalls
Computational accuracy in DSP implementations: Introduction, number formats for signals
and coefficients in DSP systems, dynamic range and precision, sources of errors in DSP
implementations, A/D conversion errors, and DSP computational errors, D /A conversion errors.
Architectures for programmable digital signal processing devices: introduction, basic
architectural features, DSP computational building blocks, bus architecture and memory, data
addressing capabilities, address generation unit, programmability and program execution,
speed issues, features for external interfacing.

Reading:
1. D.A, Patterson And J.L. Hennessy, Computer Organization and Design: Hardware / Software
Interface, 4th Edition, Elsevier, 2011.
2. A.S. Tannenbaum, Structured Computer Organization, 4th Edition, Prentice-Hall, 1999
3. W. Wolf, Modern VLSI Design: Systems on Silicon, 2nd Edition, Pearson Education, 1998
4. KeshabParhi, VLSI digital signal processing systems design and implementations, Wiley 1999
5. Avatar sigh, Srinivasan S, Digital signal processing implementations using DSP
microprocessors with examples, Thomson 4th reprint, 2004.

11. EC683 Hardware – Software Co-Design 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge on Model data flow and implement the same through
software and hardware.

The Nature of Hardware and Software: Introducing Hardware/Software Co-design, The

Quest for Energy Efficiency, The Driving Factors in Hardware/Software Co-design, The
Dualism of Hardware Design and Software Design. Data Flow Modeling and
Transformation: Introducing Data Flow Graphs, Analyzing Synchronous Data Flow
Graphs, Control Flow Modeling and the Limitations of Data Flow, Transformations.
Data Flow Implementation in Software and Hardware: Software Implementation of Data
Flow, Hardware Implementation of Data Flow, Hardware/Software Implementation of
Data Flow.
Analysis of Control Flow and Data Flow: Data and Control Edges of a C Program,
Implementing Data and Control Edges, Construction of the Control Flow Graph4.4
Modern Bipolar, Transistor Structures, Construction of the Data Flow Graph.
Finite State Machine with Datapath: Cycle-Based Bit-Parallel Hardware, Hardware
Modules, Finite State Machines with Datapath, FSMD Design Example: A Median
Processor
System on Chip: The System-on-Chip Concept, Four Design Principles in SoC Architecture, SoC
Modeling in GEZEL. Applications: Trivium Crypto-Coprocessor, CORDIC Co-Processor.

Reading:
1. Patrick Schaumont, A Practical Introduction to Hardware/Software Co-design,
Springer, 2010.
2. Ralf Niemann, Hardware/Software Co-Design for Data flow Dominated Embedded
Systems,
Springer, 1998.

12. EC684 Hardware Description Languages 3 0 0 3

Pre-requisite: Nil
Objectives: Upon completion of this course, students will be able to Differentiate sequential
language and concurrent language.

Introduction: About VHDL, Design Flows & EDA Tools, Code Structure, Data types,
Operators and Attributes: Operators, Attributes, User-Defined Attributes, Operator,
overloading
Concurrent Code: Concurrent versus Sequential, Using Operators, WHEN, Generate
and Block.
Sequential Code: Process, Signals and Variables, IF, WAIT, CASE, Using Sequential,
Code To Design Combinational Circuits
State Machines: Introduction, Design Style #1, Design Style #2 (Stored Output),
Encoding Style: From Binary to OneHot
Introduction to Verilog-AMS: Verilog Family of Languages, Mixed Signal Simulators,
Applications of Verilog-AMS, Analog Modeling. Language Reference: Basics, Data
Types, Signals, Expressions, Analog Behavior

Reading:
1.Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd Edition, MIT Press,
2010.
2. Kenneth S Kundert, Olaf Zinke, Designers Guide to Verilog AMS, Springer, 2004.

13. EC685 FPGA Design 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge to Implement parameterized library cell design.

Introduction to FPGAs: Design and implementation of FPGA, Evolution of

programmable devices, Application of FPGA.
Design Examples Using PLDs Design of Universal block, Memory, Floating point
multiplier, Barrel shifter.
Special Purpose Processors Programming technologies, commercially available
FPGAs, Xilinx’s Vertex and Spartan, Actel’s FPGA, Altera’s FLEX 10k.
Logic Block Architectures: Logic block functionality versus area-efficiency, Logic
block area and routing model, Impact of logic block functionality on FPGA performance,
Model for measuring delay.
Case Study – ACTEL FPGA

Reading:
1. John V. Old Field, Richrad C. Dorf, Field Programmable Gate Arrays, Wiley, 2008.
2. Michel John Sebastian Smith, Application Specific Integrated Circuits, Addison Wesley
Professional, 2008.
3. Stephen D. Brown, Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic, Field
Programmable Gate Arrays, 2nd Edition, Springer, 1992.

14. EC686 Full Custom Design 3 0 0 3

Pre-requisite: EC 662
Objectives: Upon completion of this course, students will understand efficient Layout
design techniques and Design layouts for minimizing stress effects.

Introduction: Schematic fundamentals, Layout design, Introduction to CMOS VLSI

manufacturing processes, Layers and connectivity, Process design rules Significance of
full custom IC design, layout design flows.
Advanced techniques for specialized building blocks: Standard cell libraries, Pad
cells and Laser fuse cells, Advanced techniques for building blocks, Power grid Clock
signals and Interconnect routing.
Interconnect layout design, Special electrical requirements, Layout design techniques to
address electrical characteristics.
Layout considerations due to process constraints: Large metal via
implementations, Step coverage rules, Special design rules, Latch-up and Guard rings,
Constructing the pad ring, Minimizing Stress effects.
Proper layout: CAD tools for layout, Planning tools, Layout generation tools, Support
tools.

Reading:
1. Dan Clein, CMOS IC Layout Concepts Methodologies and Tools, Newnes, 2000.
2. Ray Alan Hastings, The Art of Analog Layout, 2nd Edition, Prentice Hall, 2006

15. EC687 ASIC System Design 3 0 0 3

Pre-requisite: EC 662
 Objectives: Upon completion of this course, students will be able to Identify new
developments in SOC and low power design.

Introduction, Types of ASIC’s Design Flow, CMOS Logic. ASIC Library Design,
Transistor Parasitic Capacitance, Input Slew Rate, Library-Cell Design, Library
Architecture. Programmable ASICs, The Antifuse Metal Antifuse, Static RAM, EPROM
and EEPROM Technology, Practical Issues.

Programmable ASIC Logic Cells, Actel, Xilinx LCA., XC3000 CLB, XC4000 Logic Block,
XC5200 Logic Block, Xilinx CLB Analysis, Logic Expanders. Programmable ASIC I/O
Cells, Totem-Pole Output, Mixed-Voltage Systems, Metastability, Xilinx I/O Block.
Boundary Scan.
Programmable ASIC Interconnect and Programmable ASIC Design Software. Actel
ACT, RC Delay in Antifuse Connections, Xilinx EPLD Logic Synthesis, FPGA Synthesis,
Third-party Software, low level design entry, logic synthesis, simulation.

Test and ASIC construction, VHDL, Verilog HDL, Logic Synthesis, Simulation.

Reading:
1. Michel John Sebastian Smith, Application Specific Integrated Circuits, Addison
Wesley Professional, 2008.
2. HimanshuBhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler, 2nd
Edition, Kluwer Academic, 2001.

16. EC673 Low Power VLSI Design 3 0 0 3

Pre-requisite: Nil
Objectives: Low power Design techniques will be discussed.

Introduction, Sources of Power Dissipation, Static Power Dissipation, Low Static/Dynamic

Power Techniques, Pass-Transistor Logic Families
Standard Adder Cells, CMOS Adders Architectures, Parallel Adder.
Types Of Multiplier Architectures, Parallel Multiplier, Braun, Booth and Wallace Tree
Multipliers and their performance comparison, Sources of power dissipation in SRAMs, Low
power SRAM circuit techniques, Sources of power dissipation in DRAMs, Low power VLSI
design methodology - LP Physical Design, LP Gate-Level Design, LP Architecture-Level
Design, Algorithmic-Level power Reduction.

Reading:
1. J. Rabaey, “Low Power Design Essentials” Springer, 2009
2. Kiat Seng Yeo and Kaushik Roy, Low- Voltage, Low-Power VLSI Subsystems,
Edition 2009, Tata Mc Graw Hill
3. Soudris D, Piguet C and Goutis C, Designing CMOS Circuits for Low Power, Kluwer
Academic Publishers, 2002
Reference Book: Jan Rabaey, Low Power Design Essentials, Springer

17. EC688 GaAs Technology 3 0 0 3

Pre-requisite: EC 661
Objectives: To provide knowledge to understand low power arithmetic circuits and systems
using GaAs Technology.

Non-Silicon MOSFET Technology: Introduction, Brief and Non-Comprehensive History

of the NSMOSFET, Surface Fermi Level Pinning: The Bane of NSMOSFET,
Technology Development

Properties and Trade-Offs of Compound Semiconductor MOSFETs: Simulation

Framework, Power-Performance Trade-offs in Binary III-V Materials (GaAs, InAs, InP
and InSb) vs. Si and Ge, Power-Performance of Strained Ternary III-V Material (Inx
Ga1−xAs), Strained III-V for p-MOSFETs. Device Physics and Performance Potential of
III-VField-Effect Transistors: InGaAs HEMTs

Theory of Hfo2-Based High-K Dielectric Gate Stacks: Methodology of DFT Simulations

of High-k Oxides on Semiconductor Substrates, DFT Simulations of High-k Oxides on
Si/Ge Substrates.

Materials and Technologies for III-V MOSFETs: Introduction, III-V HEMTs for Digital
Applications, Challenges for III-V MOSFETs, and Mobility in Buried Quantum Well
Channel.
Atomic-Layer Deposited High-k/III-V Metal-Oxide-Semiconductor Devices and Correlated
Empirical Model: History and Current, Empirical Model for III-V MOS, Experiments on High-k/III-
V MOSFETs, Technology/Circuit Co-Design for III-V FETs.

Electrical and Material Characteristics of Hafnium Oxide with Silicon Interface Passivation on III-
V Substrate for Future Scaled CMOS Technology: Introduction, MOSCAPs and MOSFETs on GaAs
with Si, SiGe Interface Passivation Layer (IPL), MOSCAPs and MOSFETs on InGaAs with Si IPL,
MOSCAPs and Self-Aligned n-channel MOSFETs on InP, Channel Materials with Si IPL.

Reading:
1. Serge Oktyabrsky, Peide D. Ye, Fundamentals of III-V Semiconductor MOSFETs,
Springer,
2010.
2. C.Y. Chang, Francis Kai, GaAs High-speed Devices, Physics Technology and Circuit
Applications, John Wiley, 1994.
 18. EC689 Formal Verification 3 0 0 3

Pre-requisite: Nil
Objectives: Upon completion of this course, students will be able to Implement simulation
based verification and model hardware interfaces with concurrency constructs.

Verification process: Verification plan, Debug Cycle, Simulation and Output data, Test
bench development
Current verification techniques: HDL Software simulator, Accelerated simulation,
Process Based Accelerator techniques, Hardware emulation, FPGA prototyping
Introduction to formal techniques and property specification: Reachability analysis,
Elements of property languages, Property language layers, PSL basics, Formal test
plan process
Techniques for proving properties: Abstraction reduction, Compositional reasoning,
Counter abstraction, Gradual Exhaustive formal verification
Final system simulation: Module verification, Full simulation from a simulation, Full
Simulation from a formal verification
IEEE 1850 PSL Property specifications and IEEE 1800 Verilog assertions: Introduction,
operations and keywords, PSL Boolean and temporal layer, Introduction to IEEE 1800
System Verilog, Sequence and property, BNF 185 and BNF 223

Reading:
1. Douglas L Perry Harry D Foster, Applied Formal Verification, McGraw Hill, 2005.
2. William K Lam, Hardware Design Verification: Simulation and Formal Method-based
Approaches, Prentice Hall, 2008.

19. EC690 RF IC Design 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge of various compound semiconductor alloys, and their
growth, properties, devices and applications.

High frequency devices: Gunn diode, RWH mechanism, v-E characteristic, formation of
domains, modes of operation in resonant circuits, fabrication, control of v-E
characteristics by ternary and quaternary alloys.

III-V opto- and high frequency materials: Bonds, crytstal lattices, crystallographic planes
and directions, direct and indirect semiconductors and their comparison for optical
applications, optical processes of absorption and emission , radiative and non-radiative
deep level transitions, phase and energy band diagrams of binary, ternary and
quaternary alloys, determination of cross-over compositions and band structures.

Heterostructures: Introduction, abrupt isotype/anisotype junctions, band diagrams and

band off-sets, electrical and optoelectronic properties, symmetrical and asymmetrical p-
n diodes and their characteristics, 2-Dimensional Electron Gas (2- DEG).

Heterostructure devices: HBT, MOSFET, HEMT, quantum well and tunneling structures,
lasers, LED and photodetectors, optoelectronic IC’s and strained layer structures.

Miscellaneous devices: Compound semiconductor MESFETs, infrared and window

effect in photovoltaic converters, strain sensors and their sensitivities, QWITT and
DOVETT devices.

Reading:
1. Arora, N., “MOSFET Models for VLSI Circuit Simulation: Theory and Practice”, 4th
Ed., Springer-Verlag.
2. Tsividis, Y., “Operation and Modeling of the MOS Transistor”, 2nd Ed., Oxford
University Press.
3. Sze, S. M., and Ng, K. K., “Physics of Semiconductor Devices”, 3rd Ed., Wiley-
Interscience.
4. Liu, W., “MOSFET Models for Spice Simulation (including BSIM3V3 and BSIM4)”,
Wiley-IEEE Press

20. EC696 MEMS and Microsystems 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge of the products and materials used in MEMS and Micro
sensors and reconfigurable design implementation in MEMS.

Overview of MEMS and Microsystems: Mems And Microsystems, Evolution of micro

fabrication, Microsystems and miniaturization, Application of Microsystems, Markets for
Microsystems
Working Principles of Microsystems: Introduction, MEMS and Micro actuators,
Microfluidics, Micro actuators with Mechanical inertia
Engineering Science for Microsystems Design: Introduction, Molecular theory of
matter and intermolecular forces, Doping of semiconductor, Plasma physics,
Electrochemistry
Thermofluid Engineering and Microsystems Design: Introduction, Clock Skew and
Sequential Circuit Performance, Clock Generation and Synchronization
Designing Arithmetic Building Blocks: Introduction, Basic equation in continuum fluid
dynamics, Laminar fluid flow in circular conduits, Computational fluid dynamics,
incompressible fluid flow in micro-conduits
Microsystems Fabrication Processes: Introduction, Photolithography, Diffusion, Oxidation,
Chemical vapour deposition

Reading:
1. Tai-Ran Hsu, MEMS and Microsystems, 2nd Edition, Wiley, 2008.
2. Mohamad Gad El Hak, MEMS Design and Fabrication, 2nd Edition, CRC Press, 2006.

21. EC697 Organic Electronics 3 0 0 3

Pre-requisite: Nil
Objectives: Study, modeling and simulation of organic material based devices and circuits.
Acquaint the students with the conducting polymers, small-molecules,organic materials,
different structures of OFETs, OLEDs and various applications of organic thin film
transistors.

Sl. Contents Contact

No. Hours
1. Organic and Inorganic Materials & Charge Transport: 8
Introduction; Organic Materials: Conducting Polymers and Small
Molecules, Organic Semiconductors: p-type, n-type, Ambipolar
Semiconductors, Charge Transport in Organic Semiconductors, Charge
Transport Models, Energy Band Diagram, Organic and inorganic materials
for: Source, Drain and Gate electrodes , Insulators, Substrates ;
Comparison between Organic and Inorganic Semiconductors.
2. Device Physics and Structures: Organic Thin Film Transistors: 8
Overview of Organic Field Effect Transistor (OFET); Operating Principle;
Classification of Various Structures of OFETs; Output and Transfer
Characteristics; OFETs Performance Parameters: Impact of Structural
Parameters on OFET; Extraction of Various Performance Parameters,
Advantages, Disadvantages and Limitations.
3. Organic Device Modeling and Fabrication Techniques: 8
Modeling of OTFT Different Structures, Origin of Contact Resistance,
Contact Resistance Extraction, Analysis of OFET Electrical Characteristics,
Validation and Comparison of OFETs. Organic Devices and Circuits
Fabrication Techniques.
 4. OLEDs and Organic Solar Cells 10
Organic Light Emitting Diodes (OLEDs): Introduction; Different Organic
Materials for OLEDs; Classification of OLEDs, Output and Transfer
Characteristics; Various Optical, Electrical and Thermal properties,
Advantages, Disadvantages and Limitations.
Organic Solar Cells: Introduction, Materials, various properties,
Characteristics, Advantages, Disadvantages and Limitations and
Applications;
5. OTFT Applications 8
Organic Inverters: Inverter Circuits based on Different Materials
Combination and Configurations; All-p-type, Organic Complementary
Inverter Circuits, Hybrid Complementary Inverters, Comparison between
All P-Type, Fully Organic and Hybrid Complementary Inverter Circuits;
Logic Circuit Implementation; Organic Memory: Organic Static Random
Access Memory (OSRAM) Organic DRAM, Shift registers and other
Important Organic Memory Designs. OTFT as Driver for organic Light
Emitting Diodes (OLEDs). Addition of More Applications based on Recent
Technology Development.
Total 42

Suggested Books:

SL. Name of Authors/Books/Publishers Year of

No. Publication/Reprint
Text Books
1. Hagen Klauk, Organic Electronics: Materials, Manufacturing and 2006
Applications, Wiley-VCH Verlag Gmbh & Co. KGaA, Germany.
2. Klaus Mullen, Ullrich Scherf, Organic Light Emitting Devices: 2005
Synthesis, Properties and Applications, Wiley-VCH Verlag Gmbh
& Co. KGaA, Germany.
Reference Books
1. Hagen Klauk, Organic Electronics II: More Materials and 2012
Applications, Wiley-VCH Verlag Gmbh & Co. KGaA, Weinheim,
Germany, 2012
2. Flora Li, Arokia Nathan, Yiliang Wu, Beng S. Ong, Organic 2011
Thin Film Transistor Integration: A Hybrid Approach,
Wiley-VCH, Germany; 1st Ed.
 3. Wolfgang Brutting, Physics of Organic Semiconductors, Wiley- 2005
VCH Verlag Gmbh & Co. KGaA, Germany.
4. Dresselhaus, M.S., Dresselhaus, G. and Avouris, P., Carbon 2001
Nanotubes: Synthesis, Structure, Properties and Applications.
New York: Springer- Verlag,

22. EC698 Physical Design Automation 3 0 0 3

Pre-requisite: EC 661
Objectives: To provide knowledge of the relationship between design automation
algorithms and various constraints posed by VLSI fabrication and design technology.

VLSI design Cycle, Physical Design Cycle, Design Rules, Layout of Basic Devices, and
Additional Fabrication, Design styles: full custom, standard cell, gate arrays, field
programmable gate arrays, sea of gates and comparison, system packaging styles,
multi-chip modules.
Design rules, layout of basic devices, fabrication process and its impact on physical
design, interconnect delay, noise and cross talk, yield and fabrication cost
Factors, Complexity Issues and NP-hard Problems, Basic Algorithms (Graph and
Computational Geometry): graph search algorithms, spanning tree algorithms, shortest
path algorithms, matching algorithms, min-cut and max-cut algorithms, Steiner tree
algorithms
Basic Data Structures, atomic operations for layout editors, linked list of blocks, bin
based methods, neighbor pointers, corner stitching, multi-layer operations,
Graph algorithms for physical design: classes of graphs, graphs related to a set of lines,
graphs related to set of rectangles, graph problems in physical design, maximum clique
and minimum coloring, maximum k-independent set algorithm, algorithms for circle
graphs
Partitioning algorithms: design style specific partitioning problems, group migrated algorithms,
simulated annealing and evolution, and Floor planning and pin assignment, Routing and
placement algorithms

Reading:
1) 1NaveedShervani, Algorithms for VLSI Physical Design Automation, 3rd Edition,
Kluwer Academic, 1999.
2) Charles J Alpert, Dinesh P Mehta, Sachin S Sapatnekar, Handbook of Algorithms for
Physical Design Automation, CRC Press, 2008
 23. EC699 Embedded System Design 3 0 0 3

Pre-requisite: Nil
Objectives: Understand the embedded system design ARM micro-controller and I/O
Interfacing.

Sl. Contents Contact

No. Hours
Embedded Processing – Evolution, Issues and Challenges; System and 5
Processor Architecture: von Neumann, Harvard and their variants, Memory
1. Architecture and Devices.
Input-Output Devices and Mechanisms, Instruction Set and Addressing 7
2. Modes, Interfacing of Memory and Peripheral Devices – Functional and
Timing Issues, Application Specific Logic Design using Field Programmable
Devices and ASICs.

3. Analog to Digital and Digital to Analog Converters, Bus I/O and Networking 4
Considerations Bus and Wireless Protocols.
Embedded Systems Software: Constraints and Performance Targets, Real- 5
time Operating Systems: Introduction, Scheduling in Real-time Operating
4. Systems, Memory and I/O Management: Device Drivers.
5. Embedded Software Development : Flow, Environments and Tools, System 4
Specification and Modeling, Programming Paradigms
6. System Verification, Performance Analysis and Optimization : Speed, Power 5
and Area Optimization, Testing of Embedded Systems

7. ARM Microcontroller Architecture: Getting Started with the ARM 12

Microcontroller Architecture, Memory organization in the ARM, ARM
Instruction Set - Types of instructions and addressing modes, Programming
ARM Microcontroller, General structure of a program, Program Download
Mechanisms ,Writing Programs, Register Level Programming of the Digital
IO peripheral
Total 42

Suggested Books:

Sl. Name of Books/ Authors Year of

No. Publication
1. Designing Embedded Hardware 2nd Edition by John Catsoulis, O'Reilly 2005
Media, Print ISBN: 978-0-596-00755-3.
 Embedded System Design: A Unified Hardware/Software Approach by
2. Frank Vahid and Tony Givargis, John Wiley & Sons; ISBN: 0471386782. 2002

3. Joseph Yiu, The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 2013
Processors, Newnes; 3rd edition

24. EC700 Nanoscale Devices 3 0 0 3

Pre-requisite: EC 661
Objectives: To provide in depth knowledge of interconnect modeling and performance
analysis; introduction and analysis of futuristic material based interconnects such GNRs,
CNTs and fiber optics.

Sl. Contents Contact Hours

No.
1 CMOS scaling challenges in nanoscale regimes: Moore’s and Koomey's law, 6
Leakage current mechanisms in nanoscale CMOS, leakage control and
reduction techniques, process variations in devices and interconnects.

2 Device and technologies for sub 100nm CMOS: Silicidation and Cu-low k 10
interconnects, strain silicon – biaxial stain and process induced strain; Metal-
high k gate; Emerging CMOS technologies at 32nm scale and beyond –
FINFETs, surround gate nanowire MOSFETs, heterostructure (III-V) and Si-Ge
MOSFETs.

3 Device scaling and ballistic MOSFET: Two dimensional scaling theory of 10

single and multigate MOSFETs, generalized scale length, quantum
confinement and tunneling in MOSFTEs, velocity saturation, carrier back
scattering and injection velocity effects, scattering theory of MOSFETs.

4 Emerging nanoscale devices: Si and hetero-structure, Quasi Ballistic and 10

Ballistic Transports, nanowire MOSFETs, carbon nanotube MOSFETs, Tunnel
FET, semi-classical and quantum treatment; quantum wells, quantum wires
and quantum dots; Single electron transistors, resonant tunneling devices.

5 Non-classical CMOS: CMOS circuit design using non-classical devices – 6

FINFETs, nanowire, carbon nanotubes and tunnel devices.
Total 42

Readings:

Sl. Name of Books/ Authors Year of

No. Publication
1 Lundstrom, M., “Nanoscale Transport: Device Modeling, and Simulation”, Springer. 2005

2 Maiti, C.K., Chattopadhyay, S. and Bera, L.K., “Strained-Si and Hetrostructure Field 2007
Effect Devices”, Taylor and Francis.

3 Hanson, G.W., “Fundamentals of Nanoelectronics”, Pearson India. 2008

4 Wong, B.P., Mittal, A., Cao Y. and Starr, G., “Nano-CMOS Circuit and Physical Design”, 2004
Wiley.

5 Sandip Kundu, Aswin Sreedhar, “Nanoscale CMOS VLSI Circuits: Design for 2010
Manufacturability” McGraw Hill

6 Research and Review papers in specific area

25. EC701 Advanced VLSI Interconnects 3 0 0 3

Pre-requisite: Nil
Objectives: To provide knowledge of device physics/operation, technologies and issues in
nanoscale CMOS and other emerging devices.

Sl. Contents Contact

No. Hours
1 Preliminary concepts Interconnects for VLSI applications, metallic interconnects, 8
optical interconnects, superconducting interconnects, advantages of copper
interconnects, challenges posed by copper interconnects, fabrication process, even
and odd mode capacitances, miller theorem, transmission line equations, resistive
interconnection as ladder network, propagation modes in microstrip interconnection,
slow wave mode propagation, propagation delays.

2 Parasitic extraction Parasitic resistance, effect of surface/interface scattering and 8

diffusion barrier on resistance, Capacitance: parallel-plate capacitance, fringing
capacitance, coupling capacitance, methods of capacitance extraction, Inductance: self
 inductance, mutual inductance, methods of inductance extraction, highfrequency
losses, frequency dependent parasitics, skin effect, dispersion effect.

3 Modeling of interconnects and Crosstalk analysis Elmore model, Transfer function 8

model, even and odd mode model, Time domain analysis of multiconductor lines,
Finite Difference Time Domain (FDTD) method, performance analysis using linear
driver (Resistive) and nonlinear driver (CMOS), advanced interconnect techniques to
avoid crosstalk.

4 Future VLSI Interconnects Optical interconnects, Superconducting interconnects, 9

Nanotechnology interconnects, Silicon nanowires, Carbon nanotubes, Graphene
nanoribbons: system issues and challenges, material processing issues and challenges,
design issues and challenges.

5 Carbon nanotube and Graphene nanoribbon VLSI interconnects Quantum electrical 9

properties: quantum conductance, quantum capacitance, kinetic inductance, Carbon
nanotube (CNT) and Graphene nanoribbon (GNR) interconnects, electron scattering
and lattice vibrations, electron mean free path, single-wall CNT and single layer GNR
resistance model, multi-wall CNT and multi-layer GNR resistance model, transmission
line interconnect models, performance comparison of CNTs, GNRs and copper
interconnects.

Total 42

Readings:

Sl. Name of Books/ Authors Year of

No. Publication
1 High-Speed VLSI Interconnects, Ashok K. Goel 2007

2 Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications, Y.S. 2009

Diamand

3 Carbon nanotube and Graphene Device Physics, H.S Philip Wong and Deji 2011
Akinwande
26. EC702 SEMICONDUCTOR DEVICE MODELING 3 0 0 3

Pre-requisite: Nil
Objectives: The course will provide adequate understanding of semiconductor device
modeling aspects, useful for designing devices in electronic, and optoelectronic applications

Sl. Contents Contact

No. Hours
Introduction to Numerical Modeling: Fundamental semiconductor equations,
Finite difference scheme, Error analysis, Solution of a system of Linear
1. Equations, Direct Method: LU-decomposition, Tri-diagonal system, Relaxation 12
Method, Numerical solution of Non-Linear Equations: Newton-Raphson
method, Finite difference discretization example: Current continuity and energy
relations, Introduction to circuit simulations.
MESFET Modeling: Bridging between time and frequency domains:
2. Harmonic Balance Method, MESFET small signal and large signal equivalent
circuit, numerical device simulation and parameter extraction. 7
3. Quantum Physics Aspects of Device: Effective mass Schrodinger equation,
Matrix representation, Dirac notation, WKB Approximation, semi- classical 7
transport in semiconductors: Boltzmann transport equation, numerical scheme,
Introduction to Monte Carlo simulations.
Mathematical Techniques and Compact MOSFET models for VLSI
Design: Equilibrium carrier concentration, Carrier transport, Transport 10
4. Equation, Mobility and Resistivity, Carrier Generation and Recombination,
High-frequency behavior of MOS transistor, Poisson equation, continuity
equation, Pao and Sah’s Model, drift-diffusion equation, Small-signal
equivalent circuit, Compact Model Parameters for circuit simulators, Outline of
- Level 1, BSIM v3, BISIM v4, BISIM v6
5. Introduction to Quantum Effect Device Modeling: Double barrier resonant tunneling 6
diode, Device modeling through transfer matrix approach, Numerical estimation of
diode current density, coupled Poisson-Schrödinger scheme for electron transmission
simulations
Total 42

Suggested Books:
Sl. Name of Books/ Authors Year of
No. Publication
1. Selberherr, S., Analysis and Simulation of Semiconductor Devices, 1984 1984
Springer-Verlag
Arora, N., MOSFET Models for VLSI Circuit Simulation, Springer-Verlag 1993
2.
C.M. Snowden, and, E. Snowden, Introduction to Semiconductor Device 1998
3. Modeling, World-Scientific
4. W.J. McCalla,Fundamentals of Computer-Aided Circuit Simulation, 1987
Kluwer Academic
5. Leonard I. Schiff, Quantum Mechanics, Third Edn.,Tata Mc-Graw-Hill 2010
Research papers in specific area

27. EC703 MEMS & NEMS Technology 3 0 0 3

Pre-requisite: Nil
Objectives: The course will provide understanding of underlying principles of MEMS and
NEMS devices, and will provide insight to design related technologies.

Sl. No. Contents Contact

Hours
1. Introduction to Micro-fabrication: Cleaning, Oxidation, Diffusion, 8
Mask making, Lithography, Etching, Ion Implantation, CVD, PVD,
Metallization; Surface micromachining and Bulk Micromachining, DRIE,
LIGA, Fabrication of high aspect ratio deformable structures
2. Elasticity in Materials: Stress, strain calculations, Normal and Shear 14
strains and constitutive relations, Plane stress, biaxial stress, residual
stress, energy relations, Load-deflection calculations in beams,
cantilevers (rectangular cross section), Elastic deformation in square
plate, Resonant frequency calculations: Rayleigh-Ritz method
3. MEMS Capacitive Switch: Lumped model, pull-in voltage, 12
Electromechanical deflection modeling, pull-in instability, switching time
and pull-in voltage scaling, Physical effects in nanoscale gap-size,
squeeze-film damping , perforated MEMS Capacitive switch, Comb
actuators, Accelerometer, Pressure sensor, Energy approach: Lagrangian
Mechanics applicable to MEMS capacitive switches, Reliability in RF-
capacitive switch.
4. MEMS Sensors: Thermal sensor, Interaction of Thermal-Electrical 4
Fields,
Numerical design of thermal sensors, Bio-MEMS design problems
5. Optical MEMS: 2-D, 3-D switches, design examples 4
Total Contact Hours 42

Suggested Books:
Sl. Name of Authors / Books / Publishers Year of
No. Publication/Reprint
1. Rebeiz, G.M., RF MEMS: Theory Design and Technology,Wiley 1999
2. Stephen D. Senturia, Microsystem Design, Kluwer Academic 2001
3. Madou, M., Fundamentals of Microfabrication, CRC Press 1997
4. Sandana A., Engineering biosensors: kinetics and design 2002
applications, Academic Press
5 Related research papers

28. EC704 VLSI Architectural 3 0 0 3

Pre-requisite: Nil
Objectives: Understand the VLSI Architecture design

Sl. Contents Contact

No. Hours
1 Computer arithmetic architectures: Integer and Floating point arithmetic, Fast 8
adder/subtractors, sequential and array multipliers & dividers, square root, Absolute
difference value, CORDIC.

2 Introduction to design and implementation methodologies; Architectural mapping with 10

case studies: Data path, Control path synthesis; Control strategies; Hardware
implementation of various control structures; Micro-program control techniques;
Design issue: Timing, Area, power; FSM Architecture and Synthesis, Semiconductor
Memory and Peripheral Architectures.

3 Hardware architecture design and performance analysis: Sequential/Folding 10

architectures, bit and word serial architectures; High performance architecture
pipelined, parallel and systolic array with examples; Architectural performance
analysis: Throughput and latency: Low power VLSI architecture.

4 Basic hardware architecture for Digital Signal and Communication Systems. 6

5 Introduction to VLSI chip testing architectures: Introduction to chip fault model, DFT 8
architecture, BIST architecture.

Total Contact Hours 42

Suggested Books:
Sl. Name of Authors / Books / Publishers Year of
No. Publication/Reprint
1. B. Randell, P. C. Treleaven, “VLSI Architecture”, Pearson 1983
2. Egon Borger, “Architecture Design and Validation method” 2000
Springer
3. H. Kaeslin “Top Down Digital VLSI Design” Morgan Kaufmanl 2015
4. Related research papers