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HybridPFC PDF
HybridPFC PDF
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics
Abstract—Buck Power Factor Correction (PFC) has attracted converter will much lower at low input condition for such
a lot of research interests for its low output voltage and high wide input condition [6].
efficiency at low input condition. However, the traditional Buck Recently, using a Buck (step-down) converter as a front-
PFC converter usually has low power factor (PF) and poor end PFC converter has been introduced in [6]-[27]. The Buck
harmonic performance due to the inherent dead angle of the
PFC converter has higher low-line efficiency and lower EMI
input current, especially at low input condition. To solve this
problem, this paper proposes a family of hybrid PFC converter noise compared to the Boost PFC converter [6], [14]. The
topologies combining the advantages of step-up PFC and step- traditional Buck PFC converter and its steady state operation
down (Buck) PFC converters, which features low output voltage waveforms are shown in Fig. 1. Due to the inherent dead time
and continuous input current (high PF). The derivation in the input current when the input voltage is lower than the
methodology is presented in detail and two topologies are output voltage, the Buck PFC usually has limited PF and high
selected as typical examples to explore their performances. With current distortion, which is hard to meet the current harmonic
the improved peak current control scheme, the two proposed requirements, especially for lighting applications.
converters can achieve high PF under universal input range, and
their input current harmonics can easily meet the IEC61000-3-2
Class C limits. The optimal design considerations are presented
and two 150W prototypes are built to verify the theoretical
analysis.
I. INTRODUCTION
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Transactions on Power Electronics
Another method is compensating the current during the 2(b) is an example of cascade connection, which is a kind of
dead time to further improve its PF performance, and an extra traditional four-switch Buck-Boost converter [29]. When the
converter can be integrated with the Buck PFC converter [10], input voltage is lower than the output voltage, Q1 is always on
[17]-[20]. A Buck PFC with an active buffer was proposed in and the circuit operates as a Boost converter. While the input
[18] and almost unity power factor can be achieved, but the voltage is higher than the output voltage, Q2 is off and the
circuit needs extra active switches and bulky high voltage circuit operates as a Buck converter. However, the circuit has
capacitor and inductor. A Buck PFC integrated with a Buck- large device counts, high conduction loss and needs a high-
Boost and a Flyback circuit has been proposed in [19] and side (HS) gate driver, which is not preferred in practical
[20], respectively. Unfortunately, no systematical derivation applications.
methodology has been proposed to give a thorough insight for
B. Parallel Connection
these kinds of topologies.
In order to solve the issues mentioned above, this paper The circuit diagram of a hybrid PFC with parallel
proposes a family of single phase hybrid step-down PFC connection is shown in Fig. 3. In this structure, the step-up
converters with high power factor. The objective of hybrid converter should have the input and output disconnecting
PFC converter is to combine the advantages of the step-up capability, simple structure and the capability of sharing some
PFC and the Buck PFC to further improve their performance. components with buck converter. Since the Boost converter
In Section II, the derivation methodology of hybrid step-down does not have the disconnection capability between the input
PFC converters is discussed and two optimal topologies are and the output terminals, it cannot be adopted in parallel
selected to further disclose their operation principles. The connection structure. The Buck-Boost converter is a good
control method and design considerations of the two proposed candidate since it has the disconnection capability, low device
converters are presented in Section III. Finally, the counts and similar structure with the buck converter. As
experimental results from two 150W prototypes with shown in Fig. 4, the Buck converter and Buck-Boost
universal AC input and 80Vdc output voltage are presented in converter have very similar input structure (shown in green
Section IV. Section V concludes this paper. dash box) and output structure (shown in red dash box), so
they can share part of the components during the integration.
II. HYBRID STEP-DOWN PFC CONVERTERS Based on the shared components, there are three ways to
In this section, a family of hybrid step-down PFC integrate the two converters to derive a new hybrid PFC
converters is presented and the derivation methodology is converter.
discussed [28]. The main idea is integrating a step-up
converter with the Buck converter to compensate the input
current during the dead time, which is referred as the hybrid
method in this paper. The step-up converter can be a Boost
converter or a Buck-Boost converter (also a Flyback converter
as its isolated version).
Generally, there are two ways to integrate a step-down
converter with a step-up converter, i.e. cascade connection
and parallel connection, respectively. Fig. 3. Circuit diagram for hybrid PFC with parallel connection.
A. Cascade Connection
The circuit diagram of a hybrid PFC with cascade
connection is shown in Fig. 2(a). The circuit shown in Fig.
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Transactions on Power Electronics
Fig. 6. Hybrid PFC converters with parallel connection – sharing the output block.
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Transactions on Power Electronics
will be high. Furthermore, for topologies 2 and 4, the output which includes the topologies corresponding to the ones in
terminal is always floating in both Buck mode and Buck- Fig. 6 with a modification where the positive or negative half
Boost mode, which will increase the EMI noise. For topology of the FBR associated with the Buck-Boost/Flyback switch is
1, 3, 5 and 7, the output terminal only floats in Buck- removed, and instead, the Buck-Boost/Flyback switch is
Boost/Flyback mode, compared to topologies 2 and 4, the directly connected to the output of the input FBR. In order to
EMI noise may be a little reduced. And for topologies 6 and 8, avoid the output capacitor discharging when the switch Q 2 is
the output terminal is not floating. on, the switch Q1 should be a unidirectional switch, so a
The topologies shown above only need one inductor Schottky diode D2 in series with Q1 can be used. It can be
(coupled inductor), which is attractive for size reduction. recognized that topologies 9 and 10 are the corresponding
However, the differential mode (DM) filter must be located in ones to topologies 2 and 4 after the above modification. In the
the AC side, which will increase the size of the EMI filter. same way, topology 11 corresponds to topologies 6 and 7, and
Furthermore, the conduction loss of the input rectifier diodes topology 12 corresponds to topologies 5 and 8. Particularly,
will be high due to the input current with the switching the above modification cannot be applied for topologies 1 and
frequency component flowing through it. 3.
For topologies shown in Fig. 6, the differential mode (DM)
3) Sharing the input FBR & the output block
filter must be located in the AC side. However, by sharing the
The hybrid PFC converters by sharing the input full-bridge
input FBR, the DM filter can be located in the DC side
rectifier (FBR) and the output block are shown in Fig. 7,
because the input current of Buck and Buck-Boost/Flyback
mode both flows through the same FBR. In this way, the sizes
of DM capacitors can be largely reduced and the conduction
loss of the FBR can also be reduced.
A summary of the derived hybrid step-down PFC
converters based on Buck converter and Buck-Boost/Flyback
converters is shown in Table I. Among all the topologies, the
topologies 9 and 11 are easy to drive (do not need high-side
gate driver), need the least extra components and the DM
filter can be located in the DC side, which are attractive for
practical applications. Besides, topology 9 utilizes the
magnetic core more efficiently because only one inductor
winding is needed. For topology 11, the common mode (CM)
interference is small because the output terminal is not
floating. In this paper, these two topologies are taken for
further evaluation, where the topology 9 is referred as
Buck+Buck-Boost converter and the topology 11 is referred
as Buck+Flyback converter, respectively.
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Transactions on Power Electronics
HS Driver needed Step-up operation EMI filter Extra Components Floating Output
Topology 1 YES Q1: On, Q2: PWM AC side 2 diodes, 1 switch YES
Topology 2 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES
Topology 3 YES Q1: On, Q2: PWM AC side 2 diodes, 1 switch YES
Topology 4 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES
Topology 5 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES
Topology 10 YES Q1: Off, Q2: PWM DC side 1 diode, 1 switch YES
Fig. 8 Main circuits with improved peak current control scheme: (a) Buck+Buck-Boost converter (Topology 9). (b) Buck+Flyback converter (Topology 11).
equal to Vref1(t) or Vref2(t). With proper selected peak current i peak _ buck (t ) Vref 2 (t ) Vcomp / Rcs
reference, a smooth transition between two operation modes
can be achieved. Vref 2 (t ) kb1 (Vin sin t kb 2 Vo ) (3)
The average input current iavg(t) of the proposed hybrid
kb1 Rv 4 / ( Rv 3 Rv 4 )
PFC converter in half a line cycle can be calculated as k R / ( R R )
1 Vo b2 v1 v1 v2
2 i peak _ buck (t ) V sin t t0 t t0 i peak _ flyback (t ) Vref 1 (t ) Vcomp / Rcs
in
1 nVo Vref 1 (t ) k f Vin sin t (4)
iavg (t ) i peak _ flyback (t ) 0 t t0 and
2 Vin sin t +nVo
t0 t ) k f RL 2 / ( RL1 RL 2 )
Vin is the peak input voltage, Vo is the output voltage.
(1) ipeak_buck(t) and ipeak_flyback(t) represent the instant peak current
of Buck and Buck-Boost/Flyback operation in the proposed
where hybrid converters, respectively. ωt0 is the transition point
Vswitch between Buck-Boost/Flyback mode and Buck mode operation.
t0 arcsin (2)
Vin Parameter n is the turns ratio (N2/N1) of the coupled inductor
in topology 11 (Buck+Flyback) as shown in Fig. 8 (b), while
it is equal to 1 in topology 9 (Buck+Buck-Boost). Vcomp is the
output of the voltage feedback loop, which is related to the
output power and keeps almost constant during half a line
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Transactions on Power Electronics
i peak _ buck (t ) Lm
t0 t t0
V o
i (t ) n Lm
Toff (t ) peak _ flyback 0 t t0 and (8)
V o
t0 t )
Due to the CRM operation, the switching frequency varies
with the input voltage and load condition. Similar to most
traditional CRM PFC design method, the inductance is mainly
Fig. 9 Theoretical current waveforms with proposed control scheme designed based on the switching frequency at full load
condition. At low input voltage, the switching frequency
cycle. kb1, kb2 and kf are the ratio of the resistor dividers R v3 should be above 20 kHz to avoid audible noise. At high input
and Rv4, Rv1 and Rv2, RL1 and RL2, respectively, which are voltage, the switching frequency should not be too high
used to generate the peak current waveform references from considering the EMI performance, it’s better to keep the
input and output voltage. In topology 11, the two references switching frequency at high input condition be below 150 kHz
Vref1(t) and Vref2(t) can be obtained from input and output or even 75 kHz for better EMI performance.
voltages by the resistor dividers, and the parameters kb1, kb2 Since the proposed hybrid converter is mainly operated in
and kf are given in (3) and (4). In topology 9, Vref2(t) is Buck mode, the switching frequency of Buck mode is much
generated by a subtracter, and the component kb1*kb2*Vo is more important for the converter performance. Fig. 10 shows
obtained by a fixed DC voltage Vb2 as shown in Fig.8 (a), the switching frequencies in Buck mode with different PFC
while kb1 and kf still keep the same as given in (3) and (4). inductance. The switching frequency is proportional to the
In order to achieve a smooth transition between Buck mode input voltage and inversely proportional to the inductance.
and Buck-Boost/ Flyback mode, the input voltage and average From Fig. 10 (a), it can be found that a smaller inductance
input current should meet (5) at the transition point ωt0 such as 120μH is preferred for a higher minimal switching
Vin sin t0 Vswitch
frequency at 90Vac input. Nevertheless, a larger inductance
(5) such as 150μH is preferred for better EMI performance, as
iavg _ buck (t0 ) iavg _ flyback (t0 )
shown in Fig. 10 (b). It is reasonable to design the inductance
Generally, Vswitch is designed to be the same as Vo from (5), between these ranges. In this work, Lm is chosen as 135μH for
the relationship between kb1, kb2 and kf can be obtained as the prototypes.
1 n
kf kb1 (1 kb 2 ) (6)
n
As long as the parameters kb1, kb2 and kf satisfy equation (6),
a smooth current transition between Buck-Boost/ Flyback
mode and Buck mode can be achieved, which is not affected
by the variation of the input voltage. The theoretical current
waveforms under different input voltages are shown in Fig. 9.
B. Design Considerations of the Inductance Lm and the Turns
Ratio n
In the hybrid PFC converter, the switching frequency is
mainly determined by the PFC inductance Lm. The turns ratio
n only affects the switching frequency in the Flyback mode
operation. According to the peak current control scheme and
voltage-second balance, Ton and Toff in the two operation
modes can be expressed in (7) and (8)
i peak _ buck (t ) Lm
t0 t t0
Vin sin t Vo
i peak _ flyback (t ) n 2 Lm
Ton (t ) 0 t t0 and (7)
Vin sin t
t0 t )
Fig. 10 Calculated switching frequency in the Buck mode versus
different input voltages: (a) Vin=90Vac. (b) Vin=220Vac.
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Transactions on Power Electronics
Po 0
Pflyback _ nor (n) d t
Vin sin t nVo
P
buck _ nor (n) 1 Pflyback _ nor (n)
(9)
where η is the efficiency of the converter, Po is the output
power.
Fig. 12 shows the calculated switching frequency in half a
line cycle with n=0.5, 1 and 2. It can be seen that the turns
ratio n has a strong influence on the frequency in the Flyback
mode. A smaller n will lead to a higher frequency in Flyback
mode, for example, when n=0.5, the highest frequency will be
above 1MHz theoretically. On the other hand, a bigger n will
increase the coupled inductor size because more turns are Fig. 14 Calculated harmonics and THD varied with the parameter kb2: (a)
required for the Flyback winding. Generally, n=1 is an 3rd and 5th harmonic. (b) 7th and 9th harmonic. (c) THD.
appropriate turns ratio for topology 11. Therefore, topology 9 waveform. Therefore, the input current harmonics and the
and topology 11 have the same main circuit parameters and THD are affected by this parameter. Fig. 13 shows the
control scheme. calculated average input current waveforms with kb2=0.5, 0.7
C. Harmonics Analysis and Design Considerations for and 0.9.
Parameter kb2 The harmonic spectrum of the input current waveform can
be calculated by using Fourier decomposition. To compare
The parameter kb2 determines the peak current waveform in
with the IEC61000-3-2 Class C limits, the odd-order
the Buck mode, so it also determines the average input current
harmonic current contents from 3rd to 9th varied with the
parameter kb2 are shown in Fig. 14 (a) and (b). The higher
order (greater than 9th) harmonic current contents can also be
analyzed in the same way, which are not repeated here
because they are usually much easier to meet the IEC61000-3-
2 Class C limits in the proposed converters.
Fig. 14 can be used to select the appropriate parameter kb2
for the proposed converters. As shown in Fig. 14 (a) and (b),
the 3rd and 7th harmonic current components are always below
the limits. The 5th and 9th harmonic current contents will be
below the limits when kb2 is below 0.92. Besides, as shown in
Fig. 14 (c), the minimal THD is about 4.5% when the
parameter kb2 is around 0.7. Thus, kb2=0.7 is an optimal value
Fig. 12 Calculated switching frequency with different turns ratio n.
for the harmonic performance of the proposed converters.
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Transactions on Power Electronics
IV. EXPERIMENTAL RESULTS parameters of the prototypes are shown in Table II.
Two 150W prototypes using topology 9 and topology 11 The input voltage and input current waveforms of the
with universal AC input and 80Vdc output are built to verify traditional Buck PFC and the two proposed hybrid PFC
the proposed hybrid PFC converters and the control method. converters with full load at 110 and 220Vac inputs are shown
The main circuits and control schemes of these two topologies in Fig. 15. It can be seen that the dead time of the input
are shown in Fig. 8. The PQ2625 ferrite core is adopted for current is eliminated in the two proposed converters, and the
the inductor in topology 9 and the coupled inductor in current waveforms are almost the same for the two proposed
topology 11. For these two topologies, the PFC inductance is topologies.
set to 135μH and the parameter kb2 is set to 0.7. For topology The measured PFs of the traditional Buck PFC converter
11, the turns ratio n of the coupled inductor is set to 1 as and the two proposed hybrid PFC converters are shown in Fig.
discussed above. Considering the output voltage ripple, the 16. Obviously, the PF is greatly improved in the proposed
converters at low line voltage. The measured harmonic
switching voltage Vswitch for the Buck mode and Buck-
Boost/Flyback mode is set to 85Vdc in the prototypes. For contents of the input current at 110Vac and full load condition
comparison, a 150W prototype of the traditional Buck PFC are shown in Fig. 17. It can be seen that the proposed
converter with same parameters is also built up. The key converters can easily meet the IEC61000-3-2 Class C limits
with large margins.
TABLE II KEY PARAMETERS OF THE TWO PROPOSED PROTOTYPES
Controller Q L6562D Fig. 16 Measured PF at different input voltages and full load.
Fig. 15 Measured input voltage and input current of traditional Buck PFC and the two proposed hybrid PFC converters: (a), (b), (c) Traditional Buck,
Topology 9, Topology 11 at 110Vac input. (d), (e), (f) Traditional Buck, Topology 9, Topology 11 at 220Vac input.
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Transactions on Power Electronics
Fig. 20 The waveforms of output voltage ripple at 110Vac input and full
load: (a) Buck converter. (b) Topology 9. (c) Topology 11.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics
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Transactions on Power Electronics
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