EECS240 – Spring 2010

Lecture 4: Design-Driven Small Signal Models

Elad Alon
Dept. of EECS

MOSFET Models for Design

• SPICE (BSIM)
• For verification
• Device variations

• Hand analysis
• Velocity-sat model (good mostly for intuition)
• Small-signal model

• Challenge
• How to accurately design when hand analysis
models may be way off?

EECS240 Lecture 4 2
 Parameters Designers Care About
• Layout designer:
• Mostly care about just W and L

• Circuit designer:
• Gain gm, ro
• Bandwidth gm, CGS, CGD, …
• Power ID
• Voltage swing minimum VDS
• Noise

• Can get many of the circuit parameters without

resorting to BSIM
• Or rather, by just using BSIM as a look-up table

EECS240 Lecture 4 3

Small Signal Model

• Never really changes:

• Just need to know the coefficients…

• Look at design-driven methods to figure out
what ro, gm, etc. are
• And what values you want to choose for them

EECS240 Lecture 4 4
Output Resistance ro

Hopeless to model this with a simple equation

(e.g. gds = λ ID)

EECS240 Lecture 4 5

What You Really Care About: Gain av0

• Represents maximum attainable

gain from a transistor
• Often more useful than ro

• Simulation Notes:
• Bias current idc sets VGS - VT
• Use feedback to find correct VGS
while sweeping VDS
• Use relatively small gain (100) for
fast DC convergence

EECS240 Lecture 4 6
Gain, av0 = gm ro

L = 0.18µm
• Strong tradeoff:
av0 versus VDS
range

• Create plots for

several device
lengths

EECS240 Lecture 4 7

Long Channel Gain

L = 0.35µm

L↑ av0 ↑

EECS240 Lecture 4 8
Technology Trend
80

70 0.5µm

60 0.35µm

50
gm⋅ro

0.25µm
40

30 0.18µm

20

10

0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VDS [V]

Short channel devices usually have lower

peak gain

EECS240 Lecture 4 9

Transistor Gain Detail

45

40

35 0.5µm

30

0.35µm
g m⋅ r o

25

20 0.25µm

15
0.18µm
10

0
0.0 0.1 0.2 0.3 0.4

VDS [V]

For practical VDS gain penalty is less severe

(remember: worst case VDS is what matters!)

EECS240 Lecture 4 10
 gm: Square Law Model
• In saturation:

Vod

EECS240 Lecture 4 11

Figure of Merit: gm/ID

• How much gm per unit current

• Purely a DC metric
• Will look at dynamic implications later

• Why does gm/ID flatten out at low Vgs?

EECS240 Lecture 4 12
 Weak Inversion gm
• In weak inversion we have bipolar behavior

• Good model if transistor is actually used in weak

inversion

EECS240 Lecture 4 13

Efficiency gm/ID
vs.

• “Big” Vod MOS has worse gm/Id

• In weak or moderate inversion,

NMOS and PMOS approach BJT
gm/IC = 1/Vt ~ 40 V-1

EECS240 Lecture 4 14
 Efficiency as a Design Parameter
• Why not use gm/ID for design?

• Can always determine value (from ID and gm)

• Can do this “independently” of short channel effects
(using simulator)

• Units (V-1) and physical interpretation a little

strange
• But we’ll just redefine things slightly to fix this

EECS240 Lecture 4 15

Substitute for gm/ID: V*

• Define:

2ID gm 2
V* = ⇔ =
gm ID V *

e.g. V* = 200mV gm/ID = 10 V-1

• Square-law devices: V* = VGS-VTH = Vod

2I D 2I
Square law : gm = = D
VGS − VTH V *

• Remember: real devices do not obey the square

law!
EECS240 Lecture 4 16
 Vod vs V*
• Overdrive voltage Vod • V* = 2ID/gm
• Cannot be measured • Measure (simulate) easily
• Complex equations • Complex equations

• “Long channel” devices: • “Short channel” devices:

• Vod = Vdsat = V* • All interpretations of V* are
• ID ~ V*2 approximations
• Boundary between • Except V* = 2 ID / gm (but V*
≠ Vdsat)
triode and saturation
• ro “large” for VDS > V*
• CGS, CGD change

EECS240 Lecture 4 17

Design Example
Example: Common-source amp
av0 > 70, fu = 100MHz for CL = 5pF

• av0 > 70 L =0.35µm

• g m ≈ 2πf u C L = 3.14mS

• Pick V* = 200mV
g mV *
ID = = 314µA
• 2

EECS240 Lecture 4 18
 Device Sizing
• Pick L 0.35µm
• Pick V* 200mV
NMOS
• Determine gm 3.14mS

• ID = 0.5 gm V* = 314µA

• W from graph
(generate with SPICE)
141uA
W = 10µm (314µA /141µA)
= 22µm

• Create these graphs for

several device lengths and
flavors

EECS240 Lecture 4 19

Common Source Verification

• Amplifier gain > 70; gain-bandwidth “dead on”

• Output range to 0.6V – 1.5V for gain (about ±0.45V
swing)
• How did we pick V* = 200mV? Why not 75mV?
• Need to look at AC model…
EECS240 Lecture 4 20
 Small-Signal AC Model

Gate Drain
gmvgs ro
Source

Bulk = Substrate

EECS240 Lecture 4 21

PMOS AC Model

EECS240 Lecture 4 22
 SPICE Charge Model
• Charge conservation

• MOSFET:
• 4 terminals: S, G, D, B
• 4 charges: QS + QG + QD + QB = 0 (3 free variables)
• 3 independent voltages: VGS, VDS, VSB
• 9 derivatives: Cij = dQi / dVj, e.g. CG,GS ~ CGS
• Cij != Cji

Ref: HSPICE manual, “Introduction to Transcapacitance”, pp.

15:42, Metasoft, 1996.

EECS240 Lecture 4 23

Small Signal Capacitances

Weak inversion Strong inversion Strong inversion
linear saturation
CGS Col CGC/2 + Col 2/3 CGC + Col
CGD Col CGC/2 + Col Col
CGB CGC || CCB 0 0
CSB CjSB CjsB + CCB/2 CjsB + 2/3 CCB
CDB CjDB CjDB + CCB/2 CjDB

CGC = CoxWL Cox = 5.3 fF/µm 2

0.35u Process
ε Si ColN = 0.24 fF/µm
CCB = WL
xd ColP = 0.48 fF/µm

EECS240 Lecture 4 24
Layout

HSPICE geo = 0 (default)

HSPICE geo = 3

EECS240 Lecture 4 25

Source/drain Parasitics and HSPICE

• ACM=3 model (not in our current library)
• HDIF = half of heavily doped diffusionHSPICE
length
geo = 0 (default)

• GEO = 0: No sharing
• GEO = 1: Drain shared
• GEO = 2: Source shared HSPICE geo = 3

• GEO = 3: Both shared

EECS240 Lecture 4 26
 Dynamic Figure of Merit
• Unity current-gain bandwidth

od
(Long channel model, Cgd=0)

• For degenerate short channel device

EECS240 Lecture 4 27

Efficiency gm/ID versus fT

Speed-
Efficiency
Tradeoff

NMOS faster
than PMOS

0.35u Process

EECS240 Lecture 4 28
 Device Scaling
60

50
0.18µm

40
fT [GHz]

30
0.25µm

20 0.35µm

10 0.5µm

0
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VGS-VTH [V]

Short channel devices significantly faster

EECS240 Lecture 4 29

Composite Figure-of-Merit: fT·gm/ID

400

0.18µm
350

300
fT⋅ g m/ID [GHz/V]

250

200

0.25µm
150

0.35µm
100

50 0.5µm

0
-0.1 0.0 0.1 0.2 0.3 0.4 0.5

V G S -V TH [V]

Peak performance for low VGS-VTH (implies low V*)

• Guides choice of V*: if in doubt,

EECS240 Lecture 4 30
 Small Signal Design Summary
• Determine gm (from design objectives)

• Pick L
• Short channel high fT
• Long channel high ro, av0, better matching

• Pick V* = 2ID/gm based on qualitative interpretation

• Small V* large signal swing, high current efficiency
• High V* high fT, lower device parasitics
• Also affects noise (see later)

• Determine ID (from gm and V*)

• Determine W (SPICE / plot)  takes care of short channel

effects, etc.

• Accurate for short channel devices key for design

EECS240 Lecture 4 31