Professional Documents
Culture Documents
(2018-19)
➢ They can develop solutions for any practical problems through projects.
➢ They can understand the use of ICs in different domains.
Aim: To design a non-inverting amplifier with a gain of 3.2 using Op-Amp LM/NE/μA741.
Verify the results of both software and hardware.
Apparatus:
1. PC with multisim software
2. Function generator /Audio oscillator
3. D.S.O
4. Bread board
5. DC±12V (or)±15V fixed regulated power supply
6. Op-Amp LM/NE/μA741
7. Resistors
8. Connecting wires
Circuit Diagram:
Theory:
1 1 Vo
Vi
R R R
⇨ i f f
R f Ri Vo
Vi
R .R R
⇨ i f f
Rf
Vo 1 .Vi
⇨ Ri
Vo Rf
1
⇨ Gain= Vi = Ri
Rf
1
That is gain of non-inverting amplifier = Ri . There is no phase difference between input and
output. This configuration is used to design an amplifier by using Op-Amp when the required
Rf
1
gain is positive. Suppose the required gain is 10 then Ri =10. This implies Rf=9Ri. By
Design calculations:
Procedure:
1. Take care of +VCC and –VEE values. They should not exceed +15 volts and -15volts
respectively.
2. Be clear with pin numbers.
Result:
Software Hardware
Gain
Output
Aim: To verify Op-Amp LM/NE/μA741as adder and subtractor with the help of both software
and hardware.
Apparatus:
1. PC with multisim software
2. Function generator /Audio oscillator
3. D.S.O
4. Bread board
5. DC±12V (or)±15V fixed regulated power supply
6. Op-Amp LM/NE/μA741
7. Resistors: 100KΩ3 No.s
10KΩ4 No.s
8. Connecting wires.
Circuit Diagrams:
(a) Adder
Theory:
The Op-Amp adder circuit shown is connected in inverting configuration. So, there will be a
phase difference of 1800 between input and output. The potential at node A will be ‘0volts’ as it
is at virtual ground.
Applying KCL at node A
V A V1 V A V2 V A Vo
Ri1 Ri 2 R f =0
⇨ V2 2V1 V2 2V0 0
⇨ V0 V2 V1
Theoretical Calculations:
Adder output = -(300mV+200mV)
=-500mV
Subtractor output = 300mV – 200mV
=100mV
Procedure:
Precautions:
1. Take care of +VCC and –VEE values. They should not exceed +15 volts and -15volts
respectively.
2. Be clear with pin numbers.
Adder
Subtractor
Aim: To design Op-Amp differentiator circuit for 100Hz signal and realize the same in both
software and hardware.
Apparatus:
1. Function generator
2. D.S.O
3. IC breadboard / trainer unit
4. DC ± 12V (or) ±15V fixed regulated power supply
5. Op-Amp LM/NE/μA741
6. Resistors R=10Ω,100 Ω,1 kΩ, 100 kΩ, 1 MΩ
7. Capacitors C = 0.001μF, 0.01μF, 0.1μF and
8. connecting wires
Circuit Diagram:
Design Steps:
1. Assume op-amp differentiator will differentiate an input signal with fmax = 100Hz.
2. Select fa = fmax = 100Hz = 1/(2πRfCi). Let Ci = 0.1µF and calculate Rf.
Theory:
The basic single resistor and single capacitor op-amp differentiator circuit is not widely used to
reform the mathematical function of Differentiation because of the two inherent faults,
“Instability” and “Noise”. So in order to reduce the overall closed-loop gain of the circuit at high
frequencies, an extra resistor, Ri is added to the input. Adding the input resistor Ri limits the
differentiators increase in gain at a ratio of Rƒ/Ri. The circuit now acts like a differentiator
amplifier at low frequencies and an amplifier with resistive feedback at high frequencies giving
much better noise rejection. Additional attenuation of higher frequencies is accomplished by
connecting a capacitor C in parallel with the differentiator feedback resistor, Rƒ.
The high pass filter acts as differentiator only when RC << T, where T is the time period of input
signal and RC is the time constant of the high pass filter.
Procedure:
Model Waveforms:
Result:
Aim: To design the function generator using op-amp to generate 1KHz Square Wave, Sinusoidal
Wave and Triangular Wave.
Apparatus:
1. IC breadboard/trainer unit
2. DC ± 12V (or) ±15V fixed regulated power supply
3. D.S.O
4. Op-Amp LM/NE/μA741
5. Resistors: 4.7kΩ, 100kΩ, 1MΩ, 1.98kΩ, 4kΩ
6. Capacitor C =0.01μF and
7. Connecting wires
Circuit Diagram:
Design Equations:
The common practice is to make the R3 equal to R2. Then the equation for the time period can
be simplified as: T = 2.1976R1C
Design Equations:
The oscillation frequency (f) for sine wave generator(Wein Bridge Oscillator) is given by
1
f=
2𝜋𝑅𝐶
Theory:
In the square wave generator shown in figure, due to the presence of positive feedback it works
in saturation mode. So output is either +Vcc or –Vcc. First letus assume that the output is at
Vcc .R1
+Vcc. Then voltage at the non inverting terminal becomes R1 R2 and capacitor starts charging
Vcc .R1
towards Vcc and the moment when it exceeds R1 R2 then inverting input dominates and
Vcc .R1
output becomes –Vcc. Then voltage at the non inverting terminal becomes - R1 R2 and
Vcc .R1
capacitor starts discharging towards –Vcc and the moment when it just falls below - R1 R2
then the non inverting terminal dominates and output becomes +Vcc. This cycle repeats and
results in square wave output. This output is given to integrator to get triangular output. Low
The sine wave generator is wien bridge oscillator. Under bridge balance condition, it generates
oscillations, as it is known that the oscillator produce oscillations only when it meets Barkhausen
criteria of oscillations, i.e
1. A 1
2. Angle( A )=3600
Procedure:
Precautions:
Model Waveforms:
Software Hardware
Square wave
Triangular Wave
Sine Wave
Aim: To design a first order active high pass filter circuit with cut off frequency of 159 Hz.
Apparatus:
1. IC breadboard/trainer unit
2. DC ± 12V (or) ±15V fixed regulated power supply
3. Signal generator (10 mV peak,1 kHz input signal)
4. D.S.O
5. Op-Amp LM/NE/μA741
6. Resistors: R1=1kΩ,R2 =10 kΩ
7. Capacitor C=1μF and
8. connecting wires
Circuit Diagram:
Theory:
High pass filter is an electronic circuit which will pass all the frequencies from cutoff frequency
and stops all frequencies below cutoff frequency. The circuit diagram is obtained by connecting
a passive high pass filter followed by non-inverting amplifier.
For D.C ( zero frequency) capacitor behaves like open circuit and there will not be any
connection between input and output, which results in zero output. As the frequency is increasing
the capacitive reactance is decreasing, drop across the output is decreasing and hence output is
increasing. After reaching the cutoff frequency the output will reach 70.7% of maximum
possible output. From there after the output and gain will slowly increase as shown in the
frequency response curve.
For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a
function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value
and is given as:
f
AF ( )
Vout fc
Vin f
1 ( )2
Voltage gain(AV)= fc
● Where:
● AF = the Pass band Gain of the filter, ( 1 + R2/R1 )
● ƒ = the Frequency of the Input Signal in Hertz, (Hz)
● ƒc = the Cut-off Frequency in Hertz, (Hz)
Just like the low pass filter, the operation of a high pass active filter can be verified from the
frequency gain equation above as:
V out
AF
V
● 3. At very high frequencies, ƒ > ƒc : in
Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the lower cutoff
frequency, ƒC at 20dB/decade as the frequency increases. At ƒC the gain is 0.707*AF, and after ƒC
all frequencies are pass band frequencies so the filter has a constant gain AF with the highest
frequency being determined by the closed loop bandwidth of the op-amp.
When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally
expressed in decibels or dB as a function of the voltage gain, and this is defined as:
Vout
AV ( dB ) 20 log10 ( )
Vin
For a first-order filter the frequency response curve of the filter increases by 20dB/decade or
6dB/octave up to the determined cut-off frequency point which is always at -3dB below the
maximum gain value. As with the previous filter circuits, the lower cut-off or corner frequency
(ƒc) can be found by using the same formula:
1
fC Hz
2 RC
The corresponding phase angle or phase shift of the output signal is the same as that given for the
passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off frequency ƒc
value and is given as:
Procedure:
S.No. Input Voltage (V) Frequency (Hz) Output Voltage (V) Voltage Gain
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Precautions:
Result:
Theoretical Practical
Software Hardware
Aim: To design a 555 timer astable multivibrator circuit to generate a clock signal with 61%
duty cycle with a frequency of 1.45 KHz.
Apparatus:
1. IC breadboard
2. 555TimerIC
3. DC variable regulated power supply
4. C.R.O
5. Resistors
6. Capacitor 0.1μF, 0.01μF and connecting wires
Circuit Diagram:
Initially switch on the power supply. The flip-flop is RESET (and hence the output of the timer is
low). As a result, the discharge transistor is driven to saturation (as it is connected to Q’). The
capacitor C of the timing circuit is connected at Pin 7 of the IC 555 and will discharge through
the transistor. The output of the timer at this point is low. The voltage across the capacitor is
nothing but the trigger voltage. So while discharging, if the capacitor voltage becomes less than
1/3 VCC, which is the reference voltage to trigger comparator (comparator 2), the output of the
comparator 2 will become high. This will SET the flip-flop and hence the output of the timer at
pin 3 goes to HIGH.
This high output will turn OFF the transistor. As a result, the capacitor C starts charging through
the resistors R1 and R2. Now, the capacitor voltage is same as the threshold voltage (as pin 6 is
connected to the capacitor resistor junction). While charging, the capacitor voltage increases
exponentially towards VCC and the moment it crosses 2/3 VCC, which is the reference voltage to
threshold comparator (comparator 1), its output becomes high.
As a result, the flip-flop is RESET. The output of the timer falls to LOW. This low output will
once again turn on the transistor which provides a discharge path to the capacitor. Hence the
capacitor C will discharge through the resistor R2. And hence the cycle continues.
While charging, the capacitor charges through the resistors R1 and R2. Therefore the charging
time constant is (R1 + R2) C as the total resistance in the charging path is R1 + R2. While
Procedure:
1. Make the connections as per the circuit diagram.
2. Identify the pins of 555 IC correctly. Ensure that +VCC is applied properly.
3. Connect the output to DSO and observe the output waveforms at pin no.3 and 2 (VO and VC),
to the same time scale on a dual beam/dual trace DSO.
4. Measure voltage and time intervals. Compare theoretical and actual values of software and
software. Sketch the output waveforms.
Model Waveforms:
Precautions:
Result:
1. Why 50% duty cycle can’t be obtained with the above circuit?
2. What are the applications of this circuit?
3. Draw the circuit, to get50%dutycycle?
4. Design an IC555 astable multi that produces a square wave of 5KHz frequency with 60%
Duty cycle.
Apparatus:
Circuit Diagram:
Design Equation:
The R-2R resistor ladder network directly converts a parallel digital symbol/word into an analog
voltage. Each digital input (b0, b1, etc.) adds its own weighted contribution to the analog output.
This network has some unique and interesting properties.
Procedure:
1. Make the connections as per the circuit diagram shown in figure 15.
2. Give +Vcc and –Vcc supply connections correctly.
3. Apply Vref and change the switch positions as per the following table and note the
corresponding outputs with Multimeter.
4. Verify theoretical and actual voltages, in each case.
Precautions:
Result:
Aim: To verify the functionality of voltage regulator ICs – 78xx and 79xx series.
Apparatus:
1. 230V-12V Step Down Transformer
2. Bridge Rectifier (or 4 PN Diodes – 1N4007)
3. 1A Fuse
4. 1000μF Capacitor
5. 7805 Voltage Regulator IC
6. 0.22μF Capacitor
7. 0.1μF Capacitor
8. 1N4007 Diode
Circuit Diagram:
The AC power supply from mains first gets converted into and unregulated DC and then into a
constant regulated DC with the help of this circuit. The circuit is made up of transformer, bridge
rectifier made up from diodes, linear voltage regulator 7805 and capacitors.
If you observe, the working of the circuit can be divided into two parts. In the first part, the AC
Mains is converted into unregulated DC and in the second part, this unregulated DC is converted
into regulated 5V DC. So, let us start discussing the working with this in mind.
Initially, a 230V to 12V Step down transformer is taken and its primary is connected to mains
supply. The secondary of the transformer is connected to Bridge rectifier (either a dedicated IC
or a combination of 4 1N4007 Diodes can be used).
A 1A fuse is placed between the transformer and the bridge rectifier. This will limit the current
drawn by the circuit to 1A. The rectified DC from the bridge rectifier is smoothened out with the
help of 1000μF Capacitor.
So, the output across the 1000μF Capacitor is unregulated 12V DC. This is given as an input to
the 7805 Voltage Regulator IC. 7805 IC then converts this to a regulated 5V DC and the output
can be obtained at its output terminals.
Observations:
1. The first important point to note is that the input voltage should always be greater than the
output voltage (at least by 2.5V).
2. Identify the pin configuration of the IC properly.
Result:
Apparatus:
1. Function generators
2. Oscilloscope
3. Dual DC-power supply
4. LM565 IC
5. Resistors
6. Capacitors
7. Digital voltmeter
Circuit Diagram:
4. Gradually decrease the frequency fi, and determine fC+ [the upper edge of the capturerange].
Decrease further fi and measure Vo(t) and VD for each integer-value (in kHz)setting of fi.
Find fH¡ [the lower edge of the tracking range], and record in table (2).
Apparatus:
1. LM566 IC
2. Resistors
3. Capacitors
4. DC power supply
5. CRO
6. Connecting wires
Circuit Diagram:
Resistor R1 and capacitor C1 forms the timing components. Capacitor C2 is used to prevent the
parasitic oscillations during VCO switching. Resistor R3 is used to provide the control voltage
Vc. Triangle and square wave outputs are obtained from pins 4 and 3 respectively. The output
frequency of the VCO can be obtained using the following equation:
Fout = 2.4(V+-V5) /(R1C1V+) . Where Fout is the output frequency, R1 and C1 are the timing
components and V+ is the supply voltage.
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Apply DC supply to the IC.
3. Connect CRO at the output terminals to observe output waveforms.
4. Vary the values of R1 and C1 and observe different outputs.
5. Note the readings for different cases.
Graph: