5 4 3 2 1

http://laptop117.com
D D

Gilbert Graphic Schematics Document

ATI M11-P External VGA BD
C
REV : 1.0 ( A00 ) C

@ : Nopop Component

MODEL NAME : EBQ20

PCB NO : LS-2501
DATE : 9/24/2004
B B

COMPAL CONFIDENTIAL

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Cover Page
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Friday, September 24, 2004 Sheet 1 of 12
5 4 3 2 1
 5 4 3 2 1

http://laptop117.com
+3VRUN +3VRUN
GAD[31..0]
<9> GAD[31..0]

2
U1A
GAD0 GPIO0 R624 R35
GAD1
H29
H28
AD0 M11-P GPIO0 AJ5
AH5 GPIO1
GPIO0 <11>
AD1 GPIO1 GPIO1 <11>
GAD2
GAD3
J29 AD2 (1/6) GPIO2 AJ4 GPIO2
GPIO3
GPIO2 <11>
4.7K_0402_5%~D 10K_0402_5%~D
J28 AK4 GPIO3 <11>

1
GAD4 AD3 GPIO3 R1 10K_0402_5%~D DVI_DETECT2 SCS#
K29 AD4 GPIO4 AH4
GAD5 K28 AF4 1 2
GAD6 AD5 GPIO5
L29 AD6 GPIO6 AJ3
GAD7 L28 AK3 MEM_ID3
AD7 GPIO7 MEM_ID3 <11>
GAD8 N28 AH3
D AD8 GPIO8 SOUT <11> D
GAD9 P29 AJ2
AD9 GPIO9 SIN <11>
GAD10 P28 AH2 SCLK
AD10 GPIO10 SCLK <11>
GAD11 R29 AH1 ROM_ID1
AD11 GPIO11 ROM_ID1 <11> ROM_ID4 <11>
GAD12 R28 AG3 ROM_ID2
AD12 GPIO12 ROM_ID2 <11> +3VRUN
GAD13 T29 AG1 ROM_ID3
AD13 GPIO13 ROM_ID3 <11>
GAD14 T28 AG2 DVI_DETECT2
GAD15 AD14 GPIO14 POW_SW
U29 AD15 GPIO15 AF3 POW_SW <5,10>

1
GAD16 N25 AF2 OSC_SPREAD
AD16 GPIO16 OSC_SPREAD <11>
GAD17 R26 R632

ZV PORT / EXT TMDS / GPIO / ROM

GAD18 AD17 VREFG +3VRUN
P25 AD18 VREFG/(NC) AG4
GAD19 R27 4.7K_0402_5%~D
GAD20 AD19 SCS#
R25 AF5 SCS# <11>

2
AD20 ROMCS#

1
GAD21 T25
GAD22 AD21 R10
T26 AD22 ZV_LCDDATA0 AH6
GAD23 U25 AJ6 I2C_DAT
AD23 ZV_LCDDATA1 I2C_DAT <8>
GAD24 V27 AK6 1K_0402_1%~D
GAD25 AD24 ZV_LCDDATA2
W26 AH7

2
GAD26 AD25 ZV_LCDDATA3 VREFG
W25 AD26 ZV_LCDDATA4 AK7
GAD27 Y26 AJ7 +3VRUN
AD27 ZV_LCDDATA5

1
GAD28 Y25 AH8
+3VRUN GAD29 AD28 ZV_LCDDATA6 R11
AA26 AD29 ZV_LCDDATA7 AJ8

1
GAD30 AA25 AH9
GC/BE#[3..0] GAD31 AD30 ZV_LCDDATA8 1K_0402_1%~D R634
<9> GC/BE#[3..0] AA27 AD31 ZV_LCDDATA9 AJ9
1 AK9

2
C582 GC/BE#0 ZV_LCDDATA10 4.7K_0402_5%~D
N29 C/BE#0 ZV_LCDDATA11 AH10
GC/BE#1 U28 AE6 LCD_TST LCD_TST <8>

2
U20 @ 0.1U_0402_10V6K~D GC/BE#2 C/BE#1 ZV_LCDDATA12 LCD_STAT
P26 C/BE#2 ZV_LCDDATA13 AG6 LCD_STAT <8>
@ TC7SH08FU_SSOP5~D 2 C1 @ 22P_0402_50V8J~D R3 @ 33_0402_5%~D GC/BE#3 R7 33_0402_5%~D
U26 C/BE#3 ZV_LCDDATA14 AF6
5

1 2 1 2 AE7 1 2 I2C_CLK
ZV_LCDDATA15 I2C_CLK <8>
1 CK_66M_AGP AG30 AF7
P

B <9> CK_66M_AGP PCICLK ZV_LCDDATA16

4 AG28 AE8 R8
GRST# O GREQ# RST# ZV_LCDDATA17 33_0402_5%~D
<9> GRST# 2 A <9> GREQ# AF28 REQ# ZV_LCDDATA18 AG8
G

C GGNT# C
<9> GGNT# AD26 GNT# ZV_LCDDATA19 AF8 1 2
GPAR M25 AE9 1 2 1 2 +3VRUN
<9> GPAR
3

GSTOP# PAR ZV_LCDDATA20 MEM_ID2 R9 R635 0_0402_5%~D

<9> GSTOP# N26 STOP# ZV_LCDDATA21 AF9 MEM_ID2 <11>
GDEVSEL# V29 AG10 MEM_ID0 10K_0402_5%~D 1 2 VDD_CORE1.8
<9> GDEVSEL# DEVSEL# ZV_LCDDATA22 MEM_ID0 <11>
GTRDY# V28 AF10 MEM_ID1 RP1
<9> GTRDY# TRDY# ZV_LCDDATA23 MEM_ID1 <11>
GIRDY# W29 10K_0804_8P4R_5%~D R636 @ 0_0402_5%~D
<9> GIRDY# IRDY#
1 2 GFRAME# W28 AJ10 LCDCNTL0 1 8
<9> GFRAME# FRAME# ZV_LCDCNTL0
R693 0_0402_5%~D GIRQA# AE26 AK10 LCDCNTL1 2 7
<9> GIRQA# INTA# ZV_LCDCNTL1
AJ11 LCDCNTL2 3 6

PCI/AGP
GWBF# ZV_LCDCNTL2 LCDCNTL3
<9> GWBF# AC26 WBF# ZV_LCDCNTL3 AH11 4 5

STP_AGP# AH30 AE10 1 2

<9> STP_AGP# STP_AGP# DVOMODE
AGP_BUSY# AH29 R602 0_0402_5%~D
<9> AGP_BUSY# AGP_BUSY#
GRBF# AE29 AK16 TXOUT_L0-
<9> GRBF# RBF# TXOUT_L0N TXOUT_L0- <8>
GADSTB0 M28 AH16 TXOUT_L0+
<9> GADSTB0 AD_STBF_0 TXOUT_L0P TXOUT_L0+ <8>
GADSTB1 V25 AH17 TXOUT_L1-
<9> GADSTB1 AD_STBF_1 TXOUT_L1N TXOUT_L1- <8>
GADSTB0# M29 AJ16 TXOUT_L1+
<9> GADSTB0# AD_STBS_0 TXOUT_L1P TXOUT_L1+ <8>
GADSTB1# V26 AH18 TXOUT_L2-
AGP MODE Ra Rb <9> GADSTB1# AD_STBS_1 TXOUT_L2N TXOUT_L2- <8>
AJ17 TXOUT_L2+
GSBA[7..0] TXOUT_L2P TXOUT_L2+ <8>
AGP 2.0 (4X) .75V 1K 1% 1K 1% GSBA0 AD28 AK19

LVDS
<9> GSBA[7..0] SBA0 TXOUT_L3N
GSBA1 AD29 AH19 BLON
GSBA2 SBA1 TXOUT_L3P TXCLK_L-
AGP 3.0 (8X) .35V 324R 1% 100R 1% AC28 SBA2 TXCLK_LN AK18 TXCLK_L- <8>
GSBA3 AC29 AJ18 TXCLK_L+
TXCLK_L+ <8>

AGP8X
SBA3 TXCLK_LP

2
GSBA4 AA28 AG16 TXOUT_U0-
SBA4 TXOUT_U0N TXOUT_U0- <8>
1 GSBA5 AA29 AF16 TXOUT_U0+ R687
SBA5 TXOUT_U0P TXOUT_U0+ <8>
Ra Rb C95 GSBA6 Y28 AG17 TXOUT_U1-
SBA6 TXOUT_U1N TXOUT_U1- <8>
GSBA7 Y29 AF17 TXOUT_U1+ 10K_0402_5%~D
SBA7 TXOUT_U1P TXOUT_U1+ <8>
R79 R81 0.1U_0402_10V6K~D AF18 TXOUT_U2-
TXOUT_U2- <8>

1
2 GST[2..0] GST0 TXOUT_U2N TXOUT_U2+
+1.5VRUN 1 2 1 2 <9> GST[2..0] AF29 ST0 TXOUT_U2P AE18 TXOUT_U2+ <8>
GST1 AD27 AH20
1K_0402_1%~D 1K_0402_1%~D GST2 ST1 TXOUT_U3N
AE28 ST2 TXOUT_U3P AG20
AF19 TXCLK_U-
B TXCLK_UN TXCLK_U- <8> B
PLACE AGPREF DIVIDER CIRCUIT CLOSE TO ASIC GSBSTB AB29 AG19 TXCLK_U+
<9> GSBSTB SB_STBF TXCLK_UP TXCLK_U+ <8>
GSBSTB# AB28 AE12 FPVCC
<9> GSBSTB# SB_STBS DIGON FPVCC <8,9> +3VRUN
AG12 BLON R684 0_0402_5%~D
BLON/(BLON#) BLON <8>
M26 AGPREF 1 2 1 2 1 2
R13 1 2 47_0402_5%~D M27 AJ13 R14 R15
+1.5VRUN AGPTEST TX0M DVI_TX0- <9>

@ 6.8K_0402_5%~D
R17 1 2 47K_0402_5%~D AH14 330_0402_5%~D 330_0402_5%~D
TX0P DVI_TX0+ <9>

4.7K_0402_5%~D

R130

4.7K_0402_5%~D
R131
<9> G_DBI_HI G_DBI_HI AB25 AJ14 +3VRUN
DBI_HI TX1M DVI_TX1- <9>
<9> G_DBI_LO G_DBI_LO AB26 AH15
DBI_LO TX1P DVI_TX1+ <9>

1
+1.5VRUN R19 1 2 47K_0402_5%~D AJ15
TX2M DVI_TX2- <9>

R129
AGP8X_DET# AC25 AK15
<9> AGP8X_DET# AGP8X_DET# TMDS TX2P DVI_TX2+ <9>
R16 1 2 47K_0402_5%~D AH13 Q11
TXCM DVI_CLK- <9>

1
+3VRUN D- R21 R22 @ BSN20
<11> D- AE11 DMINUS TXCP AK13 DVI_CLK+ <9>
D+
<11> D+ AF11
THRM 1 2 1 2

2
R18 715_0402_1%~D DPLUS DVI_DDCCLK DVI_DDC2CLK
DDC2CLK AE13 2 3 DVI_DDC2CLK <9>
1 2 AK21 AE14 330_0402_5%~D 330_0402_5%~D DVI_DDCDAT
DAC2_C/R R2SET DDC2DATA
<9> DAC2_C/R AJ23 C_R
DAC2_Y/G AJ22 AF12 DVI_DETECT1 +3VRUN
<9> DAC2_Y/G Y_G HPD1 DVI_DETECT1 <9>

@ 6.8K_0402_5%~D
DAC2

DAC2_COMP/B AK22
<9> DAC2_COMP/B COMP_B

1
AJ24 AK27 DAC1_RED
H2SYNC R DAC1_RED <9>

R132
AK24 AJ27 DAC1_GRN
V2SYNC G DAC1_GRN <9>
AJ26 DAC1_BLU Q12
B DAC1_BLU <9>

1
DAC2_DDC3CLK AG23 AG25 DAC1_HSY @ BSN20
<11> DAC2_DDC3CLK DDC3CLK HSYNC DAC1_HSY <9>
DAC1

DAC2_DDC3DAT AG24 AH25 DAC1_VSY

<11> DAC2_DDC3DAT DAC1_VSY <9>

2
R24 1K_0402_1%~D DDC3DATA VSYNC R28 1 DVI_DDC2DAT
RSET AH26 2 499_0402_1%~D 2 3 DVI_DDC2DAT <9>
1 2 AK25 AF25 DAC1_DDCDAT
SSIN DDC1DATA DAC1_DDCCLK DAC1_DDCDAT <9>
T1 PAD~D
R27 @ 0_0402_5%~D
AJ25 SSOUT SSC DDC1CLK AF24
AF26
DAC1_DDCCLK <9> R686 0_0402_5%~D
AUXWIN
1
1
2
2
AH28
AJ29
XTALIN CLK B6
1 2

R29 0_0402_5%~D XTALOUT TEST_MCLK/(NC)

TEST_YCLK/(NC) E8
1 2 AH27 TESTEN PLLTEST/(NC) AE25
Rt R32 1K_0402_1%~DAG26 AG29 1 2
A R23 1 SUS_STAT# RSTB_MSK/(NC) A
<11> OSC_IN 2 121_0402_1%~D R33 PLACE TMDS TERMINATION
R25 1 2 22_0402_5%~D 216PBCGA15F_BGA708 1K_0402_1%~D
<11> OSC3.3_OUT <9> ICH_SUSTAT# RESISTORS CLOSE TO ASIC
C3 X1 R26
0.1U_0402_10V6K~D 4 3 1 2 VID_CLK
+3VRUN
1
VCC OUT DELL CONFIDENTIAL/PROPRIETARY
1

2 1 @ 121_0402_1%~D
R30 GND E/D R31
27.000MHz Rs
Compal Electronics, Inc.
1K_0402_1%~D 2 71.5_0402_1%~D Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
MOBILITY M11-P_A
2

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, October 05, 2004 Sheet 2 of 12
5 4 3 2 1
 1 2 3 4 5 6 7 8

U1B
M11-P
http://laptop117.com U1C
M11-P
MDA0 L25 E22 MAA0 MDB0 D7 N5 MAB0
DQA0 AA0 DQB0 AB0
MDA1
MDA2
L26 DQA1 (2/6) AA1 B22 MAA1
MAA2
MDB1
MDB2
F7 DQB1 (3/6) AB1 M1 MAB1
MAB2
K25 DQA2 AA2 B23 E7 DQB2 AB2 M3
A MDA3 MAA3 MDB3 MAB3 A
K26 DQA3 AA3 B24 G6 DQB3 AB3 L3
MDA4 J26 C23 MAA4 MDB4 G5 L2 MAB4
MDA5 DQA4 AA4 MAA5 MDB5 DQB4 AB4 MAB5
H25 DQA5 AA5 C22 F5 DQB5 AB5 M2
MDA6 H26 F22 MAA6 MDB6 E5 M5 MAB6
MDA7 DQA6 AA6 MAA7 MDB7 DQB6 AB6 MAB7
G26 DQA7 AA7 F21 C4 DQB7 AB7 P6
MDA8 G30 C21 MAA8 MDB8 B5 N3 MAB8
MDA9 DQA8 AA8 MAA9 MDB9 DQB8 AB8 MAB9
D29 DQA9 AA9 A24 C5 DQB9 AB9 K2
MDA10 D28 C24 MAA10 MDB10 A4 K3 MAB10
MDA11 DQA10 AA10 MAA11 MDB11 DQB10 AB10 MAB11
E28 DQA11 AA11 A25 B4 DQB11 AB11 J2
MDA12 E29 E21 MAA12 MDB12 C2 P5 MAB12
MDA13 DQA12 AA12/(AA13) MAA13 MDB13 DQB12 AB12/(AB13) MAB13
G29 DQA13 AA13/(AA12) B20 D3 DQB13 AB13/(AB12) P3
MDA14 G28 C19 MDB14 D1 P2
MDA15 DQA14 AA14/(NC) MDB15 DQB14 AB14/(NC)
F28 DQA15 D2 DQB15
MDA16 G25 J25 DQMA#0 MDB16 G4 E6 DQMB#0
MDA17 DQA16 DQMA#0 DQMA#1 MDB17 DQB16 DQMB#0 DQMB#1
F26 DQA17 DQMA#1 F29 H6 DQB17 DQMB#1 B2
MDA18 E26 E25 DQMA#2 MDB18 H5 J5 DQMB#2
MDA19 DQA18 DQMA#2 DQMA#3 MDB19 DQB18 DQMB#2 DQMB#3
F25 DQA19 DQMA#3 A27 J6 DQB19 DQMB#3 G3
MDA20 E24 F15 DQMA#4 MDB20 K5 W6 DQMB#4

MEMORY INTERFACE B
MDA21 DQA20 DQMA#4 DQMA#5 MDB21 DQB20 DQMB#4 DQMB#5
F23 DQA21 DQMA#5 C15 K4 DQB21 DQMB#5 W2
MDA22 E23 C11 DQMA#6 MDB22 L6 AC6 DQMB#6
MDA23 DQA22 DQMA#6 DQMA#7 MDB23 DQB22 DQMB#6 DQMB#7
D22 DQA23 DQMA#7 E11 L5 DQB23 DQMB#7 AD2
MDA24 B29 MDB24 G2
MDA25 DQA24 MDB25 DQB24 QSB0
C29 DQA25 F3 DQB25 QSB0 F6
MDA26 C25 J27 QSA0 MDB26 H2 B3 QSB1
DQA26 QSA0 DQB26 QSB1
MEMORY INTERFACE
MDA27 C27 F30 QSA1 MDB27 E2 K6 QSB2
MDA28 DQA27 QSA1 QSA2 MDB28 DQB27 QSB2 QSB3
B28 DQA28 QSA2 F24 F2 DQB28 QSB3 G1
MDA29 B25 B27 QSA3 MDB29 J3 V5 QSB4
MDA30 DQA29 QSA3 QSA4 MDB30 DQB29 QSB4 QSB5
C26 DQA30 QSA4 E16 F1 DQB30 QSB5 W1
MDA31 B26 B16 QSA5 MDB31 H3 AC5 QSB6
MDA32 DQA31 QSA5 QSA6 MDB32 DQB31 QSB6 QSB7
F17 DQA32 QSA6 B11 U6 DQB32 QSB7 AD1
MDA33 E17 F10 QSA7 MDB33 U5
MDA34 DQA33 QSA7 MDB34 DQB33 RASB#
D16 DQA34 U3 DQB34 RASB# R2
B MDA35 MDB35 B
F16 DQA35 V6 DQB35
MDA36 E15 MDB36 W5 T5 CASB#
MDA37 DQA36 RASA# MDB37 DQB36 CASB#
F14 DQA37 RASA# A19 W4 DQB37
MDA38 E14 MDB38 Y6 T6 WEB#
MDA39 DQA38 CASA# MDB39 DQB38 WEB#
F13 DQA39 CASA# E18 Y5 DQB39
MDA40 C17 MDB40 U2 R5 CSB0#
MDA41 DQA40 WEA# MDB41 DQB40 CSB0#
B18 DQA41 WEA# E19 V2 DQB41
MDA42 B17 MDB42 V1 R6 CSB1#
MDA43 DQA42 CSA0# MDB43 DQB42 CSB1#
A

B15 DQA43 CSA0# E20 V3 DQB43

MDA44 C13 MDB44 W3 R3 CKEB
MDA45 DQA44 CSA1# MDB45 DQB44 CKEB
B14 DQA45 CSA1# F20 Y2 DQB45
MDA46 C14 MDB46 Y3 N1 CLKB0
MDA47 DQA46 CKEA MDB47 DQB46 CLKB0 CLKB0#
C16 DQA47 CKEA B19 AA2 DQB47 CLKB0# N2
MDA48 A13 MDB48 AA6
MDA49 DQA48 MDB49 DQB48 CLKB1
A12 DQA49 AA5 DQB49 CLKB1 T2
MDA50 C12 B21 CLKA0 MDB50 AB6 T3 CLKB1#
MDA51 DQA50 CLKA0 CLKA0# MDB51 DQB50 CLKB1#
B12 DQA51 CLKA0# C20 AB5 DQB51
MDA52 C10 VDD_MEM_IO MDB52 AD6
MDA53 DQA52 CLKA1 MDB53 DQB52 VDD_CORE1.8
C9 DQA53 CLKA1 C18 AD5 DQB53
MDA54 B9 A18 CLKA1# MDB54 AE5
MDA55 DQA54 CLKA1# 1
MDB55 DQB54 R37 1
B10 DQA55 AE4 DQB55 MEMVMODE0 C6 2 4.7K_0402_5%~D
MDA56 E13 D30 DIMA_0 R34 MDB56 AB2 C7 1 2
DQA56 DIMA0 DQB56 MEMVMODE1

@
MDA57 E12 B13 DIMA_1 MDB57 AB3 R38 4.7K_0402_5%~D
MDA58 DQA57 DIMA1 1K_0402_1%~D MDB58 DQB57 DIMB_0
E10 DQA58 AC2 DQB58 DIMB0 E3
MDA59 F12 VREF = .50*VDDQ MDB59 AC3 AA3 DIMB_1

@ 4.7K_0402_5%~D
2

MDA60 DQA59 MDB60 DQB59 DIMB1

F11 B7 AD3
DQA60 MVREFD DQB60 FOR 2.5V VDDR1

1
4.7K_0402_5%~D

R40

R41
MDA61 E9 MDB61 AE1
DQA61 DQB61
1

MDA62 F9 DQA62 MVREFS/(NC) B8 1 MDB62 AE2 DQB62 MEMTEST C8 MEMVMODE0 = 1.8V

MDA63 F8 R36 C4 MDB63 AE3
DQA63 DQB63 MEMVMODE1 = GND

1
1K_0402_1%~D 0.1U_0402_10V6K~D 216PBCGA15F_BGA708 R39 FOR 1.8V VDDR1(ELPIDA)

2
216PBCGA15F_BGA708 2
MEMVMODE0 = GND
2

C 47_0402_5%~D C
MEMVMODE1 = 1.8V

2
VDD_MEM_IO

RASA# PLACE MVREF DIVIDER COMPONENTS RASB#

<5,6> RASA# <5,7> RASB#
1

AS CLOSE TO ASIC AS POSSIBLE

CASA# R42 CASB#
<5,6> CASA# <5,7> CASB#
WEA# 1K_0402_1%~D WEB#
<5,6> WEA# <5,7> WEB#
2

CSA0# CSB0#
<5,6> CSA0# <5,7> CSB0#
1

CSA1# 1 CSB1#
<5,6> CSA1# <5,7> CSB1#
R43 C5
CKEA CKEB
<5,6> CKEA <5,7> CKEB
1K_0402_1%~D 0.1U_0402_10V6K~D
CLKA0 2 CLKB0
<6> CLKA0 <7> CLKB0
2

CLKA0# CLKB0#
<6> CLKA0# <7> CLKB0#
CLKA1 CLKB1
<6> CLKA1 <7> CLKB1
CLKA1# CLKB1#
<6> CLKA1# <7> CLKB1#
QSA[7..0] QSB[7..0]
<5,6> QSA[7..0] <5,7> QSB[7..0]
DQMA#[7..0] DQMB#[7..0]
<5,6> DQMA#[7..0] <5,7> DQMB#[7..0]
MDA[63..0] MDB[63..0]
<5,6> MDA[63..0] <5,7> MDB[63..0]
MAA[13..0] MAB[13..0]
<5,6> MAA[13..0] <5,7> MAB[13..0]
D DIMA_0 DIMB_0 D
<5,6> DIMA_0 <5,7> DIMB_0
<5,6> DIMA_1 DIMA_1 <5,7> DIMB_1 DIMB_1

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MOBILITY M11-P_B,C
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 3 of 12
1 2 3 4 5 6 7 8
 5 4 3 2 1

U1F VDD_CORE

http://laptop117.com
M11-P
M12 VDDC (6/6) VDDC AD15
M13 VDDC VDDC AD13
+3VRUN M14 AC17
VDDC VDDC
M17 VDDC VDDC AC15
U1D M18 AC13
VDDC VDDC

1
VDD_MEM_IO B1
M11-P D1
M19
N12
VDDC
T12 (105MA 1.5V VDDCI)
VDDR1 VDD_CORE VDDC VDDCI
B30 VDDR1 (4/6) 2.4V N13 VDDC VDDCI M15
A15 VDDR1 VDDRH0 F18 VDD_MEM_CLK N14 VDDC VDDCI W16

CORE POWER
A21 N6 N17 R19

2
22U_1206_6.3VAM~D VDDR1 VDDRH1 VDDC VDDCI

22U_1206_6.3VAM~D
1 1 A28 VDDR1 N18 VDDC
D D
A3 VDDR1 N19 VDDC
C6

C7

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
A9 VDDR1 VSSRH0 F19 1 1 1 1 1 1 1 1 1 1 P12 VDDC VSS R12

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17
AA1 VDDR1 VSSRH1 M6 P13 VDDC VSS R13
2 2
AA4 VDDR1 P14 VDDC VSS T13
AA7 VDDR1 P17 VDDC VSS R14
2 2 2 2 2 2 2 2 2 2
AA8 VDDR1 P18 VDDC VSS T14
AD4 VDDR1 MPVDD A7 VDD_MEM_PLL P19 VDDC VSS N15
D5 VDDR1 MPVSS A6 MPVSS U12 VDDC VSS P15
D8 VDDR1 U13 VDDC VSS R15
1000P_0402_50V7K~D

1000P_0402_50V7K~D 1000P_0402_50V7K~D
D11 VDDR1 U14 VDDC VSS T15
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1 1 1 1 D13 VDDR1 PVDD AK28 VDD_PLL U17 VDDC VSS U15

D14 VDDR1 PVSS AJ28 PVSS U18 VDDC VSS V15
C18

C19

C20

C21
D17 VDDR1 U19 VDDC VSS W15
D20 VDDR1 V12 VDDC VSS H16
2 2 2 2
D23 VDDR1 V13 VDDC VSS M16
D26 VDDR1 VDDR3 AC19 V14 VDDC VSS N16
E27 VDDR1 VDDR3 AC21 V17 VDDC VSS P16
F4 VDDR1 VDDR3 AC22 V18 VDDC VSS R16
G7 VDDR1 VDDR3 AC8 V19 VDDC VSS T16
G10 AD19 +3VRUN W12 U16
VDDR1 VDDR3 VDDC VSS
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1 1 1 G13 VDDR1 VDDR3 AD21 W13 VDDC VSS V16

G15 VDDR1 VDDR3 AD22 W14 VDDC VSS R17
C22

C23

C24

G19 VDDR1 VDDR3 AD7 W17 VDDC VSS T17

G22 VDDR1 W18 VDDC VSS R18
2 2 2

22U_1206_6.3VAM~D

22U_1206_6.3VAM~D

1000P_0402_50V7K~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D

0.1U_0402_10V6K~D
G27 VDDR1 Trace width 40mil 1 1 1 1 1 1 W19 VDDC VSS T18

C25

C133

C132

C26

C27

C2
H10 VDDR1 VSS T19
H13 VDDR1 VDDR4 AC10
H15 VDDR1 VDDR4 AC9
2 2 2 2 2 2
H17 VDDR1 VDDR4 AD10
H19 AD9 216PBCGA15F_BGA708
VDDR1 VDDR4
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D

1 1 1 H22 VDDR1 VDDR4 AG7 +VDDR4

J1 VDDR1 1 2
C28

C29

C30

C L41 C
J23 VDDR1 1 1 1 1

I/O POWER
J24 BLM21AF121SN1D_0805~D
2 2 2 VDDR1
J4 VDDR1 VDDP AA23
J7 AA24 C31 C32 C33 C34 0.1U_0402_10V6K~D
VDDR1 VDDP 0.1U_0402_10V6K~D 2 2 2 2
J8 VDDR1 VDDP AB30
L27 AC23 0.1U_0402_10V6K~D
VDDR1 VDDP 0.1U_0402_10V6K~D
L8 VDDR1 VDDP AC27
M4 AE30 U1E
VDDR1 VDDP
N4 VDDR1 VDDP AF27 M11-P
N7 VDDR1 VDDP J30 (56MA 1.5V VDDP)
N8 VDDR1 VDDP M23 +1.5VRUN (5/6)
R1 VDDR1 VDDP M24 A10 VSS

22U_1206_6.3VAM~D

22U_1206_6.3VAM~D

1000P_0402_50V7K~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D

0.1U_0402_10V6K~D
T4 VDDR1 VDDP N30 1 1 1 1 1 1 A16 VSS VSS H4

C35

C36

C37

C38

C39

C40
T7 VDDR1 VDDP P23 A2 VSS VSS H8
T8 VDDR1 VDDP P27 A22 VSS VSS H9
V4 VDDR1 VDDP T23 A29 VSS VSS H12
2 2 2 2 2 2
V7 VDDR1 VDDP T24 AA30 VSS VSS H14
V8 VDDR1 VDDP T30 AB1 VSS VSS H18
VDD15 D19 U27 AB23 H21
VDDR1/(CLKAFB) VDDP VSS VSS
R4 VDDR1/(CLKBFB) VDDP V23 AB24 VSS VSS H23
L3 (65 MA 1.5V VDD15) V24 AB27 H27
VDDP VSS VSS
1 2 AC11 VDDC15/(VDDC18) VDDP W30 AB4 VSS VSS K1
AC20 VDDC15/(VDDC18) VDDP Y27 AB7 VSS VSS K23
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

22U_1206_6.3VAM~D

BLM21AF121SN1D_0805~D 1 1 1 H11 AB8 K24

VDDC15/(VDDC18) VSS VSS
H20 VDDC15/(VDDC18) AC12 VSS VSS K27
C137

C136

C135

L23 VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25) AE20 VDD_PNLIO2.5 AC14 VSS VSS K30

P8 VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25) AE17 AC16 VSS VSS K7
2 2 2
Y23 VDDC15/(VDDC18) LVDDR_18 AF21 VDD_PNL_IO1.8 AC18 VSS VSS K8
Y8 AE15 AC4 L4

CORE POWER
VDDC15/(VDDC18) LVDDR_18 VSS VSS
LPVDD AJ20 VDD_PNL_PLL AD12 VSS VSS M30
AD16 VSS VSS M7
AD18 VSS VSS M8
B B
VDD_PNL_PLL AK12 TPVDD LVSSR AF20 AD25 VSS VSS N23
LTPVSS AJ12 TPVSS LVSSR AF15 AD30 VSS VSS N24
LVSSR AE19 AE27 VSS VSS N27
LVSSR AE16 AG11 VSS VSS P4
LPVSS AJ19 LTPVSS AG15 VSS VSS R23
AVDD_1.8 AH24 AVDD AG18 VSS VSS R24
AG21 A2VDD AG22 VSS VSS R30
VDD_DAC2.5 AH21 A2VDD VDD1DI AE24 VDDDI_1.8 AG27 VSS VSS R7
A2VDDQ_1.8 AF22 A2VDDQ VDD2DI AE22 AG5 VSS VSS R8
AG9 VSS VSS T1
AJ1 VSS VSS T27
VSS1DI AE23 DVSSDI AJ30 VSS VSS U23
AH22 A2VSSN VSS2DI AE21 AK2 VSS VSS U4
AJ21 A2VSSN AK29 VSS VSS U8
A2VSSQ AF23 A2VSSQ C1 VSS VSS V30
TXVDDR AF13 C28 VSS VSS W23
TXVDDR AF14 C3 VSS VSS W24
C30 VSS VSS W27
AH23 AVSSN D10 VSS VSS W7
AVSSQ AD24 AVSSQ TXVSSR AG13 D12 VSS VSS W8
TXVSSR AG14 D15 VSS VSS Y4
TXVSSR AH12 D18 VSS VSS G9
D21 VSS VSS G12
D24 VSS VSS G16
D25 VSS VSS G18
D27 VSS VSS G21
216PBCGA15F_BGA708 D4 G24
VSS VSS
D6 VSS
D9 VSS
E4 VSS
F27 VSS
A A

216PBCGA15F_BGA708

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MOBILITY M11-P_D,E
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 4 of 12
5 4 3 2 1
 5 4 3 2 1

MDA1
MDA4
MDA3
MDA7
RP2
1
2
3
4
100_0804_8P4R_5%
8
7
6
5
1
+VTT1
MDA32
MDA33
MDA35
MDA34
RP15 100_0804_8P4R_5%
1
2
3
4
8
7
6
5 http://laptop117.com
1
+VTT1
MDB6
MDB5
MDB4
MDB3
RP23 100_0804_8P4R_5%
1
2
3
4
8
7
6
5
1
+VTT2
MDB38
MDB39
MDB36
MDB37
RP36 100_0804_8P4R_5%
1
2
3
4
8
7
6
5
1
+VTT2

0.1U_0402_10V6K~D

C537

0.1U_0402_10V6K~D

C538

0.1U_0402_10V6K~D

C539

0.1U_0402_10V6K~D

C540
RP3 100_0804_8P4R_5% RP16 100_0804_8P4R_5% RP24 100_0804_8P4R_5% RP37 100_0804_8P4R_5%
MDA5 1 8 MDA36 1 8 MDB1 1 8 MDB33 1 8
MDA6 2 7 MDA38 2 7 MDB2 2 7 MDB34 2 7
MDA2 2 MDA37 2 MDB0 2 MDB32 2
3 6 3 6 3 6 3 6
MDA0 4 5 MDA39 4 5 MDB7 4 5 MDB35 4 5
D DQMA#0 DQMA#4 DQMB#0 DQMB#4 D
1 2 1 1 2 1 1 2 1 1 2 1

0.1U_0402_10V6K~D

C567

0.1U_0402_10V6K~D

C569

0.1U_0402_10V6K~D

C576

0.1U_0402_10V6K~D

C578
R668 100_0402_1%~D R664 100_0402_1%~D R678 100_0402_1%~D R675 100_0402_1%~D
RP4 100_0804_8P4R_5% RP17 100_0804_8P4R_5% RP25 100_0804_8P4R_5% RP38 100_0804_8P4R_5%
MDA11 1 8 MDA40 1 8 MDB15 1 8 MDB43 1 8
MDA10 2 MDA41 2 MDB13 2 MDB41 2
2 7 2 7 2 7 2 7
MDA9 3 6 MDA47 3 6 MDB12 3 6 MDB40 3 6
MDA12 4 5 MDA42 4 5 MDB14 4 5 MDB42 4 5
1 1 1 1
0.1U_0402_10V6K~D

C544

0.1U_0402_10V6K~D

C545

0.1U_0402_10V6K~D

C546

0.1U_0402_10V6K~D

C547
RP5 100_0804_8P4R_5% RP18 100_0804_8P4R_5% RP26 100_0804_8P4R_5% RP39 100_0804_8P4R_5%
MDA8 1 8 MDA43 1 8 MDB11 1 8 MDB47 1 8
MDA13 2 7 MDA44 2 7 MDB10 2 7 MDB45 2 7
MDA15 2 MDA45 2 MDB8 2 MDB46 2
3 6 3 6 3 6 3 6
MDA14 4 5 MDA46 4 5 MDB9 4 5 MDB44 4 5

DQMA#1 1 2 1 DQMA#5 1 2 1 DQMB#1 1 2 1 DQMB#5 1 2 1

0.1U_0402_10V6K~D

C563

0.1U_0402_10V6K~D

C570

0.1U_0402_10V6K~D

C572

0.1U_0402_10V6K~D

C581
R662 100_0402_1%~D R665 100_0402_1%~D R672 100_0402_1%~D R674 100_0402_1%~D
DIMA_0 1 2 DIMA_1 1 2 DIMB_0 1 2 DIMB_1 1 2 +3VRUN
R663 100_0402_1%~D R666 100_0402_1%~D R673 100_0402_1%~D R670 100_0402_1%~D
RP6 100_0804_8P4R_5% 2 RP19 100_0804_8P4R_5% 2 RP27 100_0804_8P4R_5% 2 RP40 100_0804_8P4R_5% 2
MDA16 1 8 MDA50 1 8 MDB19 1 8 MDB48 1 8 1
MDA17 2 7 MDA51 2 7 MDB17 2 7 MDB49 2 7 C541
MDA19 3 6 MDA48 3 6 MDB16 3 6 MDB50 3 6
1 1 1 1
VTT REGULATORS
0.1U_0402_10V6K~D

C549

0.1U_0402_10V6K~D

C550

0.1U_0402_10V6K~D

C551

0.1U_0402_10V6K~D

C552
MDA18 4 5 MDA49 4 5 MDB18 4 5 MDB51 4 5 22U_1206_6.3VAM~D
2
RP7 100_0804_8P4R_5% RP20 100_0804_8P4R_5% RP28 100_0804_8P4R_5% RP41 100_0804_8P4R_5%
MDA20 2 MDA55 2 MDB20 2 MDB53 2
1 8 1 8 1 8 1 8

1K_0402_1%~D
MDA22 2 7 MDA54 2 7 MDB21 2 7 MDB55 2 7

5
6
7
8
MDA23 3 6 MDA52 3 6 MDB23 3 6 MDB54 3 6 REG72

R637
MDA21 4 5 1 MDA53 4 5 1 MDB22 4 5 1 MDB52 4 5 1 1 4

VCNTL
VCNTL#6
VCNTL#7
VCNTL#8
IN VOUT +VTT1
0.1U_0402_10V6K~D

C566

0.1U_0402_10V6K~D

C571

0.1U_0402_10V6K~D

C573

0.1U_0402_10V6K~D

C579
DQMA#2 1 2 DQMA#6 1 2 DQMB#2 1 2 DQMB#6 1 2
R667 100_0402_1%~D R659 100_0402_1%~D R676 100_0402_1%~D R677 100_0402_1%~D

2
C RP8 100_0804_8P4R_5% 2 RP21 100_0804_8P4R_5% 2 RP29 100_0804_8P4R_5% 2 RP42 100_0804_8P4R_5% 2 C
3 REFEN GND 2 1
MDA25 1 8 MDA63 1 8 MDB29 1 8 MDB61 1 8

1
1K_0402_1%~D

1K_0402_1%~D
MDA27 2 7 MDA62 2 7 MDB31 2 7 MDB62 2 7 Q20 RT9173CS + C542

R638

R639
MDA28 3 6 1 MDA61 3 6 1 MDB26 3 6 1 MDB60 3 6 1 @ 2N7002LT1 1 330U_D4_6.3VM
0.1U_0402_10V6K~D

C554

0.1U_0402_10V6K~D

C555

0.1U_0402_10V6K~D

C556

0.1U_0402_10V6K~D

C557
MDA24 4 5 MDA58 4 5 MDB24 4 5 MDB63 4 5 C543
2
<2,10> POW_SW 1
RP9 100_0804_8P4R_5% RP22 100_0804_8P4R_5% RP30 100_0804_8P4R_5% RP43 100_0804_8P4R_5% 0.1U_0402_10V6K~D

2
MDA31 2 MDA56 2 MDB28 2 MDB57 2 2
1 8 1 8 1 8 1 8

2
MDA26 2 7 MDA57 2 7 MDB30 2 7 MDB59 2 7
MDA29 3 6 MDA60 3 6 MDB25 3 6 MDB56 3 6
MDA30 4 5 1 MDA59 4 5 1 MDB27 4 5 1 MDB58 4 5 1
0.1U_0402_10V6K~D

C562

0.1U_0402_10V6K~D

C568

0.1U_0402_10V6K~D

C575

0.1U_0402_10V6K~D

C580
DQMA#3 1 2 DQMA#7 1 2 DQMB#3 1 2 DQMB#7 1 2
R660 100_0402_1%~D R661 100_0402_1%~D R671 100_0402_1%~D R669 100_0402_1%~D VDD_MEM_IO
2 2 2 2

1K_0402_1%~D
1

5
6
7
8
RP10 100_0804_8P4R_5% RP31 100_0804_8P4R_5% REG73

R640
RASA# 1 8 MAB12 1 8 1 4

VCNTL
VCNTL#6
VCNTL#7
VCNTL#8
IN VOUT +VTT2
MAA11 2 7 1 CSB0# 2 7 1
0.1U_0402_10V6K~D

C558

0.1U_0402_10V6K~D

C559
MAA8 3 6 MAB2 3 6
MAA3 4 5 WEB# 4 5

2
3 REFEN GND 2 1
RP11 100_0804_8P4R_5% 2 RP32 100_0804_8P4R_5% 2

1
1K_0402_1%~D

1K_0402_1%~D
MAA0 1 8 RASB# 1 8 RT9173CS + C548

R641

R642
CASA# 2 7 MAB5 2 7 1 330U_D4_6.3VM
CKEA 3 6 1 MAB13 3 6 1 C553
2
0.1U_0402_10V6K~D

C564

0.1U_0402_10V6K~D

C577
CSA0# 4 5 MAB8 4 5 1
0.1U_0402_10V6K~D

2
RP12 100_0804_8P4R_5% RP33 100_0804_8P4R_5% Q21 2

2
MAA6 2 MAB11 2 @ 2N7002LT1
1 8 1 8
MAA7 2 7 MAB4 2 7
MAA12 3 6 MAB10 3 6
WEA# 4 5 1 MAB9 4 5 1
0.1U_0402_10V6K~D

C560

0.1U_0402_10V6K~D

C561
B B
RP13 100_0804_8P4R_5% RP34 100_0804_8P4R_5%
MAA9 1 8 CKEB 1 8
MAA10 2 MAB1 2
2 7 2 7
MAA5 3 6 CSB1# 3 6
MAA4 4 5 R643 1 2 180_0402_5%~D QSA0 MAB3 4 5 R644 1 2 180_0402_5%~D QSB0
1 R645 1 2 180_0402_5%~D QSA1 1 R646 1 2 180_0402_5%~D QSB1
0.1U_0402_10V6K~D

C565

0.1U_0402_10V6K~D

C574

RP14 100_0804_8P4R_5% R647 1 2 180_0402_5%~D QSA2 RP35 100_0804_8P4R_5% R648 1 2 180_0402_5%~D QSB2
MAA13 1 8 R649 1 2 180_0402_5%~D QSA3 MAB6 1 8 R650 1 2 180_0402_5%~D QSB3
CSA1# 2 7 R651 1 2 180_0402_5%~D QSA4 MAB0 2 7 R652 1 2 180_0402_5%~D QSB4
MAA1 2 R653 180_0402_5%~D QSA5 MAB7 2 R654 180_0402_5%~D QSB5
3 6 1 2 3 6 1 2
MAA2 4 5 R655 1 2 180_0402_5%~D QSA6 CASB# 4 5 R656 1 2 180_0402_5%~D QSB6
R657 1 2 180_0402_5%~D QSA7 R658 1 2 180_0402_5%~D QSB7

DQMA#[7..0] DQMB#[7..0]
<3,6> DQMA#[7..0] <3,7> DQMB#[7..0]
MAA[13..0] MAB[13..0]
<3,6> MAA[13..0] <3,7> MAB[13..0]
QSA[7..0] QSB[7..0]
<3,6> QSA[7..0] <3,7> QSB[7..0]
MDA[63..0] MDB[63..0]
<3,6> MDA[63..0] <3,7> MDB[63..0]
RASA# RASB#
<3,6> RASA# <3,7> RASB#
CASA# CASB#
<3,6> CASA# <3,7> CASB#
WEA# WEB#
<3,6> WEA# <3,7> WEB#
CSA0# CSB0#
A <3,6> CSA0# <3,7> CSB0# A
CSA1# CSB1#
<3,6> CSA1# <3,7> CSB1#
CKEA CKEB
<3,6> CKEA <3,7> CKEB

<3,6> DIMA_0 DIMA_0 <3,7> DIMB_0 DIMB_0

DIMA_1 DIMB_1
<3,6> DIMA_1 <3,7> DIMB_1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MEMORY PU TERM
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 5 of 12
5 4 3 2 1
 5 4 3 2 1

http://laptop117.com
U3 U4
MAA12 M3 A7 MDA1 MAA12 M3 A7 MDA50
MAA13 BA0 DQ31 MDA3 MAA13 BA0 DQ31 MDA48
L4 BA1 DQ30 B8 L4 BA1 DQ30 B8
A8 MDA4 A8 MDA51
MAA11 DQ29 MDA7 MAA11 DQ29 MDA49
L6 A11 DQ28 A9 L6 A11 DQ28 A9
MAA10 K5 B12 MDA5 MAA10 K5 B12 MDA55
MAA9 A10 DQ27 MDA6 MAA9 A10 DQ27 MDA54
L7 A9 DQ26 C11 L7 A9 DQ26 C11
MAA8 M10 C12 MDA2 MAA8 M10 C12 MDA52
MAA7 A8/AP DQ25 MDA0 MAA7 A8/AP DQ25 MDA53
M9 A7 DQ24 D12 M9 A7 DQ24 D12
MAA6 M8 J2 MDA25 MAA6 M8 J2 MDA63
MAA5 A6 DQ23 MDA27 MAA5 A6 DQ23 MDA62
L8 A5 DQ22 J1 L8 A5 DQ22 J1
MAA4 M7 H1 MDA24 MAA4 M7 H1 MDA58
MAA3 A4 DQ21 MDA28 MAA3 A4 DQ21 MDA61
M6 A3 DQ20 H2 M6 A3 DQ20 H2
D MAA2 L5 F1 MDA31 MAA2 L5 F1 MDA56 DQMA#[7..0] D
A2 DQ19 A2 DQ19 <3,5> DQMA#[7..0]
MAA1 M5 F2 MDA26 MAA1 M5 F2 MDA57
MAA0 A1 DQ18 MDA29 MAA0 A1 DQ18 MDA60 MAA[13..0]
M4 A0 DQ17 E1 M4 A0 DQ17 E1 <3,5> MAA[13..0]
E2 MDA30 E2 MDA59
DQ16 MDA11 DQ16 MDA40 QSA[7..0]
B3 NC DQ15 E11 B3 NC DQ15 E11 <3,5> QSA[7..0]
(ELPIDA) VREF = .42*VDDQ (1.0K/715K) B10 E12 MDA10 B10 E12 MDA41
NC#B10 DQ14 MDA9 NC#B10 DQ14 MDA47 MDA[63..0]
G3 NC#G3 DQ13 F11 G3 NC#G3 DQ13 F11 <3,5> MDA[63..0]
(SSTL-2) VREF = .49*VDDQ (1.0K/1.0K) G10 F12 MDA12 G10 F12 MDA42
DIMA_0 NC#G10 DQ12 MDA13 DIMA_1 NC#G10 DQ12 MDA44
K11 NC#K11 DQ11 H11 K11 NC#K11 DQ11 H11
VDD_MEM_IO K12 H12 MDA8 K12 H12 MDA43 RASA#
NC#K12 DQ10 NC#K12 DQ10 <3,5> RASA#
L2 J11 MDA14 VDD_MEM_IO L2 J11 MDA46 CASA#
NC#L2 DQ9 NC#L2 DQ9 <3,5> CASA#
CSA1# L3 J12 MDA15 CSA1# L3 J12 MDA45 WEA#
NC#L3 DQ8 NC#L3 DQ8 <3,5> WEA#
1

M2 D1 MDA16 M2 D1 MDA32 CSA0#

NC#M2 DQ7 NC#M2 DQ7 <3,5> CSA0#

1
R50 C1 MDA17 C1 MDA33 CSA1#
DQ6 DQ6 <3,5> CSA1#
C2 MDA19 R51 C2 MDA35 CKEA
DQ5 DQ5 <3,5> CKEA
1K_0402_1%~D L12 B1 MDA18 L12 B1 MDA34 <3,5> DIMA_0 DIMA_0
MCL DQ4 MDA20 1K_0402_1%~D MCL DQ4 MDA36 DIMA_1
A4 A4 <3,5> DIMA_1
2

DQ3 MDA23 DQ3 MDA37

M12 A5 M12 A5

1 2
VREF DQ2 MDA22 VREF DQ2 MDA38
DQ1 B5 DQ1 B5
1

1 L9 A6 MDA21 1 L9 A6 MDA39
R52 C41 RFU#L9 DQ0 R53 C42 RFU#L9 DQ0

VDDQ K8 RFU B2 VDDQ K8 RFU B2

1K_0402_1%~D 0.1U_0402_10V6K~D B4 1K_0402_1%~D 0.1U_0402_10V6K~D B4
2 CLKA0#_R VDDQ#B4 2 CLKA1#_R VDDQ#B4
L11 CLK B6 L11 B6
2

2
VDDQ#B6 VDDQ#B6 CLK
VDDQ#B7 B7 VDDQ#B7 B7
CSA0# M1 CS B9 CSA0# M1 CS B9
VDDQ#B9 VDDQ#B9
VDDQ#B11 B11 VDDQ#B11 B11
RASA# L1 RAS D2 VDD_MEM_IO RASA# L1 RAS D2 VDD_MEM_IO
VDDQ#D2 VDDQ#D2
VDDQ#D11 D11 VDDQ#D11 D11
CASA# K1 CAS E3 CASA# K1 CAS E3
VDDQ#E3 VDDQ#E3
VDDQ#E10 E10 VDDQ#E10 E10
WEA# K2 WE F3 WEA# K2 WE F3
C VDDQ#F3 VDDQ#F3 C
VDDQ#F10 F10 VDDQ#F10 F10
DQMA#0 A11 DM3 H3 DQMA#6 A11 DM3 H3
VDDQ#H3 VDDQ#H3
VDDQ#H10 H10 VDDQ#H10 H10
DQMA#3 G2 DM2 J3 MEM_VDD DQMA#7 G2 DM2 J3 MEM_VDD R54 10_0402_5%~D
VDDQ#J3 VDDQ#J3 CLKA0_R
VDDQ#J10 J10 VDDQ#J10 J10 <3> CLKA0 1 2
DQMA#1 G11 DM1 C6 DQMA#5 G11 DM1 C6
VDD VDD R55 10_0402_5%~D
VDD#C7 C7 VDD#C7 C7
DQMA#2 A2 DM0 D3 DQMA#4 A2 DM0 D3 1 2 CLKA0#_R
VDD#D3 VDD#D3 <3> CLKA0#
VDD#D10 D10 VDD#D10 D10
CLKA0_R L10 CLK K3 CLKA1_R L10 CLK K3
VDD#K3 VDD#K3

1
VDD#K6 K6 VDD#K6 K6
CKEA M11 CKE K7 CKEA M11 CKE K7 R56 R57
VDD#K7 VDD#K7
VDD#K10 K10 VDD#K10 K10
A3 A3 56_0402_5%~D 56_0402_5%~D
VSSQ VSSQ
A10 A10

2
QSA0 VSSQ#A10 QSA6 VSSQ#A10
A12 DQS3 VSSQ#C3 C3 A12 DQS3 VSSQ#C3 C3
VSSQ#C4 C4 VSSQ#C4 C4
QSA3 G1 DQS2 C5 QSA7 G1 DQS2 C5
VSSQ#C5 VSSQ#C5
VSSQ#C8 C8 VSSQ#C8 C8 1
QSA1 G12 DQS1 C9 QSA5 G12 DQS1 C9 C43
VSSQ#C9 VSSQ#C9
VSSQ#C10 C10 VSSQ#C10 C10
QSA2 A1 DQS0 D5 QSA4 A1 DQS0 D5 470P_0402_50V7K~D
VSSQ#D5 VSSQ#D5 2
VSSQ#D8 D8 VSSQ#D8 D8
VSSQ#E4 E4 VSSQ#E4 E4
VSSQ#E9 E9 VSSQ#E9 E9
MEMORY GROUP 5(DQS5,DM5,DQ40:47) CANNOT BE BYTE SWAPPED VSSQ#F4 F4 MEMORY GROUP 5(DQS5,DM5,DQ40:47) CANNOT BE BYTE SWAPPED VSSQ#F4 F4
VSSQ#F9 F9 VSSQ#F9 F9
VSSQ#G4 G4 VSSQ#G4 G4
E5 TH GND VSSQ#G9 G9 E5 TH GND VSSQ#G9 G9
E6 TH GND#E6 VSSQ#H4 H4 E6 TH GND#E6 VSSQ#H4 H4
E7 TH GND#E7 VSSQ#H9 H9 E7 TH GND#E7 VSSQ#H9 H9
E8 TH GND#E8 VSSQ#J4 J4 E8 TH GND#E8 VSSQ#J4 J4
B B
F5 TH GND#F5 VSSQ#J9 J9 F5 TH GND#F5 VSSQ#J9 J9
F6 TH GND#F6 F6 TH GND#F6
F7 TH GND#F7 VSS D4 F7 TH GND#F7 VSS D4
F8 TH GND#F8 VSS#D6 D6 F8 TH GND#F8 VSS#D6 D6
G5 TH GND#G5 VSS#D7 D7 G5 TH GND#G5 VSS#D7 D7
G6 TH GND#G6 D9 G6 TH GND#G6 D9 R58 10_0402_5%~D
VSS#D9 VSS#D9 CLKA1_R
G7 TH GND#G7 VSS#J5 J5 G7 TH GND#G7 VSS#J5 J5 <3> CLKA1 1 2
G8 TH GND#G8 VSS#J6 J6 G8 TH GND#G8 VSS#J6 J6
H5 TH GND#H5 J7 H5 TH GND#H5 J7 R59 10_0402_5%~D
VSS#J7 VSS#J7 CLKA1#_R
H6 TH GND#H6 VSS#J8 J8 H6 TH GND#H6 VSS#J8 J8 <3> CLKA1# 1 2
H7 TH GND#H7 VSS#K4 K4 H7 TH GND#H7 VSS#K4 K4
H8 TH GND#H8 VSS#K9 K9 H8 TH GND#H8 VSS#K9 K9

1
R60 R61

128_64Hyn@: Pop Samsung 4MX32E-2A/700 FEGA 2.5V 128_64Hyn@: Pop Samsung 4MX32E-2A/700 FEGA 2.5V 56_0402_5%~D 56_0402_5%~D
128_64SAM@: Pop Hynix 4MX32-28/700 FBGA 128_64SAM@: Pop Hynix 4MX32-28/700 FBGA

2
64@: Pop Hynix 8M32-33/600 FBGA 2.5V 64@: Pop Hynix 8M32-33/600 FBGA 2.5V
4/8MX32 (ELPIDA OR STACKED) BGA MEMORY 4/8MX32 (ELPIDA OR STACKED) BGA MEMORY 1
C44

470P_0402_50V7K~D
VDD_MEM_IO MEM_VDD VDD_MEM_IO MEM_VDD 2

2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0402_10V6K~D

C45

1U_0603_10V4Z~D

C46

1000P_0402_50V7K~D

C47

0.01U_0402_16V7K~D

C48

22U_1206_6.3VAM~D

C49

0.1U_0402_10V6K~D

C55

1U_0603_10V4Z~D

C56

0.01U_0402_16V7K~D

C57

22U_1206_6.3VAM~D

C58

1000P_0402_50V7K~D

C50

1U_0603_10V4Z~D

C51

0.1U_0402_10V6K~D

C52

0.01U_0402_16V7K~D

C53

22U_1206_6.3VAM~D

C54

0.1U_0402_10V6K~D

C59

1U_0603_10V4Z~D

C60

0.1U_0402_10V6K~D

C61

0.01U_0402_16V7K~D

C62

22U_1206_6.3VAM~D

C63
A 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DDR 4MX32 BGA A
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 6 of 12
5 4 3 2 1
 5 4 3 2 1

http://laptop117.com
U5 U6
MAB12 M3 A7 MDB19 MAB12 M3 A7 MDB57
MAB13 BA0 DQ31 MDB16 MAB13 BA0 DQ31 MDB56
L4 BA1 DQ30 B8 L4 BA1 DQ30 B8
A8 MDB17 A8 MDB59
MAB11 DQ29 MDB18 MAB11 DQ29 MDB58
L6 A11 DQ28 A9 L6 A11 DQ28 A9
MAB10 K5 B12 MDB21 MAB10 K5 B12 MDB61
MAB9 A10 DQ27 MDB20 MAB9 A10 DQ27 MDB62
L7 A9 DQ26 C11 L7 A9 DQ26 C11
MAB8 M10 C12 MDB23 MAB8 M10 C12 MDB60
MAB7 A8/AP DQ25 MDB22 MAB7 A8/AP DQ25 MDB63
M9 A7 DQ24 D12 M9 A7 DQ24 D12
MAB6 M8 J2 MDB29 MAB6 M8 J2 MDB38
MAB5 A6 DQ23 MDB31 MAB5 A6 DQ23 MDB39
L8 A5 DQ22 J1 L8 A5 DQ22 J1
MAB4 M7 H1 MDB24 MAB4 M7 H1 MDB37
MAB3 A4 DQ21 MDB26 MAB3 A4 DQ21 MDB36
M6 A3 DQ20 H2 M6 A3 DQ20 H2
D MAB2 MDB28 MAB2 MDB33 D
L5 A2 DQ19 F1 L5 A2 DQ19 F1
MAB1 M5 F2 MDB30 MAB1 M5 F2 MDB34
MAB0 A1 DQ18 MDB25 MAB0 A1 DQ18 MDB32
M4 A0 DQ17 E1 M4 A0 DQ17 E1
E2 MDB27 E2 MDB35 DQMB#[7..0]
DQ16 DQ16 <3,5> DQMB#[7..0]
(ELPIDA) VREF = .42*VDDQ (1.0K/715K) B3 E11 MDB15 (ELPIDA) VREF = .42*VDDQ (1.0K/715K) B3 E11 MDB43
NC DQ15 MDB13 NC DQ15 MDB41 MAB[13..0]
B10 NC#B10 DQ14 E12 B10 NC#B10 DQ14 E12 <3,5> MAB[13..0]
(SSTL-2) VREF = .49*VDDQ (1.0K/1.0K) G3 F11 MDB12 (SSTL-2) VREF = .49*VDDQ (1.0K/1.0K) G3 F11 MDB40
NC#G3 DQ13 MDB14 NC#G3 DQ13 MDB42 QSB[7..0]
G10 NC#G10 DQ12 F12 G10 NC#G10 DQ12 F12 <3,5> QSB[7..0]
DIMB_0 K11 H11 MDB10 DIMB_1 K11 H11 MDB45
VDD_MEM_IO NC#K11 DQ11 MDB11 VDD_MEM_IO NC#K11 DQ11 MDB47 MDB[63..0]
K12 NC#K12 DQ10 H12 K12 NC#K12 DQ10 H12 <3,5> MDB[63..0]
L2 J11 MDB9 L2 J11 MDB44
CSB1# NC#L2 DQ9 MDB8 CSB1# NC#L2 DQ9 MDB46
L3 NC#L3 DQ8 J12 L3 NC#L3 DQ8 J12
1

1
M2 D1 MDB1 M2 D1 MDB48 RASB#
NC#M2 DQ7 NC#M2 DQ7 <3,5> RASB#
R62 C1 MDB2 R63 C1 MDB49 CASB#
DQ6 DQ6 <3,5> CASB#
C2 MDB0 C2 MDB50 WEB#
DQ5 DQ5 <3,5> WEB#
1K_0402_1%~D L12 B1 MDB7 1K_0402_1%~D L12 B1 MDB51 CSB0#
MCL DQ4 MCL DQ4 <3,5> CSB0#
A4 MDB6 A4 MDB53 CSB1#
<3,5> CSB1#
2

2
DQ3 MDB4 DQ3 MDB54 CKEB
VREF = .42*VDDQ M12 VREF DQ2 A5 VREF = .42*VDDQ M12 VREF DQ2 A5 <3,5> CKEB
B5 MDB5 B5 MDB55 <3,5> DIMB_0 DIMB_0
DQ1 DQ1
1

1
1 L9 A6 MDB3 1 L9 A6 MDB52 <3,5> DIMB_1 DIMB_1
R65 C65 RFU#L9 DQ0 R64 C64 RFU#L9 DQ0

VDDQ K8 RFU B2 K8 RFU VDDQ B2

1K_0402_1%~D 0.1U_0402_10V6K~D B4 1K_0402_1%~D 0.1U_0402_10V6K~D B4
2 CLKB0#_R VDDQ#B4 2 CLKB1#_R VDDQ#B4
L11 CLK B6 L11 B6
2

2
VDDQ#B6 CLK VDDQ#B6
VDDQ#B7 B7 VDDQ#B7 B7
CSB0# M1 CS B9 CSB0# M1 B9
VDDQ#B9 CS VDDQ#B9
VDDQ#B11 B11 VDDQ#B11 B11
RASB# L1 RAS D2 VDD_MEM_IO RASB# L1 D2 VDD_MEM_IO
VDDQ#D2 RAS VDDQ#D2
VDDQ#D11 D11 VDDQ#D11 D11
CASB# K1 CAS E3 CASB# K1 E3
VDDQ#E3 CAS VDDQ#E3
VDDQ#E10 E10 VDDQ#E10 E10
WEB# K2 WE F3 WEB# K2 F3
C VDDQ#F3 WE VDDQ#F3 C
VDDQ#F10 F10 VDDQ#F10 F10
DQMB#2 A11 DM3 H3 DQMB#7 A11 H3
VDDQ#H3 DM3 VDDQ#H3
VDDQ#H10 H10 VDDQ#H10 H10
DQMB#3 G2 DM2 J3 MEM_VDD DQMB#4 G2 J3 MEM_VDD
VDDQ#J3 DM2 VDDQ#J3
VDDQ#J10 J10 VDDQ#J10 J10
DQMB#1 G11 DM1 C6 DQMB#5 G11 C6
VDD DM1 VDD
VDD#C7 C7 VDD#C7 C7
DQMB#0 A2 DM0 D3 DQMB#6 A2 D3 R66 10_0402_5%~D
VDD#D3 DM0 VDD#D3 CLKB0_R
VDD#D10 D10 VDD#D10 D10 <3> CLKB0 1 2
CLKB0_R L10 CLK K3 CLKB1_R L10 K3
VDD#K3 CLK VDD#K3 R67 10_0402_5%~D
VDD#K6 K6 VDD#K6 K6
CKEB M11 CKE K7 CKEB M11 K7 1 2 CLKB0#_R
VDD#K7 CKE VDD#K7 <3> CLKB0#
VDD#K10 K10 VDD#K10 K10

1
VSSQ A3 VSSQ A3
A10 A10 R68 R69
QSB2 VSSQ#A10 QSB7 VSSQ#A10
A12 DQS3 VSSQ#C3 C3 A12 DQS3 VSSQ#C3 C3
C4 C4 56_0402_5%~D 56_0402_5%~D
QSB3 VSSQ#C4 QSB4 VSSQ#C4
G1 DQS2 C5 G1 C5

2
VSSQ#C5 DQS2 VSSQ#C5
VSSQ#C8 C8 VSSQ#C8 C8
QSB1 G12 DQS1 C9 QSB5 G12 C9 1
VSSQ#C9 DQS1 VSSQ#C9 C66
VSSQ#C10 C10 VSSQ#C10 C10
QSB0 A1 DQS0 D5 QSB6 A1 D5
VSSQ#D5 DQS0 VSSQ#D5 470P_0402_50V7K~D
VSSQ#D8 D8 VSSQ#D8 D8
2
VSSQ#E4 E4 VSSQ#E4 E4
VSSQ#E9 E9 VSSQ#E9 E9
MEMORY GROUP 1(DQS1,DM1,DQ8:15) CANNOT BE BYTE SWAPPED VSSQ#F4 F4 MEMORY GROUP 5(DQS5,DM5,DQ40:47) CANNOT BE BYTE SWAPPED VSSQ#F4 F4
VSSQ#F9 F9 VSSQ#F9 F9
VSSQ#G4 G4 VSSQ#G4 G4
E5 TH GND VSSQ#G9 G9 E5 TH GND VSSQ#G9 G9
E6 TH GND#E6 VSSQ#H4 H4 E6 TH GND#E6 VSSQ#H4 H4
E7 TH GND#E7 VSSQ#H9 H9 E7 TH GND#E7 VSSQ#H9 H9
E8 TH GND#E8 VSSQ#J4 J4 E8 TH GND#E8 VSSQ#J4 J4
B B
F5 TH GND#F5 VSSQ#J9 J9 F5 TH GND#F5 VSSQ#J9 J9
F6 TH GND#F6 F6 TH GND#F6
F7 TH GND#F7 VSS D4 F7 TH GND#F7 VSS D4
F8 TH GND#F8 VSS#D6 D6 F8 TH GND#F8 VSS#D6 D6
G5 TH GND#G5 VSS#D7 D7 G5 TH GND#G5 VSS#D7 D7
G6 TH GND#G6 VSS#D9 D9 G6 TH GND#G6 VSS#D9 D9
G7 TH GND#G7 J5 G7 J5 R70 10_0402_5%~D
VSS#J5 TH GND#G7 VSS#J5 CLKB1_R
G8 TH GND#G8 VSS#J6 J6 G8 TH GND#G8 VSS#J6 J6 <3> CLKB1 1 2
H5 TH GND#H5 VSS#J7 J7 H5 TH GND#H5 VSS#J7 J7
H6 TH GND#H6 J8 H6 J8 R71 10_0402_5%~D
VSS#J8 TH GND#H6 VSS#J8 CLKB1#_R
H7 TH GND#H7 VSS#K4 K4 H7 TH GND#H7 VSS#K4 K4 <3> CLKB1# 1 2
H8 TH GND#H8 VSS#K9 K9 H8 TH GND#H8 VSS#K9 K9

1
R72 R73

128_64Hyn@: Pop Samsung 4MX32E-2A/700 FEGA 2.5V 128_64Hyn@: Pop Samsung 4MX32E-2A/700 FEGA 2.5V 56_0402_5%~D 56_0402_5%~D
128_64SAM@: Pop Hynix 4MX32-28/700 FBGA 128_64SAM@: Pop Hynix 4MX32-28/700 FBGA

2
64@: Pop Hynix 8M32-33/600 FBGA 2.5V 64@: Pop Hynix 8M32-33/600 FBGA 2.5V 1
C67
4/8MX32 (ELPIDA OR STACKED) BGA MEMORY 4/8MX32 (ELPIDA OR STACKED) BGA MEMORY
470P_0402_50V7K~D
2
VDD_MEM_IO MEM_VDD VDD_MEM_IO MEM_VDD

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0402_10V6K~D

C68

1U_0603_10V4Z~D

C69

1000P_0402_50V7K~D

C70

22U_1206_6.3VAM~D

C71

0.1U_0402_10V6K~D

C76

1U_0603_10V4Z~D

C77

0.1U_0402_10V6K~D

C78

0.01U_0402_16V7K~D

C79

22U_1206_6.3VAM~D

C80

0.1U_0402_10V6K~D

C72

1U_0603_10V4Z~D

C73

0.1U_0402_10V6K~D

C74

22U_1206_6.3VAM~D

C75

0.1U_0402_10V6K~D

C81

1U_0603_10V4Z~D

C82

0.1U_0402_10V6K~D

C83

0.01U_0402_16V7K~D

C84

22U_1206_6.3VAM~D

C85
A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DDR 4MX32 BGA B
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 7 of 12
5 4 3 2 1
 5 4 3 2 1

http://laptop117.com +3VRUN

1
C586
R696
0.1U_0402_10V6K~D
4.7K_0402_5%~D U21 2
TC7SH08FU_SSOP5~D

5
D D
POK 1

P
<10> POK B
4 BACKLITE_ON
BLON O
<2> BLON 2 A

G
3
1
R697

@ 0_0402_5%~D
G_PWR_SRC

2
L42

1 2

0.01U_0402_25V7K~D

C106
FBM-11-201209-300AT_0805~D 1 1 C107
+VDDR4

1000P_0402_50V7K~D
2 2

1
R607
LCD CONNECTOR

1
4.7K_0402_5%~D Q16
BSN20 B1
LCD_STAT 2 3 J2
2

1 PLACE CAP AND BEAD +5VALW 1

C221 LAMP_STAT B+
1 2 CLOSE TO CONNECTOR 2 B+
R608 @ 0_0402_5%~D 3
470P_0402_50V7K~D GND11
1 4 GND12
2 C110 PBAT_SMBDAT B11 5 PBAT_SMBDAT
C PBAT_SMBCLK B9 C
6 PBAT_SMBCLK
VDD_CORE1.8 0.1U_0402_10V6K~D 7
2 BACKLITE_ON B10 5VALW
8 5VSUS
@ BSN20 9 FPBACK
1

Q17 INV_PWR_SRC 10
R89 PID3
11 PID2
LCD_TST 2 3 LCD_TEST 1 2 12
+15V 22_0603_5%~D PID1
13 PID0
1

LCDVCC 14
R610 LCDVCC2
15 LCDVCC1

2
+3VRUN

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
R609 1 2 1 16 GND10

22U_1206_6.3VAM~D

C111

C112

C113
1 2 @ 2.2K_0402_5%~D R90 17
Q3 VEDID
18
2

0_0402_5%~D 100K_0402_5%~D SI4410DY_SO8~D I2C_DAT B8 GND9

19 PANEL_I2C_CLK
2 1 2 I2C_CLK B6
1 8 20

1
+3VRUN PANEL_I2C_DAT
1 2 7 21 GND8
C114 3 6 PLACE BEADS TXOUT_L0+ 22 TXUCLKOUT+
5 CLOSE TO CONNECTOR TXOUT_L0- 23 TXUCLKOUT-
0.01U_0402_25V7K~D 24
2 TXOUT_L1+ GND7
25

4
TXUOUT2+

1
TXOUT_L1- 26
+3VRUN R91 TXUOUT2-
+3VRUN 27 GND6
TXOUT_L2+ 28 TXUOUT1+
0.1U_0402_10V6K~D

C115

1 100K_0402_5%~D TXOUT_L2- 29 TXUOUT1-

1 2 30

2
GND5

1000P_0402_50V7K~D

C116

0.1U_0402_10V6K~D

C117
TXCLK_L+ 31
TXCLK_L- TXUOUT0+
32 TXUOUT0-
2
33 GND4
2 1 TXOUT_U0+ 34 TXLCLKOUT+ MGND11 55
TXOUT_U0- 35 54
TXLCLKOUT- MGND10
5

U9 36 53
GND3 MGND9
1

D TXOUT_U1+ 37 52
P

B FPVCC Q4 TXOUT_U1- TXLOUT2+ MGND8 B

2 A Y 4 2 38 TXLOUT2- MGND7 51
G 2N7002_SOT23~D 39 50
GND2 MGND6
G

NC7SZ04M5X_SOT23~D S TXOUT_U2+ 40 49
3

TXOUT_U2- TXLOUT1+ MGND5

41 48
3

TXLOUT1- MGND4
42 GND1 MGND3 47
TXCLK_U+ 43 46
TXCLK_U- TXLOUT0+ MGND2
44 TXLOUT0- MGND1 45

TXOUT_L0- PLACE CAPS ON THIS PAGE AS CLOSE TO CONNECTOR AS POSSIBLE

<2> TXOUT_L0- JAE_FI-TD44SB-L~D
TXOUT_L0+
<2> TXOUT_L0+
TXOUT_L1-
<2> TXOUT_L1-
TXOUT_L1+
<2> TXOUT_L1+
TXOUT_L2-
<2> TXOUT_L2-
TXOUT_L2+
<2> TXOUT_L2+
TXCLK_L-
<2> TXCLK_L-
TXCLK_L+
<2> TXCLK_L+

TXOUT_U0-
<2> TXOUT_U0-
TXOUT_U0+
<2> TXOUT_U0+
TXOUT_U1-
<2> TXOUT_U1-
TXOUT_U1+
<2> TXOUT_U1+
TXOUT_U2-
<2> TXOUT_U2-
TXOUT_U2+
<2> TXOUT_U2+
TXCLK_U-
<2> TXCLK_U-
TXCLK_U+
<2> TXCLK_U+

FPVCC
<2,9> FPVCC
I2C_CLK
<2> I2C_CLK
I2C_DAT
A <2> I2C_DAT A
PBAT_SMBCLK
<9,11> PBAT_SMBCLK
PBAT_SMBDAT
<9,11> PBAT_SMBDAT
LCD_TST
<2>
<2>
LCD_TST
LCD_STAT
LCD_STAT DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
FPD CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 8 of 12
5 4 3 2 1
 5 4 3 2 1

J1

<2>

<2>

<2>
GAD[31..0]

GSBA[7..0]

<2> GC/BE#[3..0]

GST[2..0]
GAD[31..0]

GSBA[7..0]

GC/BE#[3..0]

GST[2..0]
http://laptop117.com DVI_TX0+

DVI_TX0-
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
FPVCC DVI_TX1+ 11 12
<2,8> FPVCC 11 12
STP_AGP# 13 14
<2> STP_AGP# 13 14
AGP_BUSY# DVI_TX1- 15 16
D <2> AGP_BUSY# 15 16 D
GRBF# 17 18
<2> GRBF# 17 18
GADSTBF0 DVI_TX2+ 19 20 DVI_CLK+
<2> GADSTB0 19 20
GADSTBF1 21 22
<2> GADSTB1 21 22
GSBSTBF DVI_TX2- 23 24 DVI_CLK-
<2> GSBSTB 23 24
GWBF# 25 26
<2> GWBF# 25 26
GSBSTBS 27 28 DVI_DDC2CLK
<2> GSBSTB# 27 28
GADSTBS0 29 30
<2> GADSTB0# 29 30
GADSTBS1 31 32 DVI_DDC2DAT
<2> GADSTB1# 31 32
CK_66M_AGP R84 0_0402_5%~D 33 34
<2> CK_66M_AGP 33 34
GRST# AGP8X_DET# 1 2 AGP8X_DET_CG 35 36 DVI_DETECT1
<2> GRST# 35 36
GREQ# 1 2 AGP8X_DET_GC 37 38 +3VRUN
<2> GREQ# 37 38
GGNT# R85 0_0402_5%~D 39 40 GIRQA#
<2> GGNT# 39 40

0.1U_0402_10V6K~D
GPAR 41 42
<2> GPAR 41 42

1000P_0402_50V7K~D
GSTOP# CK_66M_AGP 43 44
<2> GSTOP# 43 44
GDEVSEL# 45 46 1 1
<2> GDEVSEL# 45 46

C99

C100
GTRDY# GREQ# 47 48 +1.5VRUN
<2> GTRDY# 47 48
GIRDY# GST0 49 50 GST1
<2> GIRDY# 49 50
GFRAME# GST2 51 52
<2> GFRAME# 51 52 2 2
GIRQA# 53 54 GSBA0
<2> GIRQA# 53 54
PBAT_SMBCLK GSBSTBF 55 56 GSBA1
<8,11> PBAT_SMBCLK 55 56
PBAT_SMBDAT GSBSTBS 57 58 GSBA3
<8,11> PBAT_SMBDAT 57 58
RUNPWROK 59 60
<10> RUNPWROK 59 60
<2> ICH_SUSTAT# ICH_SUSTAT# GSBA2 61 62 GSBA5
AGP8X_DET# GSBA4 61 62 GSBA7
<2> AGP8X_DET# 63 63 64 64
OTEMP GSBA6 65 66 GDEVSEL#
<11> OTEMP 65 66
DVI_TX0+ RUNPWROK 67 68 GRST#
<2> DVI_TX0+ DVI_TX0- 67 68
<2> DVI_TX0- +1.5VRUN 69 69 70 70
DVI_TX1+ 71 72
<2> DVI_TX1+ DVI_TX1- GIRDY# 71 72 GRBF#
<2> DVI_TX1- 73 73 74 74
DVI_TX2+ GTRDY# 75 76 GWBF#
<2> DVI_TX2+ DVI_TX2- GSTOP# 75 76 GFRAME#
<2> DVI_TX2- 77 77 78 78 IT IS NOW RECOMMENDED TO USE OFF BOARD
DVI_CLK+ GC/BE#3 79 80 GAD30
C <2> DVI_CLK+ DVI_CLK- 81
79 80
82
GENERATED VREFGC FOR MOTHERBOARD CHIPSET C
<2> DVI_CLK- DVI_DDC2DAT GAD31 81 82 GAD28
<2> DVI_DDC2DAT 83 83 84 84
DVI_DDC2CLK GAD29 85 86 GAD26
<2> DVI_DDC2CLK DVI_DETECT1 85 86
<2> DVI_DETECT1 87 87 88 88
+1.5VRUN
VREFGC RESISTOR SELECTION
DAC2_C/R GADSTBS1 89 90 GAD24
<2> DAC2_C/R DAC2_Y/G GADSTBF1 89 90 GAD22
<2> DAC2_Y/G 91 91 92 92
<2> DAC2_COMP/B
DAC2_COMP/B 93 94 AGP MODE Rc Rd
DAC1_RED GAD27 93 94 GAD20
<2> DAC1_RED 95 95 96 96

1
1K_0402_1%~D
DAC1_GRN GAD25 97 98 GAD18
<2> DAC1_GRN 97 98
<2> DAC1_BLU
DAC1_BLU GC/BE#2 99 100 GAD23 AGP 2.0 (4X) .75V 1K 1% 1K 1%
+5VRUN 99 100

R80
G_DBI_HI 101 102 Rc
<2> G_DBI_HI 101 102
G_DBI_LO R83 GAD21 103 104 GAD17 R78
<2> G_DBI_LO 103 104
@ 0_0402_5%~D GAD19 105 106 GAD16 @ 0_0402_5%~D AGP 3.0 (8X) .35V 324R 1% 100R 1%

2
105 106
1

D G_DBI_HI 1 2 107 107 108 108 1 2 G_DBI_LO

GC_BL_SUSPEND 2 Q13 +1.5VRUN 109 110 AGP_BUSY#
G SI2301DS_SOT23~D 109 110 VREFGC
111 111 112 112 1 2
S 113 114 R77 0_0402_5%~D
3

GAD15 113 114 GC/BE#1

115 115 116 116

0.1U_0402_10V6K~D
0.1U_0402_10V6K~D GAD13 117 118 GAD14
117 118

1
1K_0402_1%~D
1 1 C189 119 119 120 120 1
C188 1000P_0402_50V7K~D GAD11 121 122 GAD12
121 122

R82

C96
GAD9 123 124 GAD10 Rd
GAD7 123 124 GAD8
125 125 126 126
5
1

2 2 2 +5VRUN +3VRUN
127 128

2
GADSTBS0 127 128 GAD6
129 129 130 130
<2> DAC1_VSY DAC1_VSY 2 4 GADSTBF0 131 132 GAD4
131 132
133 133 134 134

1
U18 GAD5 135 136 GAD2
74HCT1G126GW GAD3 135 136 GAD0 R143 Q14 R142
137 138
3

GAD1 137 138 GC/BE#0 BSN20

139 139 140 140

1
141 142 @ 4.7K_0402_5%~D 6.8K_0402_5%~D
141 142 GPAR
1 2 143 144

2
B R681 @ 0_0402_5%~D DAC1_VSYNC 143 144 GGNT# DAC1_DDC1DAT DAC1_DDCDAT B
145 145 146 146 3 2 DAC1_DDCDAT <2>
147 147 148 148 +1.5VRUN
0.1U_0402_10V6K~D DAC1_HSYNC 149 150
149 150

1000P_0402_50V7K~D

0.1U_0402_10V6K~D
1 1 C192 151 152 GC_BL_SUSPEND 1 2
C191 1000P_0402_50V7K~D DAC1_RED 151 152 R679 @ 0_0402_5%~D
153 153 154 154
155 156 STP_AGP# 1 1
155 156 +5VRUN +3VRUN

C97

C98
DAC1_GRN 157 158 OTEMP
157 158
5
1

2 2
159 159 160 160
DAC1_BLU 161 162
DAC1_HSY 161 162 DAC1_DDC1DAT 2 2
<2> DAC1_HSY 2 4 163 163 164 164

1
DAC2_Y/G 165 166 DAC1_DDC1CLK
U19 165 166 R145 Q15 R144
167 167 168 168
74HCT1G126GW DAC2_C/R 169 170 BSN20
3

169 170

1
171 172 PBAT_SMBDAT @ 4.7K_0402_5%~D 6.8K_0402_5%~D
DAC2_COMP/B 171 172 PBAT_SMBCLK
173 174

2
173 174 DAC1_DDC1CLK DAC1_DDCCLK
1 2 175 175 176 176 3 2 DAC1_DDCCLK <2>
R682 @ 0_0402_5%~D 177 178 +3VRUN
177 178
179 179 180 180
ICH_SUSTAT# 181 182 +1.5VRUN 1 2
181 182
+5VSUS 183 183 184 184 +15V R680 @ 0_0402_5%~D
G_PWR_SRC 185 186 FPVCC
185 186

0.1U_0603_25V7K~D

1000P_0402_50V7K~D
187 187 188 188 +5VRUN
1000P_0402_50V7K~D

0.1U_0402_10V6K~D

47K_0402_5%~D

0.1U_0603_25V7K~D

1000P_0402_50V7K~D

189 189 190 190 +3VRUN

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
191 191 192 192 1 1
1

C89

C90
1 1 1 1 193 193 194 194 G_PWR_SRC 1 1
C86

C87

R688

C101

C102

C91

C92
195 195 196 196
197 197 198 198
2 2
199 199 200 200 +5VALW
2 2 2 2 2 2
201 202 1 1
2

201 202
0.1U_0402_10V6K~D

1000P_0402_50V7K~D
C93

C94
FOX_QT01200A-2120L~D
A 2 2 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MODULE CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 9 of 12
5 4 3 2 1
 1 2 3 4 5 6 7 8

G_PWR_SRC VDD_CORE
L1

http://laptop117.com
1 2 (5400 MA 1.2V VDDC)
VDD_MEM_IO POWER MEM_VDD POWER 1.8U_919AS-1R8N_9.5A_30%~D

10U_1210_25V6M~D

10U_1210_25V6M~D

0.1U_0603_25V7K~D

330U_D2E_2.5VM~D

330U_D2E_2.5VM~D

22U_1206_6.3VAM~D

22U_1206_6.3VAM~D
1 1 1 TOKO 1 1

C122

C123

C108
9.5A 1 1 +3VRUN

C118

C119

C120

C121

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
FBa FBb FBc FBd FBe FBf H=4.5MM + +

2 2 2
D7 2 2 2 2 1 1

1000P_0402_50V7K~D

C128

C129
1.8V Pop Depop Depop Pop 1.8V Depop Pop

10K_0603_1%~D
2

1
2.5V Depop Pop Pop Depop 2.5V Pop Depop 1 2 2

C127

R92
1 Ra
A A
3
+5VRUN Q5 2

2
BAT54S_SOT23~D
(15MA)
Thermal
Rc R93 40.2K_0603_1%~D
1 2 POW_SW PULLED OR DRIVEN HI = 1.0V VDDC
Pad 9
POW_SW PULLED OR DRIVEN LO = 1.2V VDDC
0.1U_0402_10V6K~D

1000P_0402_50V7K~D

10U_0805_10V4M~D
OPTIONAL

1
51.1K_0603_1%~D
4 5 1.5V Q6
1.0/1.2V REGULATOR

5
C124

C125

C126

R94
1 1 1 3 6 Rb IF NO 2N7002_SOT23~D U11

1
D
2 7 POWERPLAY

P
0.1U_0603_16V7K~D
1 1 8 LOGIC 2 4 Y A 2 POW_SW <2,5>

C130
R95 G

G
2 2 2

@ 10K_0603_1%~D
U10 FDS7096N3_SO8 @ 0_0603_5%~D S

10K_0603_1%~D
1 11 NC7SZ04M5X_SOT23~D

3
VIN VCC

1
R694 @ 0_0402_5%~D 2

R97

R98
+3VRUN 1 2
POK 2 15 REG1
<8> POK PWRGD BOOT Q7 S-1131B15UC-N4A-TF_SOT89-5~D
14 SI4410DY_SO8~D 5
+3VRUN VOUT 1 VDD15

2
RUNPWROK_R UGATE VIN
<9> RUNPWROK 1 2 3 EN 1 8

2.2uF

C229
ISL6224CB
2 7 4 3

VSS
EN NC

1000P_0402_50V7K~D
R695 0_0402_5%~D 13 3 6
PHASE +3VRUN
16 FCCM R100 5 1

C230

22uF 6.3V

C231
12 1 2

2
ISEN

1
1_0603_5%~D
300mA

4
2K_0603_1%~D

R101
4 OCSET 2
1.5V FIXED
LGATE 10 SOT-89-5
7

2
SOFT
PGND 9
G_PWR_SRC
100K_0603_5%~D

0.01U_0402_16V7K~D

8 GND 1.5V LINEAR REGULATOR

1

B B
R102

C134

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
5 6 L4
VOUT VSEN
10U_1210_25V6M~D

10U_1210_25V6M~D

1 2 VDD_CORE1.8
ISL6224CA_SSOP16~D 1 1 1
2

C140

C141

C142
1 1 BLM21AF121SN1D_0805~D (150 MA 1.8V VDDR4)
C138

C139

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
RUNPWROK_R 2 2 2
2 2 L5
1 2 VDD_PLL
1 1 1

C145

C146

C147
BLM21AF121SN1D_0805~D (30MA 1.8V PVDD)
2

3
D8 D9

2.5V 1
2 2 2
*
PVSS
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
BAT54S_SOT23~D C583 BAT54S_SOT23~D L6
1 2
REGULATOR 1 1 VDD_PNL_IO1.8
C131

C109
U12 2.2U_0805_16VFZ~D 1 1 1
2

C148

C149

C150
13 28 BLM21AF121SN1D_0805~D (80 MA 1.8V
1

1
1.8V_REG DDR VCC
14 LVDDR18,LVDDR18_25,TXVDDR)
2 VIN 2
2 2 2
@ BLM41PG600SN1L_1806

0.1U_0603_16V7K~D

FBf 6 BOOT1 BOOT2 23

1

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
ISL6227CA-T

1 1 L7
B12

C143

5 24 C144 1 2 VDD_PNL_PLL
(1840MA 2.5V EXT MEM VDD) UGATE1 UGATE2
1 1 1

C151

C152

C153
4 25 0.1U_0603_16V7K~D BLM21AF121SN1D_0805~D (40MA 1.8V LPVDD,TPVDD)
PHASE1 PHASE2 1.8V
8
7

7
8
MEM_VDD 2 2
Q9A 2 27 Q8A
REGULATOR *
2

R104 2K_0603_1%~D LGATE1 LGATE2 R105 2K_0603_1%~D 2 2 2

LTPVSS
FDS6912A_SO8~D 2 1 2 7 22 1 2 2 R689 0_0402_5%~D L10
ISEN1 ISEN2
1

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
30V 6A R690 0_0402_5%~D FDS6912A_SO8~D 1 2 1 2 A2VDDQ_1.8
BLM41PG600SN1L_1806

B13

C C
1 2 3 26 30V 6A 1 1 1
1

1
PGND1 PGND2

C159

C160

C161
R691 @ 0_0402_5%~D 10 19 R692 @ 0_0402_5%~D BLM21AF121SN1D_0805~D (5 MA 1.8V A2VDDQ)
VSEN1 VSEN2
FBe 1 2 9 VOUT1 VOUT2 20 1 2

8 21
2 2 2
A2VSSQ *
2

EN1 EN2

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
L9 R106 47K_0603_5%~D R107 100K_0603_5%~D L11
1 2 1 2 11 OCSET1 OCSET2 18 1 2 1 2 VDD_MEM_PLL
1.8V_REG
1 1 1
330U_D4_6.3VM

1000P_0402_50V7K~D

10K_0603_1%~D

C163

C164

C165
1 3.3U_FDV0630-3R3M_20% C156 1 2 12 17 C157 1 2 BLM21AF121SN1D_0805~D (5 MA 1.8V MPVDD)
SOFT1 SOFT2
1

1 TOKO L8
C158

C162

R109

+ FDV0630 0.1U_0402_10V6K~D 15 16 0.1U_0402_10V6K~D 1 2

4A
PG1 PG2/REF
3.3U_FDV0630-3R3M_20%
2 2 2
MPVSS *
6
5

H=3.0MM Q9B 30V 6A 1 L12

2 2 GND

1000P_0402_50V7K~D

330U_D4_6.3VM

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
TOKO 1 1 2 AVDD_1.8
2

10K_0603_1%~D
FDS6912A_SO8~D ISL6227CA-T_SSOP28~D FDV0630 1 1 1
BLM21AF121SN1D_0805~D

1
C154

R108

C155

C167

C168

C169
4 4A + (70 MA 1.8V AVDD)
1
1
C584

C585

5.49K_0603_1%~D

H=3.0MM
R110

*
3

2 2 2 2
1 1 2 AVSSQ
L14

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1 2 VDDDI_1.8
2

5
6
22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2 2 BLM21AF121SN1D_0805~D 1 1 1

10K_0603_1%~D

C174

C175

C176
L13 (140MA 2.5V A2VDD) Q8B (5 MA 1.8V VDD1DI,VDD2DI)

1
1 2 VDD_DAC2.5 +3VRUN

R111
BLM21AF121SN1D_0805~D 4
1 1 1 FDS6912A_SO8~D 2 2 2
DVSSDI *
C171

C172

C173

30V 6A
3

1
D10

2
22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

+3VRUN REG74
VOUT 5
2 2 2
(350MA 2.5V LVDDR_25)
VDD_PNLIO2.5
* PLACE CAPS FOR THESE GROUNDS CLOSE TO ASIC AND RUN DEDICATED TRACES
FROM PINS TO JOIN THE GROUND PLANE WITH ONE VIA AT CAP 2.4V
B4
(1580 MA 1.8V/2.5V EXT MEM VDDQ,VDDR1)
@ BLM41PG600SN1L_1806
1 1 1 FBa

2
VIN DVSSDI PVSS LTPVSS A2VSSQ MPVSS AVSSQ
C177

C178

D L15 D
1 2 VDD_MEM_IO
BYPASS 4 1 2
3 1 @ BLM21AF121SN1D_0805~D 1 2
EN 2 2
0.01U_0402_16V7K~D
C232

FBc L16 (INCLUDED IN VDD_MEM_IO) FBb B5 BLM41PG600SN1L_1806

0.1U_0402_10V6K~D

2.2U_0805_16VFZ~D

22U_1206_6.3VAM~D

0.1U_0402_10V6K~D

2 1 2
GND
2
BLM21AF121SN1D_0805~D 1 1
VDD_MEM_CLK
DELL CONFIDENTIAL/PROPRIETARY
C233

C234

C179

C180

1 1 SP6203EM5-2.8 _SOT23-5

FBd L17
Compal Electronics, Inc.
2 2 Title
1 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
2 2 @ BLM21AF121SN1D_0805~D
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
REGULATORS
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, October 05, 2004 Sheet 10 of 12
1 2 3 4 5 6 7 8
 5 4 3 2 1

<2> OSC3.3_OUT
http://laptop117.com
MEMORY CLOCK SPREAD SPECTRUM

8
U13
CLKIN

PD#
REFOUT/FSIN1

CLKOUT/FSIN0
5

4 R112 2
OSC_IN <2>
1 22_0402_5%~D OSC_SPREAD <2> L18
CLP1

GND
EMI_CLIP~D
1 1
CLP4

GND
EMI_CLIP~D
+3VRUN 7 2 1 2
SCLK VDD +3VRUN
CLP2 CLP5

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

22U_1206_6.3VAM~D
6 3 BLM21AF121SN1D_0805~D
D R113 SDATA GND D
1 1 1 GND 1 1 GND

C181

C182

C183
ICS91720BGLF-T_TSSOP8~D
6.8K_0402_5%~D EMI_CLIP~D EMI_CLIP~D

2
2 2 2 CLP3
<2> DAC2_DDC3CLK

GND 1
+3VRUN
EMI_CLIP~D

1
R114

6.8K_0402_5%~D
2

<2> DAC2_DDC3DAT

+3VRUN BIOS EEPROM

@ 0_0402_5%~D

@ 0_0402_5%~D
1

1
C185
THERMAL SENSOR C184

R115

R116
1 2
1 2 U14
2200P_0402_50V7K~D U15 SIN 5 2 SOUT
<2> SIN D Q SOUT <2>
2 1 0.1U_0402_10V6K~D

2
<2> D+ D+ VDD1 SCLK
<2> SCLK 6 C
3 6 R5 1 2 @ 0_0402_5%~D
<2> D- D- ALERT# SCS#
<2> SCS# 1 S
R117 1 2 0_0402_5%~D 8 4 R4 1 2 0_0402_5%~D
<8,9> PBAT_SMBCLK SCLK THERM# OTEMP <9>
7 HOLD
R118 1 2 0_0402_5%~D 7 5
C <8,9> PBAT_SMBDAT SDATA GND C
+3VRUN 3 W
ADM1032ARM_MSOP8~D 8 4
VCC VSS
M25P10-AVMN6T_SO8~D

CF2 CF3 FD1 FD2

OPTION STRAPS +3VRUN
1 1 1 1

@ SMD40M80 @ SMD40M80 @ FIDUCAL @ FIDUCAL

FD3 FD4
R119 1 2 10K_0402_5%~D GPIO1 GPIO0 AGP 1X CLOCK FEEDBACK PHASE ADJUST WITH RESPECT TO REFCLK 1 1
<2> GPIO0
HI HI REFCLK TWO TAPS EARLIER THAN FEEDBACK @ FIDUCAL @ FIDUCAL

CF4 CF5 FD5 FD6

<2> GPIO1
R120 1 2 10K_0402_5%~D 1 1 1 1 Memory Configuration Table
@ SMD40M80 @ SMD40M80 @ FIDUCAL @ FIDUCAL
GPIO7 ZV_LCDDATA21 ZV_LCDDATA23
R121 GPIO3 GPIO2 CLOCK PHASE ADJUSTMENT BETWEEN X1 AND X2 CLK MEM_ID3 MEM_ID2 MEM_ID1 Memory type
<2> GPIO2 1 2 @ 10K_0402_5%~D
LO LO 0 TAP DELAY (DEFAULT) R157 R156 R128
H1 H2 H3 H4
@ C276D146 @ C276D138 @ C276D138 @ C276D146
0 0 0 TBD
R122 1 2 @ 10K_0402_5%~D
<2> GPIO3

1
B
0 1 0 TBD B

R123 1 2 10K_0402_5%~D ROM_ID4 ROM_ID3 ROM_ID2 ROM_ID1 ROM ID CONFIG

0 0 1 Samsung E-die 64M
<2> ROM_ID1
LO LO LO NO ROM (DEFAULT) H5 H6 H7 H8
LO
HI LO LO @ C276D146 @ C276D138 @ C276D146 @ C276D138
HI SERIAL AT25F1024 ROM 0 1
* HI LO HI HI SERIAL ST ROM
1 Samsung E-die 128M
R124 1 2 10K_0402_5%~D
<2> ROM_ID2

1
1 0 0 Hynix 64M
1 1 0 Hynix 128M
R125 1 2 @ 10K_0402_5%~D
<2> ROM_ID3
1 0 1 TBD
64MB(SAM) 128MB 64MB(Hynix)
<2> ROM_ID4
R126 1 2 10K_0402_5%~D @ Depop Depop Depop 1 1 1 TBD
128_64Hyn@ Pop Depop Depop

R157 10K_0402_5%~D
128_64SAM@ Depop Depop Pop
<2> MEM_ID3 1 2
64SAM@ Depop Pop Pop
ZV_LCDDATA22(R127):
64@ Depop Pop Depop
1 : High engine clock
R156 1 2 10K_0402_5%~D 0 : Normal engine clock
<2> MEM_ID2

A R128 A
<2> MEM_ID1 1 2 @ 10K_0402_5%~D
MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0 MEMORY TYPE CONFIG
LO LO LO LO TBD (DEFAULT)
<2> MEM_ID0
R127 1 2 10K_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Spread Spectrum and BIOS EEPROM
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 11 of 12
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Title Date
Request http://laptop117.com Issue Description Solution Description Rev.
Owner
D
1 MOBILITY Remove U17,U18 D
02 06/23/2004 Dell U17,U18 are redundant X00
M11-P_A Add T2,T3
2 MOBILITY
02,04,08,11 06/23/2004 Dell Since no external TMDS, fix ZV bus at 3.3V Removed R612,Q18,Q19,R631,R633,R601,R606 X00
M11-P_A
3 1uF caps C109,C131 on the G_PWR_SRC Vin to
10 REGULATORS 06/23/2004 Dell C109,C131 change value to 0.1U_25V X00
the ISL6227 should be 25V parts
4 10 REGULATORS 06/23/2004 Dell L44 out of 2.8V Linear LDO REG74 is redundant Remove L44 X00

5 09 MODULE CONN 06/23/2004 Dell Add bleed resistor on G_PWR_SRC Added R688 X00

6 Add ability to select hystertic mode or fixed PWM mode on 2.5V and 1.8V Added R689,R690 and populated as 0 ohm
10 REGULATORS 06/23/2004 Dell X00
regulator. Default should be fixed PWM mode Added R691,R692 and no pop
7 08 FPD CONN 06/23/2004 Dell Remove switch on G_PWR_SRC to INV_PWR_SRC Remove Q1,Q2,R86,R87,C105 X00

8 08 FPD CONN 06/23/2004 Dell Remove U7 and U8 from BACKLITE_ON Remove U7,U8,R88,C103,C104 X00
C C
9 10 REGULATORS 06/25/2004 Dell Select 1.8V operation of MEM_VDD and VDD_MEM_IO Added B12,B13 X00

10 MOBILITY
04 06/25/2004 Dell R605 is redundant Removed R605 X00
M11-P_D,E
11 10 REGULATORS 06/25/2004 Dell Add a 2.2uF capacitor for decoupling U12 Added C583 and populated as 2.2U_16V_0805 X00

12 MOBILITY Added U20,Added C582 and populated as 0.1U_10V_0402,Added R693

02 06/23/2004 Dell Add a buffer on AGP_RESET to prevent potential back drive issue from M11 X00
M11-P_A and no pop
13 MOBILITY
02 07/01/2004 Dell Level shifter pull up to +5VRUN R130, R131 change connection from +3VRUN to +5VRUN X00
M11-P_A
14 09 MODULE CONN 07/01/2004 Dell Need more power for M11, LCD backlight Added J1 pin 177 for G_PWR_SRC X00

15 MOBILITY On Gilbert MB side, there is a level shifter already, so the level

02 07/02/2004 Dell R130, R131 change connection back to +3VRUN X00
M11-P_A shifter on VGA pull up back to +3.3VRUN
16 BACKLITE_ON signal have a glitch , change power sequence from
10 REGULATORS 08/23/2004 Dell Added R694 and no pop , added R695 and populated as 0_0402 X01
RUNPWROK to +3VRUN that eliminate the glitch
B
17 Added C584 and populated as 0.1U_10V_0402 , B
10 REGULATORS 08/23/2004 Dell EMI issues , There is a BB noise in the 180 to 210 MHz range X01
added C585 and populated as 0.1U_10V_0402
18 BACKLITE_ON signal have a glitch , add U21,R696,R697,C586 to Added U21,R696,C586 and populated ,
01,08,10 FPD CONN 09/21/2004 Dell A00
eliminate the glitch added R697 and no pop
19

20

21

22

23

24
A A
25

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Changed-List History
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-2501
Date: Tuesday, September 21, 2004 Sheet 12 of 12
5 4 3 2 1