Tcad Workshop Volume I PDF

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TCAD WORKSHOP USING

SILVACO TCAD TOOLS
Volume I
This workshop w ill introduce you to process and

device simulation using the Silvaco TCAD tools. It
is assumed that you are familiar with basic
concepts of Silicon device processing and the
basic operation of Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET) and Bipolar
Junction Transistor (BJT).
SILVACO International 0
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Chapter 1: Getting Started
1.1 Running ATHENA Under DeckBuild

1. To invoke ATHENA under DECKBUILD in interactive mode, enter the UNIX
command:
deckbuild –an&
2. After a short delay, the main DECKBUILD window will appear:
Figure 1-1 Main DECKBUILD Window
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The lower text window of this window will contain the ATHENA logo and version number, a
list of available modules, and a command prompt. ATHENA is now ready to run. To become
familiar with the mechanics of running ATHENA under DECKBUILD you can load and run
some of the ATHENA standard examples.
1.2 Loading and Running ATHENA Standard Examples
DECKBUILD makes it possible to load and run a number of example simulation input files.
To access the ATHENA examples:
a. Click on the Main Control menu follows by the Examples… menu item
Figure 1-2 Loading DECKBUILD Examples.
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b. The Deckbuild: Examples window will appear (Figure 1-3).
Figure 1-3 DECKBUILD Examples Window
Groups of DECKBUILD examples are listed in the Section menu and are grouped
according to the simulation topic that the example demonstrates. Individual example
input files are listed in the Sub-section menu.
c. Select one of the simulation topics (e.g. MOS Application Examples) listed by
double-clicking on this topic. A list of the MOS Application Examples will be listed
as shown in Figure 1-4.
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Figure 1-4 A List of MOS Application Examples
d. Next, select the first input files (i.e. mos1ex01.in) by double-clicking on the input file
name. A description of the selected input file will appear in the examples window as
shown in Figure 1-5.
Figure 1-5 Description of mos1ex1.in
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e. Press the Load example button to load the selected input file into the DECKBUILD
text window as shown in Figure 1-6. The input file, along with other files associated
with the input file will be copied into your current directory.
Figure 1-6 Selected input file being loaded into DECKBUILD Text Window
f. Once the input file is loaded into the DECKBUILD text window, you can run the
input file by pressing the run button on the DECKBUILD window.
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Chapter 2: Creating an NMOS Device Structure Using

ATHENA
2.1 Overview of the Procedure
In this chapter, user will learn the basic operations required for creating a typical MOSFET
input file. These operations include:
• Developing a good simulation grid

• Performing conformal deposition
• Performing geometric etches
• Performing oxidation, diffusion, annealing and ion implantation
• Structure manipulation
• Saving and loading structure information
These operations are relevant to all individual ATHENA process simulators.
2.2 Creating An Initial Structure

2.2.1 Defining Initial Rectangular Grid
a. Clear the current text window of DECKBUILD by clicking the File menu follows
by Empty Document as shown below.
Figure 2-1 Clearing Text Window
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b. To start ATHENA as the simulator, we need to start off with the go statement (refer
to the ATHENA User’s Manual) by typing the statement: go Athena in the text
window as shown below.
Figure 2-2 Starting with “go athena”
Next, we shall specify the initial rectangular grid. The correct specification of a
grid is critical in process simulation. The number of nodes in the grid has a direct
influence on simulation accuracy and time. A finer grid should exist in those areas
of the simulation structure where ion implantation will occur, where p-n junction
will be formed, or where optical illumination will change photoactive component
concentration.
c. To define the rectangular grid, select the Mesh Define... menu item. The Mesh
Define menu will appear as shown in Figure 2-3.
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Figure 2-3 Invoking ATHENA Mesh Define Menu
2.2.2 Creating Non Uniform Grid in a Rectangular 0.6 µm by 0.8 µm Simulation

Area
a. From the Mesh Define menu, the Direction Field is selected as X by default.
b. Click on the Location field and enter a value of 0.
c. Then, click on the Spacing field and enter a value of 0.1.
d. For the Comment field, type Non-Uniform Grid (0.6um x 0.8um) as shown in
Figure 2-4.
Figure 2-4 Defining Grid Parameters.
e. Click on the Insert button in the Mesh Define window and the line parameters
will appear in the scrolling list as shown below.
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Figure 2-5 Clicking on Insert Button
f. In the same way, set the location of a second X line to 0.2 with a spacing of 0.01
and a third X line to 0.6 with a spacing of 0.01.
g. These X Line statements will define a grid that is very fine in the region on the
right hand side i.e. from location x = 0.2µm to 0.6µm. This region will later be use
for the active region of the NMOS transistor.
h. Next, we shall proceed to create the grid in the Y direction. Select Y in the
Direction field.
i. Click on the Location field and enter a value of 0. Then, click on the Spacing
field and enter a value of 0.008.
j. Click on the Insert button in the Mesh Define window.
k. In the same way, set the location of a second Y line to 0.2 with a spacing of 0.01, a
third Y line to 0.5 with a spacing of 0.05 and a fourth line to 0.8 with a spacing of
0.15 as shown in Figure 2-6.
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Figure 2-6 Mesh Define for Y Direction
Notice that the finest grid is defined at the surface i.e. from location y = 0µm to y
= 0.2µm. This region will later be use to form the surface active region of the
NMOS transistor. Thus, it is essential to have finest grid in this region.
l. To preview the rectangular grid, from the Mesh Define menu, select the View...
button. The View Grid window will be displayed. (Notice that a total of 1786
points and 3404 triangles are generated.)
Figure 2-7 View Grid Window.
m. Finally, write mesh define information to the text window by pressing on the
WRITE button on the Mesh Define menu. A set of lines will appear as
shown below.
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Figure 2-8 Line Statements for Generating Non-Uniform Grid
2.3 Defining the Initial Substrate

The LINE statements specified by the Mesh Define menu set only the rectangular base for the
ATHENA simulation structure. The next step is the initialization of the substrate region. To
initialize the simulation structure:
a. Select Mesh Initialize... from the ATHENA Commands menu. The ATHENA Mesh
Initialize menu will popup as shown in Figure 2-9.
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Figure 2-9 ATHENA Mesh Initialize Menu.
b. By default, Silicon is selected as the Material with <100> Orientation.
c. Click on the Boron impurity box so that Boron is selected as the background doping.
d. For the Concentration field, select the desired concentration as 1.0 using the slider or
by typing it, and select an exponent of 14 from the Exp: field. This will give a
background concentration of 1.0 x 1014 atom/cm3. (It is also possible to set
background concentration using the By Resistivity specification in Ohm•cm.)
e. For the Dimensionality field, check the 2D box. This forces the simulation to be run
in a two-dimensional calculation.
f. For the Comment field, type “Initial Silicon Structure with <100> Orientation” as
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Figure 2-10 Defining the Initial Substrate using the Mesh Initialize Menu.
g. Press the WRITE button to write the mesh initialization information into
DECKBUILD text window. The following Comment and Initialize statements will
appear in the text window as shown in Figure 2-11.
Figure 2-11 INIT Statement Appears in Text Window.
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2.4 Run ATHENA and Plotting
Now, run ATHENA to obtain the initial structure. Press the run button on the
DECKBUILD Control. The following output will appear in the simulator subwindow:
Figure 2-12 Running DECKBUILD
The line struct outfile=.history01.str is automatically produced by DECKBUILD via the

History function. The History function allows moving backwards to any previous line in the
input file and restarts execution. It provides an invaluable service when debugging new files,
performing what if simulations, and in visualizing the device at different stages in the process
flow.
To visualize the initial structure:
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1. Highlight the “.history01.str” file. Next, click on the Tools menu button, select Plot
and then Plot Structure... as shown in Figure 2-13.
Figure 2-13 Plot History file structure.
2. After a short delay, TONYPLOT will appear as shown in Figure 2-14. It will have
only regional and material information. From TONYPLOT, click on the Plot menu
button, followed by Display ….
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Figure 2-14 Selecting Display Menu from TONYPLOT.
3. The Display (2D Mesh) menu will appear as shown in Figure 2-15. By default, the
Edges and Regions icons will be selected. Click on the Mesh icon
as well, follows by the Apply button. The initial triangular grid will appears as shown
in Figure 2-16.
Figure 2-15 Tonyplot: Display (2D Mesh) Menu.
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Figure 2-16 Initial Triangular Grid
So, the previous INIT statement creates a <100> silicon region of size 0.6µm x 0.8µm, which
is uniformly doped with boron concentration of 1 x 1014 atom/cm3. This simulation structure
is ready for any process step (e.g. implant, diffusion, Reactive Ion Etching, etc.).
2.5 Performing Gate Oxidation
Next, we will grow an gate oxide layer on the Silicon surface by performing dry oxidation at
o
950 C for 11 minutes in 3% HCL at 1 atmospheric pressure. To perform this gate oxidation
step, from the ATHENA Commands menu, select the items Process ⇒ Diffuse.... The
ATHENA Diffuse menu will appear as shown in Figure 2-17.
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Figure 2-17 ATHENA Diffuse Menu.
a. From the Diffuse Menu, change the Time (minutes) from 30 to 11 and the
Temperature (C) from 1000 to 950. Note: The Constant Temperature is selected by
default (see Figure 2-18).
b. From the Ambient field, click on the Dry O2 box.
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c. Check on the Gas pressure and the HCL fields. Change the HCL to 3%.
d. Add a comment “Gate Oxidation” in the Comment field and click on the WRITE
button .
Figure 2-18 Gate Oxidation Parameters defined using the Diffuse Menu.
e. The gate oxidation information will be written into DECKBUILD text window as
shown in Figure 2-19. From this figure, it can be seen that the Diffuse statement is
used to perform the gate oxidation.
Figure 2-19 Gate Oxidation Step using Diffuse Statement.
f. Continue the ATHENA simulation by clicking on the Cont button on the

DECKBUILD control. Once the gate oxidation step is completed, another history file
“.history02.str” will be saved as shown in Figure 2-20.
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Figure 2-20 Continue simulating the Gate Oxidation Step
g. Plot this structure again by highlighting “.history02.str” file and then select the menu
items Plot ⇒ Plot Structure... from the Tools menu of DECKBUILD.
Figure 2-21 Gate Oxide Structure.
The resulting gate oxide structure will appears in TONYPLOT as shown in Figure 2-
21. From the plot, it can be seen that an oxide layer was deposited onto the silicon
surface.
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2.6 Extracting Gate Oxide Thickness

Next, we would like to extract the gate oxide thickness that was grown during the oxidation
process step. This can be done using the Extract routines of DECKBUILD.
Extract forms a “function calculator” that allows you to combine and manipulate values or
entire curves quickly and easily. You can create your own, customized expressions, or choose
from a number of standard routines provided for the process and device simulators. You can
take one of the standard expressions and modify it as appropriate to suit your needs. Extract
also has variable substitution capability so that you can use the results of previous Extract
commands. To extract the thickness of gate oxide:
a. From the Commands menu, just click on the Extract…. as shown below and the
ATHENA Extract menu will appears as shown in Figure 2-22.
Figure 2-22 ATHENA Extract Menu
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b. By default, the Material thickness is selected in the Extract field.
c. For the Name field, type in “Gateoxide”.
d. For the Material field, click on the Material… and select SiO~2.
e. On the Extract location field, click on the X location and enter a value of 0.3 as
Figure 2-23 Parameters used for Extracting Gate Oxide Thickness.
f. Click on the WRITE button and the Extract statement will appear in the text
window as shown in Figure 2-24.
Figure 2-24 Gate Oxide Thickness Extract Statement.
In this Extract statement, all the parameters are self-explanatory except the
mat.occno=1 which specifies the layer occurrence number. This parameter is
optional in this case as there is only one silicon dioxide layer. However, in some cases
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where there are many stacked silicon dioxide layers, we have to specify the specific
silicon dioxide layer that we are interested in.
g. Continue the ATHENA simulation by clicking on the Cont button on the

DECKBUILD control. The runtime output of the Extract statement is as shown Figure
2-25.
Figure 2-25 Runtime Output of the Extract Statement.
From the runtime output, we can see that the extracted gate oxide thickness was
131.347 Angstroms. In the next section, we shall learn how to optimize the gate oxide
thickness using the Optimizer function in DECKBUILD.
2.7 Optimizing Gate Oxide Thickness
In this section, we will learn how to use the Optimizer function in DECKBUILD to optimize
the gate oxidation process parameters. Assuming that the measured gate oxide thickness is
100 Angstroms, and both the diffusion temperature and partial pressure in the Gate Oxidation
step needs to be tuned. To optimize this parameter, DECKBUILD Optimizer will be used as
follows:
a. Click on the Main Control menu follows by Optimizer… as shown below.
Figure 2-26 Invoking DECKBUILD Optimizer.
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This invokes the DECKBUILD Optimizer as shown in Figure 2-27. The first
optimizer displays a table of the control parameters in the Setup Mode. The default
parameters here are normally adequate, except that we can set the Maximum error (%)
so as to fine tune the gate oxide thickness to 100Å.
Change
maximum
error from
5 to 1.
Figure 2-27 Setup Mode of DECKBUILD Optimizer.
b. Therefore, select the value for Maximum Error on the Stop criteria column and
change the value from 5 to 1.
c. Next, we must define the parameter to optimize by using the Mode button to change
from Setup mode to Parameters mode as shown below.
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Figure 2-28 Changing to Parameters mode.
c. For this tutorial, the optimization parameters are the temperature and partial pressure
during the Gate Oxidation step. To define this to the Optimizer, go to DECKBUILD
window and highlight the Gate Oxidation step as shown below.
Figure 2-29 Highlighting Gate Oxidation Step.
d. Then, within the Optimizer, click on the Edit menu follows by Add. The Deckbuild:
Parameter define popup window will appear as shown in Figure 2-30, listing the
items that may be used as parameters.
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Figure 2-30 Defining the Parameter to be Optimized.
e. Check on the temp=<variable> and press=<variable> items. Then, click Apply. The
added optimization parameter will then be display as shown below.
Figure 2-31 Added Optimization Parameter.
f. Next, using the Mode button, change the mode from Parameters to Targets so as to
define the target of the optimization.
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Figure 2-31 Changing to Targets Mode.
g. The Optimizer uses the value of Extract statement in DECKBUILD to define the
Optimization target. Therefore, go to DECKBUILD text window and highlight the
Extract gate oxide thickness statement as shown below.
Figure 2-32 Highlighting Optimization Target.
h. Then, within the Optimizer, click on the Edit menu follows by Add. This adds the
target “Gateoxide” to the Optimizer target list as shown in Figure 2-33.
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Figure 2-33 Add target “Gateoxide” to the Optimizer Target List.
i. You must define the target value for this entry in the Target List. Enter the Target
value as 100Å.
Figure 2-34 Enter Target value as 100Å.
The Optimizer has now been configured to optimize the gate oxide thickness by
varying the temperature and partial pressure during the Gate Oxidation process step.
j. To monitor the optimization process, change from Targets mode to Graphics mode
as shown below.
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Figure 2-35 The Graphics mode in the Optimizer.
k. Finally, to perform optimization, click on the Optimize button. The simulation will
run again and will, after a little time, start to iterate the Gate Oxidation step. The
Optimizer will then converged at a temperature of 925.727 oC and a partial pressure of
0.982979 and the extracted oxide thickness is 100.209Å as shown in Figure 2-36.
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Figure 2-36 Optimization completed.
To complete this Optimization exercise, the optimized value for the temperature and
partial pressure should be copied back to the input deck.
l. To copy this value, go to the Parameters mode and click on the Edit menu follows
by Copy to Deck to update the optimized parameter in the input deck as shown in
Figure 2-37.
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Figure 2-37 Optimized parameters automatically update in the correct place.
The input deck will be automatically updated in the correct place.
2.8 Performing Ion Implantation

Ion implantation is the main method used to introduce doping impurities into semiconductor
device structures. Adequate simulation of the ion implantation process is very important
because modern technologies employ small CDs and shallow doping profiles, high doses,
tilted implants and other advanced methods.
In ATHENA, ion implementation is done using the IMPLANT statement which can be set
using the ATHENA Implant menu. In this tutorial, we will perform a threshold voltage
adjust implant using Boron with a dose of 9.5 x 1011 cm-2 at an energy of 10 keV, with the ion
beam tilted at 7o and rotated at 30o. To do so,
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a. From the Commands menu, select Process follows by Implant.... The ATHENA
Implant menu will appears as shown in Figure 2-38.
Figure 2-38 ATHENA Implant Menu.
b. Select “Boron” from the Impurity field.
c. Enter a value of 9.5 in the Dose field using the slider or by typing it and a value of 11
in the Exp: field for the exponent.
d. Enter 10 for the Energy field, 7 for the Tilt field and 30 for the Rotation field.
e. The Dual Pearson model is chosen by default.
f. Select Material Type as “Crystalline”.
g. Enter “Threshold Voltage Adjust implant” for the Comment field.
h. Click on the WRITE button and the implant statements will appear in the text
window as shown in Figure 2-39.
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Figure 2-39 Threshold Voltage Adjust Implant Statement.
All of the parameters in the IMPLANT statement are self-explanatory except

CRYSTAL. The CRYSTAL parameter indicates that for all analytical models, the
range statistics extracted for a single silicon crystal will be applied.
i. Press the Cont button on the DECKBUILD control and ATHENA will
continue the simulation as shown in Figure 2-40.
Figure 2-40 Simulation of the Threshold Voltage Adjust Implant Step.
In the next section, we shall proceed on to analyze the doping profile of the implanted
Boron.
2.9 Analyzing Boron Doping Profile in TONYPLOT

The doping profile of the implanted Boron may be viewed using the 2D Mesh menu or using
the Cutline tool of TONYPLOT. In the 2D Mesh menu, the contour plot of the Boron doping
profile may be visualize. On the other hand, performing a Cutline on the 2D structure create a
1D cross-section plot of the Boron doping profile.
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First, we shall illustrate the use of the 2D Mesh menu to obtain the contour plot of the Boron
doping profile.
a. Plot the history file i.e. “.history05.str” of the threshold voltage adjust implant step
by highlighting it and then from the Tools menu of DECKBUILD, select the menu
items Plot ⇒ Plot Structure....
b. From TONYPLOT, select the Plot menu follows by Display…. The Display (2D
Mesh) popup will appear.
c. Select the Contours icon to plot the contour of the structure.
d. Then, click on the Define menu and select Contours… as shown in Figure 2-41.
Figure 2-41 Invoking TONYPLOT: Contour menu.
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e. The TONYPLOT: Contours popup will appears. By default, Net doping is being
selected in the Quantity option of the popup. Change the Quantity from Net doping
to Boron.
f. Click on the Apply button follows by the Dismiss button when

finished.
g. The contour plot of the Boron doping profile will appears as shown in Figure 2-42.
Figure 2-42 Contour Plot of the Boron doping profile after Ion Implantation.
Next, we shall perform a cutline on the 2D structure to create a 1D cross section plot of the
Boron doping profile. To do so,
a. From TONYPLOT, select the Tools menu follows by Cutline…. The Cutline popup
appears as shown in Figure 2-43.
b. By default, the Vertical icon is selected. This will restrict the cutline to a vertical
direction.
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Figure 2-43 TONYPLOT Cutline Popup.
c. In the structure plot, left click and drag the mouse starting from the oxide layer to the
bottom of the structure. In this way, a 1-D cross section plot of the Boron doping
profile appears in another window as shown in Figure 2-44.
Figure 2-44 Performing a Vertical Cutline across the structure.
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2.10 Performing Conformal Deposition for Polysilicon Gate

Conformal deposition can be used to generate multilayered structures. Conformal deposition
is the simplest deposit model and can be used in all cases when the exact shape of the
deposited layer is not critical.
Knowing that the polysilicon layer thickness grown in the NMOS process is 2000 Angstroms,
it is possible to substitute this with conformal polysilicon deposition. To set the conformal
deposition step, from the ATHENA Commands menu, select the items Process ⇒ Deposit
⇒ Deposit.... The ATHENA Deposit menu will appear (see Figure 2-45).
a. From the Deposit Menu, the Conformal deposition is the selected by default.
b. Select Polysilicon from the Material menu, and set its thickness to 0.2.
c. In the Grid specification parameters, click on the “Total number of grid layers”
checkbox and set its value to 10. (It is always useful to set several grid layers in a
deposited layer. In this case, 10 grid layers are needed in order to simulate impurity
transport through the polysilicon layer.)
d. Add a comment “Conformal Polysilicon Deposition” in the Comment field and

click on the WRITE button .
Figure 2-45 ATHENA Deposit Menu.
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e. The following lines will appear in the text window:
# Conformal Polysilicon Deposition

deposit polysilicon thick=0.2 divisions=10
f. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control.
g. Plot this current structure again by selecting the menu items Plot ⇒ Plot Structure....
from the Tools menu of DECKBUILD. A three layers structure is created as shown in
Figure 2-46.
Figure 2-46 Conformal Deposition of Polysilicon Layer.
2.11 Simple Geometrical Etches

The next step in the process simulation is the polysilicon gate definition. In this tutorial, we
will use a polysilicon gate edge at x = 0.35 µm and set the center of the gate at x = 0.6 µm for
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the initial grid. Therefore, polysilicon should be etched to the left from x = 0.35 as shown in
Figure 2-48.
a. Go to the Commands menu of DECKBUILD and select the chain Process ⇒ Etch
⇒ Etch.... The ATHENA Etch menu (Figure 2-47) appears.
Figure 2-47 ATHENA Etch Menu.
b. From the Etch menu, click on “Left” for the Geometrical type field.
c. From the Material field, select Polysilicon.
d. Set the Etch location to 0.35.
e. Add the comment “Poly Definition” for the Comment field.
f. Click on the WRITE button and this will give the following statement:
# Poly Definition
etch polysilicon left p1.x=0.35
g. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control and plot the etched structure as shown in Figure 2-48.
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Figure 2-48 Etching Polysilicon to form the Gate.
2.12 Performing Polysilicon Oxidation

The next step is to perform polysilicon oxidation prior to doping of the polysilicon by ion
implantation. The oxidation recipe is wet oxidation for 3 minutes at 900oC at 1 Atmospheric
pressure.
Since the oxidation is on a patterned (non-planar) and undamaged polysilicon, the method
used will be the fermi and compress methods. The fermi method is used for undamaged
substrates with doping concentrations < 1x1020 cm-3 whereas the compress method is used to
model oxidation on non-planar structures and for 2-D oxidation.
To perform this oxidation step, the Diffuse menu is used by selecting the items Process ⇒
Diffuse... from the ATHENA Commands menu.
a. From the Diffuse Menu, change the Time from 11 to 3 and the Temperature from
950 to 900.
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b. From the Ambient field, click on the Wet O2 box.
c. Check on the Gas pressure checkbox and uncheck the HCL checkbox.
d. Click on the Models setting from the Display field. The models available will then be
displayed.
e. Check on both the Diffusion and Oxidation models and select the Fermi and
Compressible boxes.
f. Add a comment “Polysilicon Oxidation” in the Comment field and click on the
WRITE button .
Figure 2-49 Polysilicon Oxidation Parameters defined using the Diffuse Menu.
g. The following Diffuse statement will then be added into the input file:
# Polysilicon Oxidation
method fermi compress
diffus time=3 temp=900 weto2 press=1.00
h. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control and plot the structure as shown in Figure 2-50. Thus, it can be
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seen that the poly oxidation step has formed oxide layer on top of the polysilicon and
also on the substrate.
Figure 2-50 Oxide Formation After the Polysilicon Oxidation Step.
2.13 Polysilicon Doping

After the polysilicon oxidation step, the next step is to dope the polysilicon with phosphorus
so as to create a n+ polysilicon gate. Here, the dose of the phosphorus used was 3x1013 cm-2
with an implant energy of 20 KeV. To perform the polysilicon doping step, the ATHENA
Implant menu is used again.
a. From the Commands menu, select Process follows by Implant.... The ATHENA
Implant menu (see Figure 2-51) will appears.
b. From the Impurity field, change the implantation impurity from “Boron” to
“Phosphorus”.
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c. In the Dose field, enter a value of 3 using the slider or by typing it and a value of 13
in the Exp: field for the exponent.
d. Enter 20 for the Energy field, 7 for the Tilt field and 30 for the Rotation field.
e. The Dual Pearson model is chosen by default.
f. Select Material Type as “Crystalline”.
g. Enter “Polysilicon Doping” for the Comment field.
Figure 2-51 Defined Polysilicon Doping Parameters using the Implant Menu.
h. Click on the WRITE button and the implant statements will appear in the text
window as follows:
# Polysilicon Doping
implant phosphor dose=3e13 energy=20 crystal
i. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control and plot the Net Doping of the structure by selecting the
Contours icon on the Display (2D Mesh) menu follows by the Apply button
as shown below.
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Figure 2-52 Net Doping Contour Plot After Polysilicon Implantation Step.
j. To view the implanted phosphorus contour plot, from the Display (2D Mesh) menu,
click on the Define menu and select Contours… as shown in Figure 2-53.
Figure 2-53 Invoking TONYPLOT: Contour menu.
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k. The TONYPLOT: Contours popup will appears. By default, Net Doping is being
selected in the Quantity option of the popup. Change the Quantity from Net Doping
to Phosphorus.
Figure 2-54 Changing Quantity Field from Net Doping to Phosphorus.
l. Click on the Apply button follows by the Dismiss button when

finished.
m. The contour plot of the implanted phosphorus doping profile will appear as shown in
Figure 2-55.
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Figure 2-55 Contour Plot of Implanted Phosphorus Doping Profile.
2.14 Spacer Oxide Deposition

Prior to the source and drain implants, spacer oxide deposition has to be performed. Here a
spacer oxide will be deposited with thickness of 0.12 µm. This can be accomplished using the
ATHENA Deposit menu as follows:
a. From the ATHENA Commands menu, select the items Process ⇒ Deposit ⇒
Deposit.... The ATHENA Deposit menu (see Figure 2-56) will appear.
b. Select Oxide from the Material menu, and set its thickness to 0.12.
c. For the Grid specification parameters, set the “Total number of grid layers” to 10.
d. Add a comment “Spacer Oxide Deposition” in the Comment field and click on the
WRITE button .
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Figure 2-56 Defined Spacer Oxide Deposition Parameters.
e. The deposit statements will appear in the DECKBUILD text window as follows:
# Spacer Oxide Deposition

deposit oxide thick=0.12 divisions=10

DECKBUILD control and plot the structure with meshes as shown in Figure 2-57.
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Figure 2-57 Mesh of the Structure After Spacer Oxide Deposition.
2.15 Sidewall Spacer Oxide Formation
To form the sidewall oxide spacer, a dry etch step has to be performed. This is done using the
ATHENA Etch menu (see Figure 2-58) as follows:
a. From the Etch menu, click on “Dry thickness” for the Geometrical type field.
b. From the Material field, select Oxide.
c. Enter 0.12 for the Thickness field.
d. Add the comment “Spacer Oxide Etch” for the Comment field.
e. Click on the WRITE button and this will give the following statement:
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# Spacer Oxide Etch
etch oxide dry thick=0.12
f. Continue the ATHENA simulation and plot the etched structure as shown in Figure 2-
58.
Figure 2-58 Sidewall Spacer Oxide Formation after Dry Etching.
2.16 Source/Drain Implant and Annealing

To form the n+ source/drain of the NMOS transistor, an arsenic implantation will be
performed. In this workshop, the dose of arsenic used is 5 x 1015 cm-3 at an implantation
energy of 50 KeV. To perform this implantation step, the ATHENA Implant menu will be
used again. After invoking the Implant menu, perform the following:
a. Change the implantation impurity from “Phosphorus” to “Arsenic” for the Impurity
field.
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b. In the Dose field, enter a value of 5 and a value of 15 in the Exp: field.
c. Enter 50 for the Energy field, 7 for the Tilt field and 30 for the Rotation field.
d. Select Material Type as “Crystalline”.
e. Enter “Source/Drain Implant” for the Comment field. Below shows the parameters
used for the source/drain implant.
Figure 2-59 Source/Drain Implant Parameters using the Implant Menu.
f. Click on the WRITE button and the implant statements will appear in the text
window as follows:
# Source/Drain Implant
implant arsenic dose=5e15 energy=50 crystal
The source/drain implant is then followed by a short annealing process in nitrogen for 1
minutes at 900 oC and 1 atmospheric pressure. This annealing process can be carried using
the Diffuse menu (see Figure 2-60) as follows:
a. From the Diffuse Menu, set the Time to 1 and the Temperature to 900.
b. From the Ambient field, click on the Nitrogen box.
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c. Check on the Gas pressure checkbox and set the value to 1.
d. Click on the Models setting from the Display field. The models available will then be
displayed.
e. Check on the Diffusion model and select the Fermi box. Uncheck the Oxidation
model.
f. Add a comment “Source/Drain Annealing” in the Comment field and click on the
WRITE button .
Figure 2-60 Annealing Process Parameters
The following diffuse statement will appear in the text window:
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
g. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control and plot the doping of the structure as shown in Figure 2-61.
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Figure 2-61 Source/Drain Implant and Annealing Process.
Next, we would like to see the change in the Net Doping before and after the annealing
process. To do this,
a. From the TONYPLOT of the Source/Drain Annealed structure (Figure 2-61), click on
the File menu, follows by the Load Structure…
b. To load the previous history file generated during the “implant arsenic dose=5e15
energy=50 crystal” step (i.e. .history12.str), key in the “.history12.str” for the
Filename field.
c. Then, click on the Load menu follows by Overlay as shown in Figure 2-62.
d. The previous implanted structure i.e. “.history12.str” will then overlay onto the
annealed structure i.e. “.history13.str” as shown in Figure 2-63. Notice that the
subtitle of the plot indicates “Data from multiple files”
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Figure 2-62 Loading Previous Implant Step Structure File and overlaying it.
Figure 2-63 Overlaying Structures.
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e. After the two structure plots are overlay onto each other, perform a Cutline by
selecting the Tools menu in TONYPLOT follows by Cutline …
f. The Cutline menu will appear. Click on the keyboard icon and enter the
following values for X and Y as shown in Figure 2-64.
Figure 2-64 Using the Keyboard option of the Cutline menu.
g. Once done, hit the “Return” button on keyboard and TONYPLOT will prompt you for
confirmation as shown below. Click on the Confirm button
Figure 2-65 Confirm Cutline.
This result in the generation of a one-dimensional plot on the right hand side as shown
in Figure 2-66. It can be seen that the short annealing process has moves the dopants
away from the surface of the MOS structure.
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Figure 2-66 One-dimensional Net Doping Plot.
2.16 Metallization
ATHENA can attribute an electrode to any metal, silicide or polysilicon region. A special
case is the backside electrode which can be placed at the bottom of the structure without
having a metal region there. In this tutorial, the metallization of the half NMOS structure is
done by, first forming the contact window in the source/drain region and next, depositing and
patterning the Aluminum.
To form the contact window in the source/drain region, the oxide layer is etch to the left at x
= 0.2 µm. using the ATHENA Etch menu as follows:
c. From the Etch menu, click on “Left” for the Geometrical type field.
d. From the Material field, select Oxide.
c. Enter 0.2 for the Etch location field.
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e. Add the comment “Open Contact Window” for the Comment field.
# Open Contact Window

etch oxide left p1.x=0.2
67.
Figure 2-67 Defining Parameters to Open Contact Window.
Figure 2-67 Forming the Contact Window before Metallization.
Next, an aluminum layer of thickness 0.03 µm will be deposited on the half NMOS structure
using the ATHENA Deposit menu as follows:
a. Select Aluminum from the Material menu, and set its thickness to 0.03.
d. For the Grid specification parameters, set the “Total number of grid layers” to 2.
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d. Add a comment “Aluminum Deposition” in the Comment field and click on the
WRITE button .
e. The following deposit statements will appear in the DECKBUILD text window:
# Aluminum Deposition
deposit aluminum thick=0.03 divisions=2

DECKBUILD control and plot the structure as shown in Figure 2-68.
Figure 2-68 Aluminum Deposition on the Half NMOS structure.
Finally, the aluminum layer is etch to the right starting from x = 0.18 µm using the Etch
menu as follows:
f. From the Etch menu, click on Right for the Geometrical type field.
g. From the Material field, select Aluminum.
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c. Enter 0.18 for the Etch location field.
h. Add the comment “Etch Aluminum” for the Comment field.
# Etch Aluminum
etch aluminum right p1.x=0.18
69.
Figure 2-69 Etching Aluminum on the Half NMOS structure.
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2.17 Extracting Device Parameters

In this session, we will extract some of the device parameters of the half NMOS structure.
These include the junction depth, n++ source/drain sheet resistance, LDD sheet resistance
under oxide spacer and the long channel threshold voltage This can be done by using the
Extract menu on DECKBUILD.
2.17.1 Extracting Junction Depth

To extract the junction depth,
a. From the Commands menu, click on the Extract…. The ATHENA Extract menu will
appears.
b. For the Extract field, select the Junction depth.
c. Type in nxj for the Name field
d. For the Material field, click on the Material… and select Silicon.
e. On the Extract location field, click on the X location and enter a value of 0.2 as
Figure 2-70 Parameters used for Extracting Gate Oxide Thickness.
window as follows:
extract name="nxj" xj material="Silicon" mat.occno=1 x.val=0.2 junc.occno=1
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In this extract statement, name="nxj" is the n-type, source/drain junction depth; xj
indicates that junction depth is to be extracted; material="Silicon" is material
containing the junction. In this case, the material is Silicon; mat.occno=1 indicates to
extract the junction depth at the first occurrence of Silicon layer; x.val=0.2 is to
extract the source/drain junction depth at x = 0.2 µm; junc.occno=1 is to extract the
junction depth at first occurrence of the junction. In a more complex structure, there
may have more than one junction within the same material layer. For example, an n+
source/drain region within a p well on an n substrate would, on a line through the
source/drain region, have two junctions.
source drain
junction 1
p Well
junction 2 n substrate
For the MOSFET structure, there is only one junction. Therefore, the junction
occurrence number in this case is optional.
2.17.2 Extracting N++ Source/Drain Sheet Resistance

To extract the sheet resistance, invoke the ATHENA Extract menu again and perform the
following:
a. Change the Extract field from Junction depth to Sheet resistance.
b. Type in n++ sheet res for the Name field.
c. On the Extract location field, with the X location selected, enter a value of 0.05 as
d. Click on the WRITE button and the Extract statement will appear in the text
window as follows:
extract name="n++ sheet res" sheet.res material="Silicon" mat.occno=1

x.val=0.05 region.occno=1
In this statement, sheet.res indicates that sheet resistance is to be extracted; and

mat.occno=1 and region.occno=1 specify the material occurrence number and the
region occurrence number to be 1; and x.val=0.05 tell the extract routine where the
n++ region is. This is done by giving the location of a point within the region at x =
0.05 µm.
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Figure 2-71 Parameters used for Extracting N++ Source/Drain Sheet Resistance.
2.17.3 Extracting LDD Sheet Resistance

To extract the LDD sheet resistance under the oxide spacer, we simply move the point of
interest to under the spacer. Referring to the structure simulated as shown in Figure 2-69, the
value of 0.3 is reasonable. We will name the extracted resistance as `ldd sheet res'. Simply
invoke ATHENA Extract menu and perform the following:
a. Change the Name field to ldd sheet res.
b. Change the value of the Extract location field to 0.3, with the X location selected.
c. Click on the WRITE button and the Extract statement will appear in the text
window as follows:
extract name="ldd sheet res” sheet.res material="Silicon" mat.occno=1

x.val=0.3 region.occno=1
2.17.4 Extracting Long Channel Threshold Voltage
To extract the long channel threshold voltage of the NMOS at x = 0.5 µm:
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a. From the ATHENA Extract menu, change the Extract field from Sheet resistance to
QUICKMOS 1D Vt.
b. For the Name field, type in 1dvt.
c. For the Device type field, click on the NMOS.
d. Check on the Qss field, and enter a value of 1e10.
e. On the Extract location field, enter a value of 0.5 as shown in Figure 2-72.
Figure 2-72 Parameters used for Extracting Long Channel Threshold Voltage.
window as follows:
extract name="1dvt" 1dvt ntype qss=1e10 x.val=0.5
In this statement, 1dvt instructs the Extract routine to extracts the 1D threshold
voltage; ntype is the device type. In this case, we have a n-type transistor; x.val=0.5
is point that lies within the channel of the device; qss=1e10 is the trapped charge,
Qss, which is given as 1 x 1010 cm-2. By default, the gate bias setting is 0-5 V for a
0.25V step with the substrate at 0V and a default device temperature of 300 Kelvin.
Continue the ATHENA simulation and all the extracted values will appears in the
DECKBUIKLD output window as shown in Figure 2-73. These information are also written to
the file `results.final' in your current working directory.
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Figure 2-73 Extracted Values Appear in the DECKBUILD Output Window.
2.18 Reflecting the Half NMOS Structure

This tutorial has been building one half of a MOSFET-like structure. At some point in the
simulation, it will be necessary to obtain the full structure. This must be done prior to
exporting the structure to a device simulator or setting electrode names. To mirror the half
MOSFET at its right boundary:
a. From the Commands menu, select Structure follows by Mirror. The ATHENA
Mirror menu will appear.
b. Select Right for the Mirror field as shown in Figure 2-74.
Figure 2-74 ATHENA Mirror Menu
c. Press the Write button to write the following statement to the input file:
struct mirror right
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d. Continue the ATHENA simulation using the Cont button on the

DECKBUILD control and plot the resulting full NMOS structure as shown in Figure
2-75.
Figure 2-75 The Full NMOS Structure.
From this figure, it can be seen that the right half of the structure is a complete mirror copy of
the right part, including node coordinates, doping values, etc.
2.19 Specification of Electrodes
To enable biasing in the device simulator ATLAS, it is essential to label the electrodes for the
NMOS transistor. The electrodes of the structure can be defined using the ATHENA
Electrode menu. To invoke this menu,
a. Go to the Commands menu, select Structure follows by Electrode.... The

ATHENA Electrode menu will appears.
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b. From the Electrode Type field, select the Specified Position button.
c. For the Name field, type in source.
d. Click on the X Position and set the value to 0.1 as shown in Figure 2-76.
e. Press the WRITE button and the following statement will appear in the input file:
electrode name=source x=0.1
Figure 2-76 Specifying Source Electrode.
Similarly, specify the drain electrode at x=1.1µm using the ATHENA Electrode menu to
obtain the following statement:
electrode name=drain x=1.1
The polysilicon gate electrode specification has the same format. For this structure it can be
done the same way as for source or drain:
electrode name=gate x=0.6
In ATHENA, a backside electrode can be placed at the bottom of the structure without having
a metal region there. To specify a backside electrode, select Backside from the Electrode
Type of the ATHENA Electrode menu. Then, type in the name “backside”. The following
backside electrode statement will appear in the input file:
electrode name=backside backside
The syntax backside specifies that a flat (zero height) electrode will be placed on the bottom
of the simulation structure.
Continue running the input file. From the output window of DECKBUILD as shown in Figure
2-77, the following notes can be seen.
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Figure 2-77 Assign Electrode Name.
With the specification of the electrodes, the NMOS structure is completed. The last session
will describe on how to save this final structure file.
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2.20 Saving Structure File for Plotting or Initializing an ATHENA

Input file for Further Processing
Although, the DECKBUILD history function saves structure files after each process step.
However, in many cases it is necessary to save and initialize structures independently. There
are several reasons for this:
i. The stack for the history files is limited (25 by default)
ii. It is not usually desirable to keep dozens of history files on disc (each of which
occupy dozens or hundreds of Kbytes) after the DECKBUILD session ends
iii. Users often want to save the structure information generated after key process steps
(e.g. final structure).
To save or load a structure, use the ATHENA File I/O menu which is invoked by:
a. Selecting File I/O... from the Commands menu.
b. Press the Save button and specify a file name nmos.str.
Figure 2-79. ATHENA File I/O Menu.
c. Press the WRITE button and the following line will appears in the input file:
struct outfile=nmos.str
d. Continue running the input file and plot the nmos.str structure file. Select the
Electrodes icon to view the drain, gate, source and backside electrodes (refer
Figure 2-80).
TCAD WORKSHOP
Figure 2-80 Full NMOS Structure.

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TCAD WORKSHOP

TCAD WORKSHOP USING

This workshop w ill introduce you to process and

Chapter 1: Getting Started

1.1 Running ATHENA Under DeckBuild

2. After a short delay, the main DECKBUILD window will appear:

Figure 1-1 Main DECKBUILD Window

1.2 Loading and Running ATHENA Standard Examples

Figure 1-2 Loading DECKBUILD Examples.

Figure 1-3 DECKBUILD Examples Window

Figure 1-4 A List of MOS Application Examples

Figure 1-5 Description of mos1ex1.in

Chapter 2: Creating an NMOS Device Structure Using

2.1 Overview of the Procedure

• Developing a good simulation grid

These operations are relevant to all individual ATHENA process simulators.

2.2 Creating An Initial Structure

Figure 2-1 Clearing Text Window

Figure 2-2 Starting with “go athena”

Figure 2-3 Invoking ATHENA Mesh Define Menu

2.2.2 Creating Non Uniform Grid in a Rectangular 0.6 µm by 0.8 µm Simulation

b. Click on the Location field and enter a value of 0.

c. Then, click on the Spacing field and enter a value of 0.1.

Figure 2-4 Defining Grid Parameters.

Figure 2-5 Clicking on Insert Button

j. Click on the Insert button in the Mesh Define window.

Figure 2-6 Mesh Define for Y Direction

Figure 2-7 View Grid Window.

Figure 2-8 Line Statements for Generating Non-Uniform Grid

2.3 Defining the Initial Substrate

Figure 2-9 ATHENA Mesh Initialize Menu.

b. By default, Silicon is selected as the Material with <100> Orientation.

Figure 2-11 INIT Statement Appears in Text Window.

2.4 Run ATHENA and Plotting

Figure 2-12 Running DECKBUILD

The line struct outfile=.history01.str is automatically produced by DECKBUILD via the

To visualize the initial structure:

Figure 2-13 Plot History file structure.

Figure 2-14 Selecting Display Menu from TONYPLOT.

Figure 2-15 Tonyplot: Display (2D Mesh) Menu.

Figure 2-16 Initial Triangular Grid

2.5 Performing Gate Oxidation

Figure 2-17 ATHENA Diffuse Menu.

b. From the Ambient field, click on the Dry O2 box.

Figure 2-19 Gate Oxidation Step using Diffuse Statement.

f. Continue the ATHENA simulation by clicking on the Cont button on the

Figure 2-20 Continue simulating the Gate Oxidation Step

Figure 2-21 Gate Oxide Structure.

2.6 Extracting Gate Oxide Thickness

Figure 2-22 ATHENA Extract Menu

c. For the Name field, type in “Gateoxide”.

Figure 2-23 Parameters used for Extracting Gate Oxide Thickness.

Figure 2-24 Gate Oxide Thickness Extract Statement.

g. Continue the ATHENA simulation by clicking on the Cont button on the

Figure 2-25 Runtime Output of the Extract Statement.

2.7 Optimizing Gate Oxide Thickness

a. Click on the Main Control menu follows by Optimizer… as shown below.

Figure 2-26 Invoking DECKBUILD Optimizer.

Figure 2-27 Setup Mode of DECKBUILD Optimizer.

Figure 2-28 Changing to Parameters mode.

Figure 2-29 Highlighting Gate Oxidation Step.

Figure 2-30 Defining the Parameter to be Optimized.

Figure 2-31 Added Optimization Parameter.