BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE PILANI, HYDERABAD CAMPUS

First Semester 2019-2020

ECE/EEE/INSTR – F214 (Electronic Devices)
Quiz-2
Time: 45 Min Max Marks: 26 Date: 21-11-2019
ID. No: Name:

Instructions: - There are 9 questions. Answer all the questions and write the answers in the space provided. Every correct answer carries 3
marks (from Q1. to Q8.) and 2 mark for only Q.9, while every incorrect answer carries -1 mark. Rough work must be carried out on the
supplementary sheet provided separately. Both the question paper as well as the answer sheet must be submitted for evaluation. Overwriting or
ambiguity will not be considered for evaluation. Also no marks will be awarded if ID No. or Name is left blank.
Answers
1 2 3 4 5 6 7 8 9
D C C B A B A C D

1. At 300º F, an NMOS device has the following parameters, n+ polysi gate, oxide thickness = 400 Å, NA = 1015/cm3,
Qox = q×5×1010/cm2, semiconductor bandgap = 1.424 eV, VT = - 0.357 V, semiconductor permittivity = 11.70, and
oxide dielectric const = 3.90. What would be the body bias so that the VT will be zero (0 V).

(A) 2.32 V (B) 3.53 V (C) 4.83 V (D) 5.43 V

2. A PMOS has the following parameters, W = 15 µm, µp = 300 cm2/V-s, L = 1.50 µm, VT = - 0.80 V. If the transistor
is working in non-saturation region at VSD = 0.50 V, then the value of gm is (given Cox = 9.86×10-8 F/cm2)
(A) 28.60 ms (B) 286 µs (C) 0.148 ms (D) 0.286 ms

3. Consider n-channel silicon JFET with the following parameters:

NA = 3 × 1018 cm−3, ND = 8 × 1016 cm−3, and a = 0.50 µm.
Assume the drain and source terminal to be grounded, what is the required gate voltage such that the undepleted
channel thickness is 0.20 µm?
(A) - 6.46 V (B) -5.56 V (C) -4.66 V (D) - 0.89 V

4. A one-sided n+p silicon diode at T = 300 K with a cross-sectional area of 10-3 cm2 is operated under forward bias.
The doping levels are ND = 1018 cm−3 and NA = 1016 cm−3, and the minority carrier parameters are τpo = 10-8 s, τno = 10-
7
s, Dp = 10 cm2/s, Dn = 25 cm2/s. The max current through the diode is 0.518 mA. What will be the maximum
forward bias voltage (in volt) and the diffusion resistance (in Ω), respectively
(A) 0.297 and 100 (B) 0.594 and 50 (C) 0.899 and 75 (D) 1.20 and 25

5. In a p+n junction, reverse biased at 10 V, the junc. capacitance is 10 pF. If the doping of the n side is doubled and
the reverse bias is changed to 80 V, what is the capacitance (in pF)? (Consider only the magnitude, i.e., mod value)
(A) 5 (B) 7.20 (C) 9.50 (D) 11.7

6. Consider a Schottky junction formed between silver and n-type Si (ND = 1016 cm−3). ni for Si is 1010 cm−3 and band
gap is 1.10 eV. Take the work function of silver to be 4.60 eV. What is the built-in potential (in V) in this junction?
Take electron affinity for Si to be 4.05 eV.
(A) 0.15 (B) 0.35 (C) 0.55 (D) 0.65

7. Consider an NMOS device with source and body connected together. Assume that the electron mobility is
dependent of VGS and VDS. Given, gm = 0.50 µA/V for VDS = 50 mV and VGS = 2V; gd = 8 µA/V for VDS = 2 mV and
I D I D
VGS = 0 V. Where g m  and g d 
VGS VDS
The threshold voltage (in volts) of the transistor is
(A) 1.20 (B) 0.80 (C) 0.60 (D) - 0.80
8. In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The
permittivities of the semiconductor and the oxide layer are Ԑs and Ԑox respectively. Assuming Ԑs/ Ԑox = 3, the ratio of
the maximum capacitance of the minimum capacitance of this MOS capacitor is

(A) 2.33 (B) 3.33 (C) 4.33 (D) 5.33

9. An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ polysilicon gate and the threshold voltage
was found to be 1 V. Now if the gate is changed to P+ polysilicon, other things remaining the same, the new threshold
voltage should be
(A) - 0.80 V (B) 0.10 V (C) 1.10 V (D) 2.10 V

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 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE PILANI, HYDERABAD CAMPUS
First Semester 2019-2020
ECE/EEE/INSTR – F214 (Electronic Devices)
Quiz-2
Time: 45 Min Max Marks: 26 Date: 21-11-2019
ID. No: Name:

Instructions: - There are 9 questions. Answer all the questions and write the answers in the space provided. Every correct answer carries 3
marks (from Q1. to Q8.) and 2 mark for only Q.9, while every incorrect answer carries -1 mark. Rough work must be carried out on the
supplementary sheet provided separately. Both the question paper as well as the answer sheet must be submitted for evaluation. Overwriting or
ambiguity will not be considered for evaluation. Also no marks will be awarded if ID No. or Name is left blank.
Answers
1 2 3 4 5 6 7 8 9
C D B C B A A B D

1. A PMOS has the following parameters, W = 15 µm, µp = 300 cm2/V-s, L = 1.50 µm, VT = - 0.80 V. If the transistor
is working in non-saturation region at VSD = 0.50 V, then the value of gm is (given Cox = 9.86×10-8 F/cm2)
(A) 28.60 ms (B) 286 µs (C) 0.148 ms (D) 0.286 ms

2. At 300º F, an NMOS device has the following parameters, n+ polysi gate, oxide thickness = 400 Å, NA = 1015/cm3,
Qox = q×5×1010/cm2, semiconductor bandgap = 1.424 eV, VT = - 0.357 V, semiconductor permittivity = 11.70, and
oxide dielectric const = 3.90. What would be the body bias so that the VT will be zero (0 V).

(B) 2.32 V (B) 3.53 V (C) 4.83 V (D) 5.43 V

3. A one-sided n+p silicon diode at T = 300 K with a cross-sectional area of 10-3 cm2 is operated under forward bias.
The doping levels are ND = 1018 cm−3 and NA = 1016 cm−3, and the minority carrier parameters are τpo = 10-8 s, τno = 10-
7
s, Dp = 10 cm2/s, Dn = 25 cm2/s. The max current through the diode is 0.518 mA. What will be the maximum
forward bias voltage (in volt) and the diffusion resistance (in Ω), respectively
(A) 0.297 and 100 (B) 0.594 and 50 (C) 0.899 and 75 (D) 1.20 and 25

4. Consider n-channel silicon JFET with the following parameters:

NA = 3 × 1018 cm−3, ND = 8 × 1016 cm−3, and a = 0.50 µm.
Assume the drain and source terminal to be grounded, what is the required gate voltage such that the undepleted
channel thickness is 0.20 µm?
(A) - 6.46 V (B) -5.56 V (C) -4.66 V (D) - 0.89 V

5. Consider a Schottky junction formed between silver and n-type Si (ND = 1016 cm−3). ni for Si is 1010 cm−3 and band
gap is 1.10 eV. Take the work function of silver to be 4.60 eV. What is the built-in potential (in V) in this junction?
Take electron affinity for Si to be 4.05 eV.
(A) 0.15 (B) 0.35 (C) 0.55 (D) 0.65

6. In a p+n junction, reverse biased at 10 V, the junc. capacitance is 10 pF. If the doping of the n side is doubled and
the reverse bias is changed to 80 V, what is the capacitance (in pF)? (Consider only the magnitude, i.e., mod value)
(A) 5 (B) 7.20 (C) 9.50 (D) 11.7

7. Consider an NMOS device with source and body connected together. Assume that the electron mobility is
dependent of VGS and VDS. Given, gm = 0.50 µA/V for VDS = 50 mV and VGS = 2V; gd = 8 µA/V for VDS = 2 mV and
I D I D
VGS = 0 V. Where g m  and g d 
VGS VDS
The threshold voltage (in volts) of the transistor is
(A) 1.20 (B) 0.80 (C) 0.60 (D) - 0.80
8. In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The
permittivities of the semiconductor and the oxide layer are Ԑs and Ԑox respectively. Assuming Ԑs/ Ԑox = 3, the ratio of
the maximum capacitance of the minimum capacitance of this MOS capacitor is

(A) 5.33 (B) 4.33 (C) 3.33 (D) 2.33

9. An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ polysilicon gate and the threshold voltage
was found to be 1 V. Now if the gate is changed to P+ polysilicon, other things remaining the same, the new threshold
voltage should be
(A) - 0.80 V (B) 0.10 V (C) 1.10 V (D) 2.10 V

---------------------###-------------------------
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE PILANI, HYDERABAD CAMPUS
First Semester 2019-2020
ECE/EEE/INSTR – F214 (Electronic Devices)
Quiz-2
Time: 45 Min Max Marks: 26 Date: 21-11-2019
ID. No: Name:

Instructions: - There are 9 questions. Answer all the questions and write the answers in the space provided. Every correct answer carries 3
marks (from Q1. to Q8.) and 2 mark for only Q.9, while every incorrect answer carries -1 mark. Rough work must be carried out on the
supplementary sheet provided separately. Both the question paper as well as the answer sheet must be submitted for evaluation. Overwriting or
ambiguity will not be considered for evaluation. Also no marks will be awarded if ID No. or Name is left blank.
Answers
1 2 3 4 5 6 7 8 9
A C B B A B C C C

1. At 300º F, an NMOS device has the following parameters, n+ polysi gate, oxide thickness = 400 Å, NA = 1015/cm3,
Qox = q×5×1010/cm2, semiconductor bandgap = 1.424 eV, VT = - 0.357 V, semiconductor permittivity = 11.70, and
oxide dielectric const = 3.90. What would be the body bias so that the VT will be zero (0 V).

(A) 5.43 V (B) 4.83 V (C) 3.53 V (D) 2.63 V

2. A PMOS has the following parameters, W = 15 µm, µp = 300 cm2/V-s, L = 1.50 µm, VT = - 0.80 V. If the transistor
is working in non-saturation region at VSD = 0.50 V, then the value of gm is (given Cox = 9.86×10-8 F/cm2)
(A) 28.60 ms (B) 286 µs (C) 0.148 ms (D) 0.286 ms

3. A one-sided n+p silicon diode at T = 300 K with a cross-sectional area of 10-3 cm2 is operated under forward bias.
The doping levels are ND = 1018 cm−3 and NA = 1016 cm−3, and the minority carrier parameters are τpo = 10-8 s, τno = 10-
7
s, Dp = 10 cm2/s, Dn = 25 cm2/s. The max current through the diode is 0.518 mA. What will be the maximum
forward bias voltage (in volt) and the diffusion resistance (in Ω), respectively
(A) 0.297 and 100 (B) 0.594 and 50 (C) 0.899 and 75 (D) 1.20 and 25

4. Consider n-channel silicon JFET with the following parameters:

NA = 3 × 1018 cm−3, ND = 8 × 1016 cm−3, and a = 0.50 µm.
Assume the drain and source terminal to be grounded, what is the required gate voltage such that the undepleted
channel thickness is 0.20 µm?
(A) - 0.89 V (B) - 4.66 V (C) - 5.56 V (D) - 6.46 V

5. In a p+n junction, reverse biased at 10 V, the junc. capacitance is 10 pF. If the doping of the n side is doubled and
the reverse bias is changed to 80 V, what is the capacitance (in pF)? (Consider only the magnitude, i.e., mod value)
(A) 5 (B) 7.20 (C) 9.50 (D) 11.7

6. Consider a Schottky junction formed between silver and n-type Si (ND = 1016 cm−3). ni for Si is 1010 cm−3 and band
gap is 1.10 eV. Take the work function of silver to be 4.60 eV. What is the built-in potential (in V) in this junction?
Take electron affinity for Si to be 4.05 eV.
(A) 0.15 (B) 0.35 (C) 0.55 (D) 0.65

7. Consider an NMOS device with source and body connected together. Assume that the electron mobility is
dependent of VGS and VDS. Given, gm = 0.50 µA/V for VDS = 50 mV and VGS = 2V; gd = 8 µA/V for VDS = 2 mV and
I D I D
VGS = 0 V. Where g m  and g d 
VGS VDS
The threshold voltage (in volts) of the transistor is
(A) 0.60 (B) 0.80 (C) 1.20 (D) - 0.80
8. In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The
permittivities of the semiconductor and the oxide layer are Ԑs and Ԑox respectively. Assuming Ԑs/ Ԑox = 3, the ratio of
the maximum capacitance of the minimum capacitance of this MOS capacitor is

(B) 2.33 (B) 3.33 (C) 4.33 (D) 5.33

9. An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ polysilicon gate and the threshold voltage
was found to be 1 V. Now if the gate is changed to P+ polysilicon, other things remaining the same, the new threshold
voltage should be
(B) - 0.80 V (B) 1.10 V (C) 2.10 V (D) 0.10 V

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