2017 22nd IEEE European Test Symposium (ETS)
Exploiting STT-MRAM for Approximate Computing
Nour Sayed Fabian Oboril Azadeh Shirvanian
Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany
E-mail: {nour.sayed, fabian.oboril, azadeh.shirvanian, rajendra.bishnoi, mehdi.tahoori}@kit.edu
Abstract—Spin Transfer Torque Magnetic RAM (STT-
MRAM) is an emerging non-volatile memory technology and
a potential candidate to replace SRAM in processor caches.
However, STT-MRAM suffers from a high write latency and
high write energy consumption which have to be addressed for
energy-efficient on-chip caches. The non-volatility property of
STT-MRAM can be relaxed by reducing the thermal stability
factor to improve both the write latency and write energy of
STT-MRAM. However, this leads to increase in retention failure
and read disturb rates resulting in erroneous data stored in the
cache. This problem can naturally be mitigated in the scope of
approximate computing in which such errors can be tolerated at
the application level. In this paper, we show how STT-MRAM
technology can effectively be used for approximate computing
by tuning technology and application parameters to achieve an
acceptable level of correctness with significant gains. Results show
that using our proposed approximate computing framework, the
per-access write latency and energy can be improved up to 25%
and 70%, respectively.
I. I NTRODUCTION
Energy consumption has emerged to be a major design
constraint for modern integrated circuits, in particular in low-
power application domains such as the “Internet of Things”.
The static power, which is the dominating component in
the total energy consumption, is the leading roadblock in
these fields [1]. Therefore, the stringent energy targets cannot
be achievable using conventional SRAMs, because of the
high leakage. As pointed out by the International Technology
Roadmap for Semiconductors [2], one of the most promising
solutions to overcome this power challenge is the integration of
non-volatile memories, where the data can be retained without
any power supply.
Among the emerging non-volatile memory technologies,
Spin Transfer Torque Magnetic Random Access Memory (STT-
MRAM) is one of the most promising technologies for future
embedded memories. STT-MRAM is a novel and unique stor-
age technology based on a magnetic device (called Magnetic
Tunnel Junction or simply MTJ) that exploits not only the
charge of electrons but also their spin to store digital content.
As a result, STT-MRAM promises almost zero static power,
fast access latencies (almost as fast as SRAM) and high
integration density (as good as DRAM) [3, 4]. Thus, STT-
MRAM has the potential to replace SRAM in the memory
hierarchy of the computing system.
However, in order to employ STT-MRAM as a promising
low-power solution still several fundamental challenges have
to be resolved. In particular, it is of decisive importance to
reduce the write energy as well as the write latency of STT-
MRAM [1, 2]. In fact, the MTJ cells require rather high current
for a long duration to switch their magnetization. Additionally,
the stochastic switching nature of the MTJ cells necessitates a
longer timing margin, which further extends the total write
period. The overall write latency is significantly increased
due to their long write period as well as the write current
978-1-5090-5457-2/17/$31.00 ©2017 IEEE
Rajendra Bishnoi Mehdi B. Tahoori
continuously flows for the same duration resulting in a high
energy [5].
Combining fast writing speed and low write energy to-
gether is not yet trivial. Consequently, there are a variety of
different approaches at circuit- and architecture-level to im-
prove the characteristics of STT-MRAM [6–10]. An interesting
solution in that regard is to relax the non-volatility property of
STT-MRAM as this improves both writing speed and energy.
On the other hand, this increases the error rate due to retention
failures as well as read disturb [11].
In this paper, we show the potential of the STT-MRAM
technology in the scope of approximate computing which
naturally fits with the aforementioned constraints. In general,
approximate computing relaxes the bounds of accurate com-
puting for the applications which are inherently error resilient
and in return, it improves the efficiency of the system by other
means such as performance and energy improvements [12, 13].
Many applications, for instance in audio or image processing
domains, possess an intrinsic fault tolerance, and thus can
deal with noisy (i.e. erroneous) data. For example, when
the output of multimedia (images, videos, etc.) processing
algorithms is left to human perception strict exactness may
not be required and imprecise results may often be sufficient.
Hence, with approximate computing, an increasing error rate
can be tolerated to improve the write energy/latency of STT-
MRAM with minimal cost. Moreover, even the overall system
energy efficiency can further be improved due to shorter
execution times thanks to the improved cache access latencies.
Our simulation results show that using the proposed ap-
proximate computing framework, the per-access write energy
of STT-MRAM can be reduced by 70 %. Applying this to the
data-cache of a microprocessor improves the overall system
performance by 10 % and 25 % for 2 GHz and 1 GHz core
frequencies, respectively.
The remainder of this paper is organized as follows. In
Section II, the basics of STT-MRAM is presented and the idea
of approximate computing is introduced. Afterwards, in Sec-
tion III, the proposed framework using approximate computing
for STT-MRAM is explained, followed by a comprehensive
experimental study in Section IV. Finally, Section V concludes
the paper.
II. P RELIMINARIES
A. Basics of STT-MRAM
In STT-MRAM, data is stored in a Magnetic Tunnel
Junction (MTJ) cell, which consists of two independent ferro-
magnetic layers separated by a thin oxide layer. The magnetic
orientation of one layer, the free layer, can be freely rotated,
while the magnetization of the other layer, the reference layer,
is fixed. Thus, the magnetization of the free layer can be in
parallel or anti-parallel to the reference layer. As a result, the
electric resistance of the MTJ changes to high for anti-parallel
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Bit-Line Bit-Line
−12 −7
x 10 x 10
3 5 1 4
Energy Retention Failure

Write Latency [ns]

Retention Failure
Write Energy [J]
Latency Read Disturb

Read Disturb
Probability

Probability
Free Layer 2 4.5

Low Resistance High Resistance 0.5 2

MgO
Parallel Anti-Parallel 1 4

Reference Layer
0 3.5 0 0
20 30 40 50 60 20 30 40 50 60
Write-0 Write-1 Thermal Stability Factor (∆) Thermal Stability Factor (∆)
Word-Line Word-Line
IW > IC IW > IC (a) (b)
Fig. 2: Effects of thermal stability factor on (a) write energy
Source-Line Source-Line and latency, (b) failure rates (for setup see Sec. IV-A)
Fig. 1: Typical STT-MRAM bit-cell structure
C. Failure Rate Dependency on Thermal Stability Factor
and low for parallel. These two states are used to represent a
logic ’0’ and ’1’, respectively (see Fig. 1). With low ∆ value, the STT-MRAM access latency and
energy can be significantly reduced. However, it increases the
In order to read data in an STT-MRAM cell, a low current retention failure rates and possibility of read disturb, that are
flows through the MTJ to sense the resistance state of the cell. explained next.
Also, to write a data into an STT-MRAM cell, current flows
through the MTJ. However, the write current (Iw ) is much Retention Failure: The retention failures in STT-MRAM
higher (tens of µA) than the critical current (Ic ) (minimum happen due to the inherent thermal fluctuation of the MTJ cell,
current required to flow for a considerable amount of time to that can lead to switch its magnetic orientation. This can occur
switch magnetization at a certain write error rate). The final regardless of whether a memory access is performed or not.
magnetization can be controlled by the write current direction The retention failure probability (PRF ) for a given time period
(see Fig. 1). As a result of this high write current, the dynamic (t) can be computed according to [14] as:
write energy in STT-MRAM is very high [5]. This issue is t
further pronounced due to the stochastic nature of the writing PRF = 1 − exp[− ] (3)
τ · e∆
(switching) process as well as the high sensitivity to process
variation, which requires considerable timing margins [7]. where τ is a constant equal to 1 ns. According to this equation,
a relatively high ∆ can significantly improve the reliability.
B. Retention Time in STT-MRAM Read Disturb: Since both read and write currents share
In general, the retention time in non-volatile memories the same path in the STT-MRAM bit-cell, the read current
refers to the data retaining capability of their bit-cell regard- can accidentally switch the bit-cell content during the read
less of their powered-on or powered-off conditions. In STT- operation time (tr ). This phenomenon is known as read disturb.
MRAM, this retention time depends on the thermal stability Its probability (PRD ) is strongly dependent on ∆ according
factor (∆) value of the MTJ cell. The higher the ∆ value, the to [16]:
tr
longer the data can stay in the bit-cell. For a value of 60, it PRD = 1 − exp[− ] (4)
∆(1− IIr )
can retain the bit-cell content for 10 years [14]. The ∆ value τ ·e c

can be modeled as: In this equation, ∆ has an exponential influence on the

V · H k · Ms
∆=
2 · KB · T
where V is the volume of the free layer, Ms is the saturation
magnetization, KB is the Boltzmann constant, T is the tem-
perature in kelvin and Hk is the effective field anisotropy. As
shown in equation (1), the ∆ value is directly proportional to
the volume of the MTJ cell, which can be tuned by changing
MTJ size during fabrication. Another way is by adjusting
the Ms and Hk values at the material level during the stack
development.
An MTJ cell with high ∆ value requires high switching
latency and energy. This is due to the fact that the height of
thermal barrier is more for a high ∆ value, hence requires more
current for a longer duration to perform switching. Its relation
with Ic can be modeled using the following equation [15]:
4 · e · KB · T α 4 · π · Mef f
Ic = · · ∆ · (1 + ) (2)
h η 2 · Hk
where h is the Planks constant, α is the LLG damping constant,
η is STT-MRAM efficiency parameter and 4πMef f is the
effective demagnetization field. The impact of the ∆ value on
switching latency and energy for a single bit-cell is illustrated
in Fig. 2 (a). Since for cache applications a high retention time
is not required, this trade-off is usually exploited to deliver a
high-performance and low-energy STT-MRAM architecture.
probability of the read disturb. In other words, small reduction
(1)
in ∆ increases the read disturb probability significantly.
Write Error: The write errors in STT-MRAM are typically
occurring due to the stochastic switching nature of their bit-
cells. However, the usage of a smaller ∆ value can make the
switching of MTJ cell faster due to the reduction in Ic value,
hence, the required switching time (tw ) of MTJ reduces for
the same target Write Error Rate (WER), which is apparent
with following equation [17]:
−π 2 · (I − 1) · ∆ Iw
WERbit (tw ) = 1 − exp[ ], I= (5)
4(I · eC(I−1)tw − 1) Ic
Here C is a technology dependent parameter and I is the ratio
of the write current (Iw ) to the critical current (Ic ).
Fig. 2 shows the effects of relaxing the thermal stability
factor on the error rate along with the MTJ switching time.
It is clear that low ∆ indicates that the cell is more likely to
suffer from errors at read access or during the retention time.
Therefore, in this work, we deal with the retention failures and
read disturb rates to trade-off with the energy and performance
improvements due to reduction in ∆ value. On the other hand,
smaller ∆ value has a positive impact on the write access
unlike the case of the retention failure and read disturb. Hence,
we are quantifying this impact by improving the write latency
as well as energy for a fixed WER.
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D. Approximate Computing
The Approximate Computing concept has recently emerged
as a promising approach which relies on relaxing the bounds
of precise computing to improve the energy, and performance
efficiency by orders of magnitude. This is done by leveraging
the applications resilience to the errors and producing an
acceptable output quality within the tolerable ranges instead of
error-free output. Furthermore, many of the applications, which
are data intensive and hence on-chip memory-exhausting,
provide opportunities to exploit approximate computing very
efficiently due to the huge existing gap between the level of
accuracy required by the perceptual limitations of humans and
that provided by the system, such as image, audio and video
processing applications. Thus, for such applications, AC has
the potential to significantly optimize the behavior of the on-
chip memory in terms of performance and energy. In this work,
we employ this approximate computing scheme in memories
at architecture-level and perform the evaluation using image
processing applications.
E. Related Work
For the high-performance and energy-efficient STT-MRAM
implementation, the prior research efforts have explored sev-
eral techniques to achieve energy efficiency at various levels
of STT design. At device-level, the extreme write margin
can be addressed by reducing the thermal stability factor [4],
however, this method dramatically affects the retention time
of the memory and can increase the overall failure rate of
STT-MRAM. Several circuit-level techniques [9, 10, 18, 19]
have been proposed to detect the actual switching time of
an STT-MRAM bit cell and stop the unnecessary current
flow immediately after the write completion. Although such
techniques significantly reduce the write energy, the overall
write latency remains the same. At the architecture level, the
write margin is reduced significantly by exploiting incomplete
write operations [20, 21]. The unfinished bits later have to be
processed by robust Error Correction Codes (ECCs). However,
such coding schemes have relatively large decoding latencies
that can impair the memory read latency. All above efforts have
been focused on addressing the inefficient write operation in
STT while preserving the accuracy of read/write operations.
Regarding the approximate computing topic, the previous
work on the approximate memory, focuses on finding a trade-
off between errors in the content of the saved or read data
and the energy consumption. In the prior works of DRAM
memory [12, 13], the energy consumption is optimized by
relaxing the refresh rate which reduces the refresh power.
However, the retention failure increases as a cost of this
method. In [22], the energy reduction is achieved by reducing
the number of pulses used to write Phase Change Memories.
For STT-MRAM memory, the prior efforts are very limited.
In [23], the approximate computing is leveraged for STT-
MRAM design improvement in which the MTJ cell is accessed
with different levels of accuracy (i.e., different current levels)
based on the application requirements. Hence the approxima-
tion is adopted in order to reduce the dynamic energy of read
and write operations by reducing both sensing and switching
currents at the cost of higher read and write error rates.
The main limitation of this work is the effect of the process
variation which is totally ignored. Process variation in STT-
MRAM affects device parameters of both MTJ cell and CMOS
transistor which in turn impacts the main parameters of read
and write operations (i.e., the switching current, the thermal
stability factor and the output current of the transistor). Conse-
quently, with different and tiny read-write access current levels,
Device- value
level (Device parameter dependent on MTJ size)
Failure Switching Switching
rates latency energy
Architecture- Fault Cache latencies Cache energy
level
injection (in cycles) (per access)
Application- SNR analysis Performance Energy
level
analysis analysis
Fig. 3: Illustration of cross layer approach for approximate
computing in STT-MRAM.
process variation results in considerable variations in the output
accuracy at architecture-level. In our work, we explore a new
approximation for STT-MRAM design to achieve substantial
improvements in both energy consumption and performance
for negligible loss in the application quality by lowering the
thermal stability factor of MTJ cell based on the application
requirements. A preliminary version of our work was published
in [24] which provides some insight into the impact of our idea
on the performance, energy consumption and reliability of the
STT-MRAM design.
III. A PPROXIMATE COMPUTING IN STT-MRAM
This section presents our proposed approximate computing
methodology for STT-MRAM. First, the overview is explained,
followed by the detailed description of each abstraction com-
ponent of our proposed methodology to trade-off accuracy
versus performance and energy. In the end, we explain, how
some parts of data, which are critical and reliable, have to be
protected in our framework.
A. Overview
Since on-chip memories (e.g., L1 cache) often do not
require long data retention periods due to frequent accesses,
the thermal stability factor of bit-cells in those memories
can be reduced, which lowers the data retention time. As
a result, the write latency will be reduced, and also, the
amount of current required to switch the bit-cell content will
be smaller. Consequently, the overall write energy will become
significantly better. However, the drawback of this approach
is an exponential increase in the retention failure and read
disturb rates. Therefore, to analyze this trade-off, we have
developed a cross-layer framework (as demonstrated in Fig. 3),
in which we carried forward the impact of ∆ reduction to the
memory architecture and application-level. We have calculated
the impact of various ∆ values on failure rates as well as
write energy and latencies at the device level (similar to
Fig. 2). These values are projected at the architecture-level
for per access energy and delay as well as failure rates. For
this, we have performed a fault injection model at memory
architecture-level to accurately mimic the possibility of read
and retention failures. At system-level, the application output
is evaluated using the Signal to Noise Ratio (SNR) metric.
This way we can find the optimal value of ∆ for the best
trade-off between acceptable quality of the output (correctness)
as well as the performance and energy improvement. In the
context of approximate computing, we allowed erroneous
(i.e. inaccurate) data to be fetched by the processor. Hence,
leveraging approximate computing can improve the writing
energy and latency of STT-MRAM. Also, as the write latency
of STT-MRAM is reduced, the overall system energy efficiency
can be further improved due to shorter execution times.
Overall, in this work, we analyze the range of parameters
from both STT-MRAM technology, system architecture and
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TABLE I: The overall mean time to failure (MTTF) for various
∆ values (for setup see Sec. IV-A)
∆ MTTF [s] ∆ MTTF [s]
20 9.22X10−7 34 1.11
25 1.37X10−4 35 3.01
31 5.52X10−2 40 447.59
32 1.50X10−1 45 6.7X10+4
33 4.08X10−1 60 2.17X10+11
application requirements to achieve acceptable level of quality
while maximizing energy and performance gains. For that pur-
pose, we employ image processing applications, in particular
as a case study, we will deal with JPEG format. This is a lossy
compression method for digital images to store or transmit
data in an efficient form without losing the ability to re-
extract an acceptable version of the image. For this reason, the
JPEG format provides some inherent level of fault tolerance,
which means that it fits very well to the idea of approximate
computing.
B. Adaptation of Thermal Stability Factor
As discussed in Sec. II-C, the thermal stability factor has
a strong influence on the reliability of STT-MRAM cell at
both idle and access time because of the reduction in Ic .
Consequently, various critical optimizations for STT-MRAM
design can be performed, namely i) performance optimization
which is obtained due to the reduction of the required time
to switch the MTJ resistance state (i.e., write latency tw ),
ii) as the write access power of STT-MRAM depends on
Ic as: Pw = Ic 2 · RM T J , where the resistance state of
MTJ cell is fixed, a low Ic value leads to a reduction in
power of the STT-MRAM cell, and iii) the energy consumption
(Ew = Pw · tw ) can also be dramatically reduced because of
the small tw and Pw values, since they are the outcomes of
low ∆ value. Fig. 2 shows the effects of ∆ value reduction on
failure probabilities, write latency and write energy. According
to this figure, as the value of ∆ decreases, both the write
access latency and write energy decrease at the cost of higher
retention failure. In our framework, for the ∆ reduction from
60 to 20, the improvements of the write latency and energy per
access reach up to 25% and 70%, respectively. Whereas, the
retention failure probability increases significantly and become
non-acceptable for the ∆ value below 32 (see Fig. 2).
C. Fault Injection Approach
There are retention failures and read disturb failures as-
sociated with low ∆ values for the STT-MRAM memory.
Therefore, an accurate fault injection model has to be built
based on the combined failure rates, i.e., Failures In Time
(FIT). The combined FIT rate has to be converted into access-
based failure probability. The accesses in memory (e.g., L1
data cache) are performed by read and write requests. However,
we perform the fault injection model at only read access,
since it is more frequent compared to the write access. We
compute the Fault Injection Rate (FIR) per read access based
on FIT value of the adopted ∆ and the Read Rate (RR) as
follows: FIR=FIT/RR. Table I provides the combined FIT rate
corresponding to ∆ values from 20 to 60.
D. Tolerate Acceptable Error Rate Using Approximate Com-
puting
To define the accepted value of the lowered ∆ for cache
memories, we have to estimate the acceptance quality of the
extracted image by observing the influence of the ∆ value on
the error rate which will be translated into the read-access-
based injected failures. The metric is based on the computed
Signal to Noise Ratio (SNR) between the approximated image
(faulty image) and golden image (faulty-free image). In other
words, SNR can be served as a quality measure for the
approximated image, which is calculated based on the variance
of the signal (i.e., the golden image) (σS2 ) and the variance of
2
the noise (i.e., the faulty image) (σN ) as Equation. (6), and is
expressed in decibel (dB). q
2 σS
SN R = 20 log10 q (6)
2
σN
The value of SNR impacts directly the performance and energy
consumption of the proposed scheme. However, the minimum
acceptable SNR value depends mainly on the application
requirements. For instance in image processing applications,
the minimum required SNR value of the faulty image SNR
Threshold (SNRth ), is set at the level where the human brain
and eyes can differentiate between a faulty image and a golden
one. This means, if the SNR value of the output is less than
SNRth , it is considered as an unacceptable output quality. See
Fig. 4 where SNR for an acceptable JPEG image quality has
to be more than SNRth = 50. However, for more performance
and energy improvements, other smaller SNR values can be
considered at the cost of less but still acceptable output quality.
The corresponding pseudo-codes for generation of golden and
faulty images are presented in Algorithm 1 and Algorithm 2.
E. Protection of Critical Data
A major challenge of using an approximate storage is
that most applications which are highly amenable to the
approximate computing paradigm, have a mixture of control
data, so-called the critical data, which cannot tolerate any
errors and the data that may be approximated or unreliable.
Since the workloads in our case study are image processing
applications (JPEG), which uses a lossy compression technique
to produce a similar coloured image with reduced size and
an acceptable quality, any imprecision on region of code that
stores the meta-data (the header of the image) totally corrupts
the output image. This means header data is controlling the
image data and should not be approximated. Whereas, the
compressed image data (i.e., quantization) has tolerance to
imprecision and any errors in it may only lead to some degree
Algorithm 1 Golden image generation
Input Error-free output constraint {∆max }
Output Error-free image
1: Set the corresponding STT-MRAM based data cache configurations
2: Execute the simulation without fault injection mode
3:return Error-free image
Algorithm 2 Faulty image generation
Input Approximate computing constraints {∆min , ∆max , SN Rth }
and the maximum number of experiments (N)
Output Acceptable and non-acceptable percentage of image quality
1: For ∆ from ∆min to ∆max do
2: Set the corresponding STT-MRAM based data cache configurations
3: Calculate the fault injection rate per read access (FIR)
4: For n from 1 to N do
5: Execute the simulation with fault injection mode
7: Calculate SN R
8: if SN R > SN Rth then
9: Increase the acceptable quality percentage
10: else
11: Increase the non-acceptable quality percentage
12: end if
13: end for
14: end for
15: return Acceptable and non-acceptable percentage of image quality
 !

(a) Golden image (b) Acceptable image qualtiy (c) Non-acceptable image quality (d) Non-acceptable image quality
∆ = 32 & SN R = 50 ∆ = 26 & SN R = 23 ∆ = 27 & SN R = 19
Fig. 4: Images of various ∆ and SNR values for STT-MRAM data cache for “jpegtran” workload

100 100
Image Quality in %

Image Quality in %
75 75

50 50

25 djpeg 25 djpeg
jpegtran jpegtran
cpeg cpeg
0 0
10 20 30 40 50 60 70 10 20 30 40 50 60 70
Thermal Stability Factor ∆ Thermal Stability Factor ∆

(a) 1 GHz clock frequency (b) 2 GHz clock frequency

Fig. 5: Acceptable image quality for various ∆ values

of quality loss in the output image. Therefore, the stored data with a fault injection framework in order to support the
has to be classified into reliable and unreliable data, which retention time of each particular value of ∆ adopted for an
are header and quantization, respectively. There are various STT-MRAM based data cache. Whereas, the instruction cache
solutions to protect the critical part of the data. has to be faulty-free. This is why, we assumed ∆ = 60 for
the instruction cache to guarantee high retention time. This
The critical data size is very small compared to that of assumption is reasonable, as the number of write accesses
the non-critical data. To make critical data error resilient, one to the instruction cache is considerably lower. Therefore, the
way is to design a heterogeneous memory array for the data performance and energy overheads of adopting higher ∆ for
cache which has high and low ∆ values. In this design, the such this cache would be negligible. Table II summarize the
critical data has to be stored to the cells of high ∆ to guarantee set-up for our experiments. The evaluations are performed by
the error free operation. However, this requires changes to the running 3 applications of image processing from MiBench
fabrication parameters of the two arrays as well as complex applications 100 times in order to make our fault injection
cache controller to allocate data to different array. A less model non-deterministic. Each output for each experiment has
complicated way to protect the critical data is either to use a different level of quality loss according to the error rate of
multiple copies of the content of this data, such as dual or triple the used ∆. We use SNR as the metric to evaluate the quality
modular redundancy, or to use Error Correction Code (ECC), of the applications output.
which protects the data by adding check bits. Since the size
of critical data is significantly smaller than approximate-able B. SNR Evaluations
data, the overhead due to extra bit-cells of either the repeated
bits of dual or triple modular redundancy or the check bits of The SNR measurements reveal the degree at which an
ECC approach is minimal. application could produce satisfactory and reasonable output
due to the use of the relaxed thermal stability factor of STT-
MRAM in data cache for approximate applications. This is
IV. SIMULATION RESULTS to determine the achievable limits of the performance and
In this section, we present the experimental analysis to energy improvements for STT-MRAM technology. Our anal-
show the benefits of using STT-MRAM in approximate com- ysis depends on extracting 100 different values of SNR for
puting by using image processing applications (JPEG) as case each ∆ value up to 70 for the all three images applications.
study. Fig. 4 shows acceptable and non-acceptable faulty image
quality along with the original one. After observing the images
A. Simulation Setup along with the related SNR, we can define the values of
For the bit-cell characterization, we extracted the read SN Rth which are 50, 50 and 60 for djpg, jpegtran and
and write latencies for STT-MRAM by SPICE simulation cjpeg, respectively. This means that the faulty image can be
using TSMC 65nm general purpose transistor models and the considered as acceptable, if its SNR value is greater than
perpendicular STT-MRAM model presented in [25]. For the SN Rth (as explained in Algorithm 2).
bit-cell in L1 data cache, we used ∆ from 10 up to 70 in
order to determine the minimum value that can be adopted TABLE II: Simulation setup in gem5
for optimal results. For our evaluations, we employed the gem5 confiquration ISA x86
gem5 simulator [26]. gem5 is a full-system, cycle-accurate Processor Single-core, 0.5/1/2 GHz, Out-of-order, 4-issue
performance simulator that supports all levels of the memory L1 data-cache
64 KB, 2-way set associative, 64B line size
STT-MRAM, different write latencies and ∆ values
hierarchy with various configurations such as capacity, asso- 32 KB, 2-way set associative, 64B line size
ciativity, latency, and block size. We extended the simulator L1 instruction-cache
STT-MRAM, ∆ = 60
MiBench Applications [27] djpeg, cjpeg, jpegtran

!
120
Relative Changes in %
100
Approximate
80
Computing Region
60
40
20
0 0
10 20 30 32 34 40
Thermal Stability Factor ∆
(a) 1 GHz clock frequency
Fig. 6: Relation between image quality, performance (runtime) and write energy for an STT-MRAM based data cache
According to the SNR measurements, we count the ac-
ceptable images from the entire 100 faulty images related to
each ∆ value for all the image applications (see Fig. 5). This
image shows that for ∆ ≤ 25, the percentage of acceptable
quality is zero, for the three image applications. Whereas, for
∆ ≥ 40, all the images are acceptable. For ∆ values equal
to 32, 33 and 34, our results show that the percentage of the
acceptable quality is more than 95%. Therefore, values of ∆
can be considered for approximate computing, in which the
output with quality loss less than 5%. Please note that in our
framework, the retention failure rate is dominating over the
read disturb rate for the SNR measurements (see Fig. 2 (b)).
For the applications with faster read requirements, higher read
currents are necessary, and consequently, the read disturb rate
will be higher. In such cases, the SN Rth evaluation criteria can
be changed, and accordingly, the percentage of the acceptable
quality can be altered.
C. Performance and Energy Analysis of Optimal ∆ for Ap-
proximate Computing
The performance influence of the lower ∆ value for STT-
MRAM data cache is closely associated with the processor
frequency. On one hand, for a given frequency, the write
latency is reduced by 0.5 ns when ∆ is lowered to 32, as
illustrated in Fig. 2 (a). On the other hand, the performance
gain further increases by a low clock frequency of the pro-
cessor as well. For instance it reaches to 25% and 10% at
clock frequency 1 GHz and 2 GHz, respectively (see Fig. 6).
Furthermore, according to our experiments, 66% of the total
energy of STT-MRAM for the L1 cache is consumed for write
operations in data cache. Therefore, any improvement in the
energy consumption of STT-MRAM cell in the data cache
leads to the overall system energy efficiency. Results show that
we are able to improve the energy consumption per access up
to 70% with a ∆ value 32.
Based on the performance and energy improvements of
the low ∆ value along with the output quality, we can define
the optimal ∆ value for a particular system setup. Fig. 6
illustrates this trilateral relationship (i.e., energy, performance,
quality). According to this figure, the optimal configuration
for approximate computing applications, can be obtained by
relaxing the thermal stability factor from the usually applied
60 down to 32, where the overall system energy reduction
reaches to around 46% and the performance gains are 25%
and 10%, at clock frequency 1 GHz and 2 GHz, respectively.
V. CONCLUSIONS
We have developed a cross-layer framework, from tech-
nology parameters to architecture and application levels to
evaluate the applicability of STT-MRAM technology for ap-
proximate computing. We have also provided a methodology
!
120
Relative Changes in %
100
Approximate
80 Computing Region
60
40
Write Energy Write Energy
Performance 20 Performance
Image Quality Image Quality
50 60 70 10 20 30 32 34 40 50 60 70
Thermal Stability Factor ∆
(b) 2 GHz clock frequency
to determine the optimal thermal stability factor in order to
find the right balance between acceptable accuracy as well
as energy and performance gains. Our results show that the
energy reduction of 46% along with performance gain of up
to 25% can be achieved at system level with a reasonable
output quality.
VI. ACKNOWLEDGEMENT
This work was partly supported by the European Commis-
sion under the Horizon-2020 Program as part of the GREAT
project (http://www.great-research.eu/) and by ANR/DFG as
part of the MASTA project.
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