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Figure 11.89
50. Due to manufacturing error, a parasitic resistor Rp has appeared in the cascode
stage of Fig.
11.90. Assuming # = 0 and using Miller’s theorem, determine the poles of the
circuit.
M 1
VDD
Vin
RS
Vout
M 2 Vb
R
RP
D
Figure 11.90
51. In analogy with the circuit of Fig. 11.89, a student constructs the stage
depicted in Fig. 11.91
but mistakenly uses an NMOS device for M3. Assuming # = 0 and using Miller’s
theorem,
M 1
VDD
Vin
Vout
M 2
M R
R G
3
Vb1
Vb2 D
Figure 11.91
compute the poles of the circuit.
Design Problems
52. Using the results obtained in Problems 9 and 10, design the two-stage amplifier
of Fig. 11.63
for a total voltage gain of 20 and a 3-db bandwidth of 1 GHz. Assume each stage
carries a
bias current of 1 mA, CL = 50 fF, and #nCox = 100 #A=V2
.
53. We wish to design the CE stage of Fig. 11.92 for an input pole at 500 MHz and
an output pole
R
V
Q1
C
CC
Vout
Vin
RB
Figure 11.9
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007
at 13:42 599 (1)
Sec. 11.10 Chapter Summary 599
at 2 GHz. Assuming IC = 1 mA, C# = 20 fF, C# = 5 fF, CCS = 10 fF, and VA = 1, and
using Miller’s theorem, determine the values of RB and RC such that the (low-
frequency)
voltage gain is maximized. You may need to use iteration.
54. Repeat Problem 53 with the additional assumption that the circuit must drive a
load capacitance of 20 fF.
55. We wish to design the common-base stage of Fig. 11.93 for a 3-dB bandwidth of
10 GHz