Theory

Demorgan's Theorem permits conversion of logic from OR/NOR to AND/NAND and

AND/NAND to OR/NOR.
Demorgan's first Theorem : (X'+Y')'= X.Y.
Here X'=A, Y'=B so equation becomes (A+B)' =A'.B' …….equation I
It says that the complement of a sum equals the product of complements. Figure 4a is
the graphical meaning of Demorgans First Theorem. The L.H.S. of equation I
represent NOR Gate & R.H.S of equation I represents bubbled AND Gate.

NOR Gate Bubbled AND Gate

Figure 1
Equation I shows that the NOR Gate is equivalent to bubbled AND Gate.
Demorgan's Second Theorem : (X'Y')'= X+Y
Here X'=A, Y’=B so equation becomes (AB)'=A'+B' ………..equation II
It says complement of a product equals the sum of the complements L.H.S of equation
II represents output of a NAND Gate. RHS of equation II represents output of
bubbled OR Gate. Thus equation II represents NAND Gate is equivalent to a bubbled
OR Gate.

NAND Gate Bubbled NOR Gate

Figure 2
DB04
Experiment

Objective :
Analysis of Demorgan's Theorem with Boolean logic equations
Equipment Needed :
1. Digital board DB04
2. DC Power Supply +5V from external source or Scientech 2611 Digital Lab.
3. Digital multi meter or Digital Lab Scientech 2611
Logic diagram & Truth Table :

Figure 3

X Y X+Y (X’.Y’)’
0 0
.
0 1
1 0
1 1

X + Y = (X’.Y’)’
Table 1
 Figure 4
X Y (X'+Y')' X.Y
0 0
0 1
1 0
1 1

X.Y = (X’+Y’)’
Table 2
Procedure :
1. Connect +5V and ground to their indicated position on DB04 experiment board
from external DC Power Supply or from DC power block of Digital Lab
Scientech 2611.
2. Connect inputs 00, 01, 10, 11 to inputs X and Y of logic circuit shown in figure
Las per truth table given.
3. Switch “On” the power supply.
4. Observe outputs (X'.Y')', (X+Y) on multi meter or on logic probe or LED
display of Digital Lab Scientech 2611 and prove truth table.
5. Repeat above steps for logic circuit of figure 2.
 Data Sheet

General Description :
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A. The 74HC/HCT04 provides six inverting buffers.
Pin out diagram :
(Pin 14 = Vcc = + 5V)

Function Table : Figure 5

General Description :
The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT00 provide the 2-input NAND function.

Function Table : Figure 6

General Description :
This device contains four independent Gates each of which performs the logic NOR
function.

Figure 7

Function Table :

Note : Pull up resistance of 1K is required in open collector ICs to get output.