Mindanao State University- Iligan Institute of Technology

EE 270: VLSI Technology

Prof. Jefferson Hora

Lab 1: Inverter
Rovil S. Berido
MSEE-Microelectronics I
ID #: 2014-7835

Submission Date: October 30, 2015

 Schematic and Symbol

pMOS: W/L=12u/1u, m=8

nMOS: W/L=2u/1u, m=8

Layout

Testbench
 Pre-Simulation Vs Post-Simulation Output Waveform
DRC, LVS and LPE Results
Conclusion: Input rise and fall time is set to 1ns. Input pulse width and period is set
to 1us and 2us respectivel. Pre-simulation output of the inverter shows rise time and
fall time being equal to 987ps and 836ps respectively. Post-simulation output of the
inverter shows rise time and fall time being equal to 961ps and 842ps. Rise time has
improved by 2.6% after layout . There is a slight change in fall time (0.7%).