8086-based Frequency meter

Rahaf awadallah 20170070

Osama kuri 20160078

Dr. Essam qaralleh

Abstract
We designed an 8086-based frequency meter. The frequency of any
square wave signal is measured and displayed on the 7-segment display
with LEDs as an indication whether the measured frequency is in HZ or
KHZ or MHZ. From the keypad you can choose whether to display the
signal’s frequency on the 7-segment or display a number from the
keypad.

PROCESS
The target signal (signal to be measured) is AND-ED with a reference
signal of 0.5 HZ; this is done because frequency is measured by the
number of pulses in one second. The output is then given to the clock
of the first counter. The process of computing the frequency is done by
the microprocessor. After programing the interfaces and initializing the
counter, the microprocessor waits 1 second and reads the count. In the
program, the count read by the microprocessor is subtracted from the
initial count to get the frequency. Finally, the microprocessors send the
value to the 8255 to be displayed later. However, if the user inserts a
certain button on the keypad the frequency of the signal won’t be
displayed but instead the 7-segment will illustrate the value entered by
the user.
1.KEYPAD FUNCTIONALITY

1 2 3

4 5 6

7 8 9

Display 0 Display
Keypa frequency
d
This 4×3 keypad matrix has 12-
pushbottons connected to row and column lines. Rows are connected
to PC0-PC3 and columns PC4-PC6.
The microprocessor sets the rows as output and columns as input, then
it picks a row and sets it high.  After that, it checks the column lines one
at a time.  If the column connection stays low, the button on the row
has not been pressed.  If it goes high, the microcontroller knows which
row (the one it set high), and which column, (the one that was detected
high when checked).
 U37
10 11
A0 D0
9 12
A1 D1
8 13
A2 D2
7 15
A3 D3
6 16
A4 D4
5 17
A5 D5
2.MEMORY 4
3
A6
A7
D6
D7
18
19
25
A8
24
A9
We used the UV EPROM memory (27512). This 21
23
A10
A11
2
memory is 512bit(64k×8). 26
A12
A13
27
A14
1
It has 64k rows and 8 columns, A15
20
CE
22
OE/VPP
which means it needs 16-address lines 27512

and reads/writes one byte at a time.

Speed of this memory (address access time ) is 150 ns ,

2.1 READY signal generation

Normally this is the circuit used to generate the ready signal.
Number of wait states = number of flipflops -1

Note that this was only for clarification purposes.

In our design, the memory used speed is fine and doesn’t require a
delay circuit.
2.2MEMORY DECODING CIRCUIT

AD[0..15]
U14 AD[0..7] AD[0..15]
U33 AD[0..7]
AD0 10 11 AD0 10 11 U34 U35
AD1 A0 D0 AD1 A0 D0 AD[0..15] AD0 AD[0..7] AD[0..15] AD0 AD[0..7]
9 A1 D1 12 9 A1 D1 12 10 A0 D0 11 10 A0 D0 11
AD2 8 13 AD2 8 13 AD1 9 12 AD1 9 12
A2 D2 A2 D2 A1 D1 A1 D1
AD3 7 15 AD3 7 15 AD2 8 13 AD2 8 13
A3 D3 A3 D3 A2 D2 A2 D2
AD4 6 16 AD4 6 16 AD3 7 15 AD3 7 15
A4 D4 A4 D4 A3 D3 A3 D3
AD5 5 17 AD5 5 17 AD4 6 16 AD4 6 16
A5 D5 A5 D5 A4 D4 A4 D4
AD6 4 18 AD6 4 18 AD5 5 17 AD5 5 17
A6 D6 A6 D6 A5 D5 A5 D5
AD7 3 19 AD7 3 19 AD6 4 18 AD6 4 18
A7 D7 A7 D7 A6 D6 A6 D6
AD8 25 AD8 25 AD7 3 19 AD7 3 19
A8 A8 A7 D7 A7 D7
AD9 24 AD9 24 AD8 25 AD8 25
A9 A9 A8 A8
AD10 21 AD10 21 AD9 24 AD9 24
A10 A10 A9 A9
AD11 23 AD11 23 AD10 21 AD10 21
AD12 A11 AD12 A11 AD11 A10 AD11 A10
2 2 23 23
A12 A12 A11 A11
AD13 26 AD13 26 AD12 2 AD12 2
AD14 A13 AD14 A13 AD13 A12 AD13 A12
27 27 26 26
A14 A14 A13 A13
AD15 1 AD15 1 AD14 27 AD14 27
A15 A15 A14 A14
AD15 1 AD15 1
A15 A15
CE13 20 CE14 20
OE CE OE CE CE15 C16
22 OE/VPP 22 OE/VPP 20 CE 20 CE
OE 22 OE 22
OE/VPP OE/VPP
27C512 27C512
27C512 27C512

U10 U11
AD[0..15] AD0 AD[0..7] AD[0..15] AD0 AD[0..7] U12 U13
10 A0 D0 11 10 A0 D0 11 AD[0..15] AD[0..7] AD[0..15] AD[0..7]
AD1 9 12 AD1 9 12 AD0 10 11 AD0 10 11
A1 D1 A1 D1 A0 D0 A0 D0
AD2 8 13 AD2 8 13 AD1 9 12 AD1 9 12
A2 D2 A2 D2 A1 D1 A1 D1
AD3 7 15 AD3 7 15 AD2 8 13 AD2 8 13
A3 D3 A3 D3 A2 D2 A2 D2
AD4 6 16 AD4 6 16 AD3 7 15 AD3 7 15
A4 D4 A4 D4 A3 D3 A3 D3
AD5 5 17 AD5 5 17 AD4 6 16 AD4 6 16
A5 D5 A5 D5 A4 D4 A4 D4
AD6 4 18 AD6 4 18 AD5 5 17 AD5 5 17
AD7 A6 D6 AD7 A6 D6 AD6 A5 D5 AD6 A5 D5
3 19 3 19 4 18 4 18
A7 D7 A7 D7 A6 D6 A6 D6
AD8 25 AD8 25 AD7 3 19 AD7 3 19
A8 A8 A7 D7 A7 D7
AD9 24 AD9 24 AD8 25 AD8 25
A9 A9 A8 A8
AD10 21 AD10 21 AD9 24 AD9 24
AD11 A10 AD11 A10 AD10 A9 AD10 A9
23 23 21 21
A11 A11 A10 A10
AD12 2 AD12 2 AD11 23 AD11 23
A12 A12 A11 A11
AD13 26 AD13 26 AD12 2 AD12 2
A13 A13 A12 A12
AD14 27 AD14 27 AD13 26 AD13 26
AD15 A14 AD15 A14 AD14 A13 AD14 A13
1 A15 1 A15 27 A14 27 A14
AD15 1 AD15 1
CE9 CE10 A15 A15
20 CE 20 CE
OE 22 OE 22 CE11 20 CE12 20
OE/VPP OE/VPP CE CE
OE 22 OE 22
OE/VPP OE/VPP
27C512 27C512
27C512 27C512

AD[0..15]
U6 AD[0..7] AD[0..15]
U7 AD[0..7]
AD0 10 11 AD0 10 11 U8 U9
A0 D0 A0 D0 AD[0..15] AD[0..7] AD[0..15] AD[0..7]
AD1 9 12 AD1 9 12 AD0 10 11 AD0 10 11
A1 D1 A1 D1 A0 D0 A0 D0
AD2 8 13 AD2 8 13 AD1 9 12 AD1 9 12
A2 D2 A2 D2 A1 D1 A1 D1
AD3 7 15 AD3 7 15 AD2 8 13 AD2 8 13
A3 D3 A3 D3 A2 D2 A2 D2
AD4 6 16 AD4 6 16 AD3 7 15 AD3 7 15
A4 D4 A4 D4 A3 D3 A3 D3
AD5 5 17 AD5 5 17 AD4 6 16 AD4 6 16
A5 D5 A5 D5 A4 D4 A4 D4
AD6 4 18 AD6 4 18 AD5 5 17 AD5 5 17
A6 D6 A6 D6 A5 D5 A5 D5
AD7 3 19 AD7 3 19 AD6 4 18 AD6 4 18
AD8 A7 D7 AD8 A7 D7 AD7 A6 D6 AD7 A6 D6
25 25 3 19 3 19
A8 A8 A7 D7 A7 D7
AD9 24 AD9 24 AD8 25 AD8 25
AD10 A9 AD10 A9 AD9 A8 AD9 A8
21 21 24 24
A10 A10 A9 A9
AD11 23 AD11 23 AD10 21 AD10 21
A11 A11 A10 A10
AD12 2 AD12 2 AD11 23 AD11 23
A12 A12 A11 A11
AD13 26 AD13 26 AD12 2 AD12 2
AD14 A13 AD14 A13 AD13 A12 AD13 A12
27 A14 27 A14 26 A13 26 A13
AD15 1 AD15 1 AD14 27 AD14 27
A15 A15 A14 A14
AD15 1 AD15 1
A15 A15
CE5 20 CE6 20
OE CE OE CE CE7 CE8
22 OE/VPP 22 OE/VPP 20 CE 20 CE
OE 22 OE 22
OE/VPP OE/VPP
27C512 27C512
U5 27C512 27C512
2 11 CE1
A Q0 U1 U2
3 9 CE2
B Q1 AD[0..15] AD[0..7] AD[0..15] AD[0..7] U3 U4
21 10 CE3 AD0 10 11 AD0 10 11
C Q2 A0 D0 A0 D0 AD[0..15] AD[0..7] AD[0..15] AD[0..7]
U36 22 8 CE4 AD1 9 12 AD1 9 12 AD0 10 11 AD0 10 11
D Q3 A1 D1 A1 D1 A0 D0 A0 D0
7 CE5 AD2 8 13 AD2 8 13 AD1 9 12 AD1 9 12
Q4 A2 D2 A2 D2 A1 D1 A1 D1
OE 23 6 CE6 AD3 7 15 AD3 7 15 AD2 8 13 AD2 8 13
INH Q5 A3 D3 A3 D3 A2 D2 A2 D2
LE 1 5 CE7 AD4 6 16 AD4 6 16 AD3 7 15 AD3 7 15
STB Q6 A4 D4 A4 D4 A3 D3 A3 D3
4 CE8 AD5 5 17 AD5 5 17 AD4 6 16 AD4 6 16
NOT Q7 A5 D5 A5 D5 A4 D4 A4 D4
18 CE9 AD6 4 18 AD6 4 18 AD5 5 17 AD5 5 17
Q8 CE10 AD7 A6 D6 AD7 A6 D6 AD6 A5 D5 AD6 A5 D5
17 3 19 3 19 4 18 4 18
Q9 A7 D7 A7 D7 A6 D6 A6 D6
20 CE11 AD8 25 AD8 25 AD7 3 19 AD7 3 19
Q10 A8 A8 A7 D7 A7 D7
19 CE12 AD9 24 AD9 24 AD8 25 AD8 25
Q11 A9 A9 A8 A8
14 CE13 AD10 21 AD10 21 AD9 24 AD9 24
Q12 A10 A10 A9 A9
13 CE14 AD11 23 AD11 23 AD10 21 AD10 21
Q13 A11 A11 A10 A10
16 CE15 AD12 2 AD12 2 AD11 23 AD11 23
Q14 A12 A12 A11 A11
15 CE16 AD13 26 AD13 26 AD12 2 AD12 2
Q15 A13 A13 A12 A12
AD14 27 AD14 27 AD13 26 AD13 26
A14 A14 A13 A13
4515 AD15 1 AD15 1 AD14 27 AD14 27
A15 A15 A14 A14
AD15 1 AD15 1
CE1 CE2 20 A15 A15
20 CE CE
OE 22 OE 22 CE3 20 CE4 20
OE/VPP OE/VPP CE CE
OE 22 OE 22
OE/VPP OE/VPP
27C512 27C512
27C512 27C512

The address bus of the microprocessor A [0-15] are connected to the

address pins of the memory A0-A15.
Output pins of the memory D0-D7 are connected to AD[0-7] of the
microprocessor.

The left address bits

A[16-19] are used for the decoding
AD[16..19]
AD16 2
U19
11 CE1
circuit to select a memory chip.
A Q0
AD17 3 CE2
AD1921
A19 22
B
C
Q1
Q2
9
10 CE3
CE4
According to those bits we can specify
U32 D Q3
8
CE5
7
OE
LE
23
1
INH
STB
Q4
Q5
Q6
6
5
CE6
CE7
the start and end address ranges of
4 CE8
Q7
NOT
Q8
Q9
18
17
CE9
CE10 each memory chip.
20 CE11
Q10
19 CE12
Q11
14 CE13
Q12
13 CE14
Q13
16 CE15
Q14
15 CE16
Q15
4515
3. The 8255

8255 ports D0-D7 are connected to AD0-AD7 of the microprocessor.

The RD and WR of 8255 should be connected to pins 32 and 29,
respectively, of the microprocessor (RD, WR/LOCK).
In our design, ports A&B are programmed as outputs. We can access
any port of the 8255 by A0&A1 which are controlled by AD14 & AD15 of
the microprocessor.
Output portA is programmed to display on the 7-segment.
Output portB5-7 are programmed to set LEDs high.
Output portC0-3 are rows of the keypad for always generating running
ones.
Input portC4-6 are columns of the keypad.
 3.1 The 8255 DECODING CIRCUIT
U2
AD8-AD15 of the microprocessor
AD8
AD9
AD10
3
4
7
D0
D1
Q0
Q1
2
5
6
are assigned to enable the 8255-
D2 Q2
LE AD11 8 9
AD12
AD13
13
14
D3
D4
D5
Q3
Q4
Q5
12
15
chip select.
AD14 17 16
D6 Q6
AD15 18 19
D7 Q7
OE 1
OE
The chip select pin is active low
A0
11
AD[0..15] LE
74HC373 and in order to enable the chip
A1

the values of AD8-AD15 should

12
11

be all ones.
6
5

4
3
2
1
U4
74S30
8

4. COUNTER (8253)
In this design, counter0 was programmed to operate in mode 0.
This means that, after initializing counter0, it will start counting as long
as the gate is high, the output will remain low until it finishes the count
then it will go high. Counting is done by decrementing the initial count
at every pulse of the clock.
Counter0 zero is a 16-bit register and it was configured to read/write
least significant byte first then most significant byte. In other words, we
had to do IN/OUT instruction twice.
The clock ounter0 operates on is the output of the target signal AND-ed
with a reference signal of 0.5 HZ. So, what we will get actually are the
number of pulses in one sec, which is the definition of frequency.
Once the initializing is done by exactly one second, microprocessor
reads the new count after
Notice that pins D0-D7 are connected to AD0-AD7 of the
microprocessor and RD &WR pins are connected to RD&WR/LOCK of
the 8086.
A0&A1 are used to choose access between the three counters and they
are controlled AD8&AD9 of the microprocessor.

4.1 COUNTER DECODING CIRCUIT

 Addresses AD8-AD15 are used to enable the chip select of the counter.
In order to select the counter chip, since the chip select is active low ,
the values of AD8-AD15 should equal
to 01111110. AD[0..15]

AD[0..15]

U8
AD8 3 2 U9
D0 Q0
AD9 4 5
D1 Q1
AD10 7 6
D2 Q2
AD11 8 9
D3 Q3
AD12 13 12
D4 Q4 NOT U6
AD13
14 15 1
D5 Q5
AD14 17 16 2
D6 Q6
AD1518 19 3
D7 Q7
4
OE 1 8
OE
LE 11 5
LE
U10 6
74HC373 11
12
74S30
NOT

5. Flow Chart algorithm of measuring the signal

frequency.
1.
2.
schematic