Unit-3 of Section B PDF

Unit 3 of Section B
Elements of Physical Design

Chapter - 5
unit- 3 of section B - Elements of Physical

Wednesday, October 03, 2018 1
Design
Examples of Polygons in Physical Design- all features
are Manhattan geometries where all turns(CORNERS)
are multiples of 90˚

Design
Basic concepts
• In physical design the schematic diagrams are carefully
translated into sets of geometric patterns to define the
on-chip physical structures.
• Every patterned layer is a group of geometrical objects
referred to as polygons.
• The different layers when stacked into 3-D structures
constitute an equivalent electrical circuit.
• For a given set of processing parameters, the electrical
characteristics of the circuit depends on the aspect
ratios of the transistors.
• In a VLSI chip the switching speed of some logic gates
will be critical, especially those in long complex logic
paths.
Design
Examples of Polygons in Physical Design- all features are
Manhattan geometries where all turns are multiples of 90˚

Design
Layout Editor
• The process of Physical Design is performed by a computer tool
called Layout Editor.
• Layout Editor is a graphics program that allows the designer to
specify the shape, dimensions, and placement of every polygon
on every layer of the chip.
• Complexity issues are attacked by first designing simple gates and
storing their descriptive files in a library sub-directory or folder.
• The gates constitute cells in the library.
• Library cells are used as building blocks by creating copies of the
basic cells to construct a larger more complex circuit.
• This process is called instancing of the cells, while a copy of a cell
is called an instance.
• The layout must be an accurate representation of the design, and
the designer’s goal is obtaining fast circuit in the minimum
amount of area.

Design
CAD Toolset
• After the layout is completed several secondary programs have to
be run that use the database information to find if our layout is
valid.
– Layout Versus Schematic (LVS) is a program that checks the layout
against the schematic diagram. LVS is important to verify that the layout
corresponds to the intended circuit.
– Design Rule Checker (DRC) is a program that uses the layout database
and checks every occurrence of the design rule list on the layout. The
spacing and widths of every material layer is checked to ensure that
they are not violated. Passing a DRC ensures that the design can be
fabricated within the limitations of the manufacturing process.
– Electrical Rule Checker (ERC) highlights all connecting paths, using which
all electrical continuity can be checked.
• Place and Route routines help the layout designer to find all viable
wiring routes between two specified points. This is useful when
trying to connect two complex units together.

Design
Layout of Basic Structures
• The sequence of operations used to define chip regions in a
double metal single poly, n-well CMOS process are
– 0. start with p-type substrate
– 1. n-well
– 2. Active
– 3. poly
– 4. p-select
– 5. n-select
– 6. Active contact
– 7. Poly contact
– 8. Metal-1
– 9. Via
– 10. Metal-2
– 11. Overglass
Design
Actual values for W and S depend on the
layer

Design
Minimum width of a feature and the minimum spacing
between adjacent features depends on the layer.
• The actual fabricated structure on the chip will

have different dimensions.
• Layout sizes are therefore called drawn
dimensions, while the resulting sizes after
fabrication are effective or final values.
• The drawn and effective dimensions are
particularly important in FET designing.
• Detailed and up-to-date sets of design rules for
various processes can be obtained from the
MOSIS web site at www.mosis.org.
Design
An n-well is required at every location where a pFET is
to be made

Design
Design rule for n-wells
• The two design rules for n-well are
– Wnm = minimum width of n-well mask feature
– Snw-nw = minimum edge-to-edge spacing of adjacent
n-wells
• it is often possible to merge adjacent n-wells
together into one
• Also every n-well must have a connection to the
power supply VDD, when used for p-FETs. Why is this
connection of n-well to VDD required ?????

Design
Active areas: All FETs are built on active areas of the substrate . After
the isolation oxide (FOX) is grown, an active area is flat and provides
access to the top of the silicon wafer. The field oxide exists everywhere
else on the wafer. Active regions are defined by closed polygons on the
Active mask. The set of polygons required to define the patterns in Fig
(a) is shown in Fig(b)

Design
Design rules for Active areas
• The two rules that go with Active areas are
– Wa = minimum width of an Active feature
– Sa-a = minimum edge-to edge spacing of Active mask
polygons
• These are minimum values that must be observed in
maximum density designs.
• The field oxide regions can be derived from the Active
mask by the expression
– FOX = NOT (Active) – logical NOT of active mask
– FOX + Active = Surface
• Which means, if the region is not Active then it is FOX by default

Design
Doped Silicon Regions
• The n+ and p+ regions are created by ion implanting
the appropriate impurity ions into the substrate in
areas described by the n-select mask.
• The n-select mask defines regions that cover Active
areas
• Both n-select and Active areas are needed to create
the n+ region Intersection of both masks
n  n  select    Active 
Design
The n+ regions are created whenever the Active and
n-select masks intersect
Substrate

Design
Design rules for Active Regions
• Wa = minimum width of an Active area
• Sa-n = minimum Active-to-n-select spacing
– Spacing distances are measured from edge-to-edge
– Design rules are invariant with respect to direction, and
so the same values also apply to the horizontal
dimensions
• The p-type implant is defined by the p-select mask
and the expression for a p+ region is
p  ( p  select )  ( Active )  (n  well )
Design
Sa-p = minimum Active to p-select spacing
sp-nw = minimum p-select to n-well spacing

Design
MOSFETS
• Self-aligned MOSFET structure exists every time a
poly gate line completely crosses an n+ or p+ region
• Actually a poly line is deposited before the ion
implant, and this acts to block dopants on the poly
mask layer.
• Design rules for poly features are
– Wp = minimum poly width = drawn channel length of a
FET = L
– Sp-p = minimum poly-to poly spacing

Design
nFET  (n  select )  ( Active )  ( poly )

Design
n  (n  select )  ( Active )  ( NOT[ poly ])
dpo = minimum
extension of poly (Green)
beyond Active
(Red)

Design
pFET  ( p  select )  ( Active )  ( poly )  (n  well )
dpo

Design
Design
p  ( p  select )  ( Active )  (n  well )  ( NOT[ poly ])
• Drawn and Effective values in MOSFETs: The critical

dimensions of a MOSFET are its channel length – L and
channel width – W
• Channel length L = Wp is established by the width of the poly
gate line
• Channel width W is set by the appropriate edge measurement
of the Active transistor area, since that region defines where
the drain/source ion implant penetrates into the silicon
• Design rules dictate the mask layout and represents the
drawn dimensions
• The final values measured on the chip will be slightly different
Design
Drawn and Effective Dimensions

Design
• The distance between two n+ regions is the channel length L = Wp =
width of poly line, in the final structure this distance is smaller
because of lateral doping during implant annealing.
• When the wafer is heated, the dopants on opposite sides move
toward one another.
• The overlap effect is symmetrical and results in the overlap distance
Lo on both sides.
• In the electrical analysis this final value referred to as the effective
(electrical) channel length is important.
Leff  L  2L0
• More general value is Leff  L  L where L is the total
reduction in channel length due to overlap and other effects

Design
• The channel width is also smaller than the drawn
value due to a reduction of active area by the field
oxide (FOX) growth.
• This is called active area encroachment and leads to
an effective channel width
Weff  W  W
here W is drawn value and W is the total reduction in

channel width from all effects
The aspect ratio of the transistor that is used in the
electrical characterization is always the ratio of
effective values  Weff 
L 
 eff 
Design
Active Contacts

Design
• An Active Contact is a cut in oxide - OX1 that allows the
first layer of metal to contact with an active (n+ or p+)
region.
• Since the contact is placed to fall inside of an n+ or p+
region, it is subject to the surround design rule
• Sa-ac = minimum spacing between Active and Active
Contact
• The dimensions of the contact are given by
– dac,v = vertical size of the contact
– dac,h = horizontal size of the contact
– A square contact (with aspect ratio 1:1) is obtained if dac,v =
dac,h = dac, but other aspect ratios are also used
Design
Metal 1
Metal -1 is used for interconnecting signals and also for power supply
distribution. Figure shows the contact cut through the oxide being filled
with a metal plug.
The two design rules shown in the drawing are
Wm1 = minimum width of metal -1 line
Sm1-ac = minimum spacing between metal-1 and active contact
Sm1-m1 = minimum spacing between two adjacent patterns of metal-1
Design
Why multiple contacts?
In figure there are
total of 12 contacts
so effective
resistance is
resistance of one
contact divided by 12
Every contact is characterized by a resistance in ohms, Rc = contact

resistance in Ω. To limit the overall resistance it is common to use as
many contacts as the design rule permits. Since the contacts are in
parallel, the effective resistance of all in parallel reduces to 1
RC ,eff  RC
N
Design
Sp-ac = minimum spacing from poly to active contact
Sa-p = minimum spacing from active to poly

Design
Sm-pc = minimum spacing between metal-1 to poly contact
Sm-m = minimum spacing between two adjacent patterns of metal-1
dpc = dimension of poly contact

Design
Sp-p = minimum poly-to-poly spacing

Design
Sg-g shown in figure is not a design rule but can be
written in terms of design rules as Sg-g = dac + 2Sp-ac

Design
Sp-a = minimum spacing between poly and
Active
The nMOSFET to The nMOSFET to

the left is having a the right is
channel width of having a channel
W1 width of W2

Design
Vias and Higher Level Metals

Design
Via to connect metal-1 and metal-2
• dv = dimension of via
• Wm2 = minimum width of metal-2 feature
• Sm2-m2 = minimum spacing between adjacent metal-2 features
• Sv-m1 = minimum spacing between via and metal-1 edges
• Sv-m2 = minimum spacing between via and metal-2 edges
• Vias between other metal layers are similar, but values of Wmj and
Smj-mj for Jth metal layer vary for J > 1
• Although simple circuits can be created in a single poly, double
metal process, interconnect routing becomes difficult in complex
networks
• Layering sequence in multiple metal layer process is
– Metal-1 → Metal-2 → Metal-3 → Metal-4 → Metal-5 → Metal-6
• In general minimum width and spacing between adjacent layers of
metal patterns increases as one goes up for more layers of metal

Design
Latch-up Prevention
• Latch-up is a condition that can occur in a circuit
fabricated in bulk CMOS technology
• When the chip is in a state of latch-up it draws a large
current from the power supply but does not function in
response to input stimuli
• If while in operation the chip enters into a state of
latch-up, removing and reconnecting the power may
restore the operation
• In the worst-case situation, the chip may enter latch-up
when power is applied and never be functional
• If the latch-up current is too large, heat dissipation will
destroy the die
Design
Design
Two parasitic bipolar junction transistors
between power supply rails

VDD
p+ region source of pFET
p
A ( p-n-p) BJT
n-well with
n
p-substrate with
resistance Rn-well
resistance Rsub p
A (n-p-n) BJT n
n+ region source of nFET

GND
A four layer p-n-p-n junction

Design
Creation of latch-up condition
• The current flowing through the MOSFETs when they are ON, will have
current through the p-substrate and n-well
• These p-substrate and n-well currents will be capable of creating a voltage
drop across their respective bulk resistances
• If these voltage drops are greater than the respective parasitic BJTs cut-in
voltage VBE then the BJTs get turned ON, once these devices are ON they
start drawing more current ,and hence more voltage drop across the
parasitic resistances and finally current through the BJTs reaches their
saturation values
• Because the two parasitic BJTs and the two parasitic resistances are
effectively connecting the power supply rails, there will be a large current
flowing between the power supply rails called latch-up current
• For small voltages of VDD the current IDD is small because of the blocking
characteristics of the pn-junctions
• However if VDD reaches the breakover voltage VBO, the blocking property no
longer exists

Design
Latch-up prevention starts at the physical level with
various rules used to avoid the formation of the bad
current path

Design
Design rules to prevent latch-up condition
• Include an n-well contact every time the source terminal of a pFET
is connected to VDD
• Include a p-substrate contact every time the source terminal of an
nFET is connected to GND rail
• It is possible to reduce the possibility of the parasitic BJTs getting
turned ON by reducing the resistances of p-substrate and n-well by
increasing their doping levels
• In Silicon-on-insulator (SOI) designs the transistors are not built
directly on silicon substrate, in such non-bulk CMOS technologies
latch-up problem will not be there as there will not be pnpn
layering
• In advanced processing lines twin-tub process is used to avoid the
problem of latch-up, wherein nFETs are placed inside p-well and
pFETS are placed inside n-well

Design
Design
Important Aspects of Layout Editors
• n+ (ndiff) region is formed whenever Active is
surrounded by n-select
• p+ (pdiff) region is formed whenever Active is
surrounded by p-select
• An nFET is formed whenever poly cuts an n+ region
into two separate segments
• A pFET is formed whenever poly cuts a p+ region into
two separate segments
• No electrical current path exists between conducting
layers (n+, p+, poly, metal etc. ) unless a contact cut (
Active Contact, Poly Contact, or Via Contact ) is
provided
Design
Different layer keys for layout drawings
n+/p+ in green colour, poly in red colour, n-well in yellow colour, metal-
1 in blue colour, metal-2 in gray colour
The three different contact cuts are indicated by following different

hatch pattern in black colour

Design
Basic features of layout editor
• One enters a polygon by first choosing the desired layer of material and then using
the drawing tools shape the object as needed
• Layout editors provide a background grid, with a specified distance between each
grid point
• The layers may be drawn in any order, so long as each polygon is properly identified
by layer colour/name/pattern. The database automatically keeps track of the
polygons drawn on each layer
• The layout pattern is used to create the mask set for the process, and constitute
drawn dimensions
• Design rules must be obeyed and the spacing must be checked before the drawing
is complete
• Polygons on a given layer may be drawn to touch or overlap, only the outline is
important
• The most common format used for handing over designs in the form of mask set is
Government Digital Service (GDS)-format which is with computer-based CAD
systems, or Caltech Intermediate Format (CIF) which is for academic users
Design
After the layout is completed for a design it is put in a standard format
for transmission to the processing line. This process is called tape-out

Design
Cell Concepts
Digital VLSI chips are based on hierarchical design. Individual transistors

are used to build gates, which are then used to create logic cascades
and functional blocks, which in turn are used as the basis for even larger
units. The basic building blocks in physical design are called cells. A cell
may be as simple as a FET, or as complex as an ALU
Design
f  a b  a b
The example function is implemented using the simple cascade of cells

of a NOT gate and a NAND2 gate. The input and output terminals are
shown as ports into the cell. The cells also need power supply ports for
VDD and VSS that are chosen to be at the same locations for every cell.
Finally the width of the complex cell is sum of all the three cell widths
Design
Dm1-m1 = edge-to-edge distance between VDD and VSS & pitch
Pm1-m1 = distance between the middle of VDD and VSS lines
Pm1-m1 = Dm1-m1+WDD, where WDD is the power supply line width

Design
Fabrication specialists often use the pitch specification, while
the actual distance D between the edges is more useful for
circuit layout

Design
Effect of FET orientation on cell dimensions

Design
Effect of tile shapes on larger cells

Design
Difference between horizontal and vertical
orientation of FETs
Horizontal Vertical
Drain and source regions run horizontally Drain and source regions run vertically
Poly gate patterns run vertically Poly gate patterns run horizontally
Once the distance between the power Here it is easy to increase the channel
supply rails are fixed, increasing the width, since that does not disturb the
channel width is not possible distance between power supply rails
The layouts size will increase along Here the layout size increases along
vertical direction, if an attempt is made to horizontal direction, if the channel widths
increase the channel widths of FETs of FETs are increased
Increasing the channel width of FETs will Increasing the channel width of FETs
make the layout tall and thin makes the layout short and stout

Design
Interconnect Routing Considerations
• In complex digital systems wiring is more complicated than
designing transistor arrays
• One approach to this problem is to place rows of logic cells in
parallel and allocate space in between the rows for wiring
• Metal-1 lines running parallel to the logic rows can be used to
route signals as required
• Since metal-2 can cross over metal-1, vertical lines can be
used to connect logic cells to the metal-1 interconnect
• This technique is used in ASIC designs as it allows significant
amount of freedom for different designs
• The drawback with this scheme is low density compared to
close-packed layouts

Design
Metal-1 wiring is run horizontally in parallel with VDD
and GND rails, metal-2 wiring is run vertically to
connect to logic cells

Design
An alternate high density technique –
Weinberger Image

Design
Weinberger Image Array
• The n-well regions surround the VDD rails and
allow p-FETS to be created above and below VDD
rail
• While n-FETs are placed on both sides of VSS rail
• Since no space is automatically reserved for
wiring, this scheme allows for high density
placement of the cells
• The drawback of this scheme is that connection
between rows must be done using metal-2 and
higher, since metal-1 is already designated for
power supply rails
Design
Logic cells
Inverted
logic cells

Design
Port Placement
• Input output ports must be placed at convenient points to help
interconnect wiring
• At the basic level, inputs are to the gate terminals of MOSFETs,
while outputs are metal interconnect lines
• Since FET gates are at the poly-silicon level, we must provide poly
contacts to connect the output of a cell to the input of another cell
• Ports are placed around the periphery of a cell
• There are no a priori constraints on the placement of cell ports, and
interior ports are also used sometimes
• Wiring problems appear at critical times when cells are wired
together in complex design
• Careful cell planning and a reliable CAD tool set helps to solve the
problem of wiring efficiently

Design
A simple example showing port
placement
Through a poly-contact

Design
FET Sizing and Unit Transistor
W 
• FETs are specified by the aspect ratio =  
 L 
• Both channel length and width are of the order of
nano meters and are established in layout drawings
• These dimensions along with processing parameters
give the electrical characteristics of the transistor
• From the basic geometry of the FET, with the drawn
dimensions of channel length and width we estimate
some layout dependent electrical properties of the
transistor

Design
Area of the Gate =AG=LW
Looking into the gate

terminal is gate
capacitance CG
ID ≈ I S

Design
CG  CoxWL L
Rchannel  Rs ,c  
Gate capacitance is equal to W 
oxide capacitance multiplied be
area of gate
Channel resistance when the
L
Rchannel    transistor is ON is expressed in
terms of equivalent channel sheet
W  resistance and channel dimensions
It is possible to decrease channel resistance of an ON transistor by

increasing its channel width
Channel dimensions establish the resistance and capacitance of a FET

Design
• Primary difference between nFET and pFET is the
polarity of charge that give the current
• An nFET uses negatively charged electrons, while a
pFET relies on positively charged holes
• However electrons can move more easily than holes
• High value of mobility means that the particle is more
mobile than a low mobility particle
• Suppose we design an nFET and a pFET with the same
aspect ratio, since electrons have higher mobility, nFET
resistance is smaller than pFET resistance
• If both nFET and pFET are of the same size, nFET is
faster than pFET

Design
n   p n
Mobility ratio r
p
In modern processes ratio of mobility r is greater than unity and usually
lies between 2 and 3, with the actual value set by the doping densities
and other physical considerations
The resistance of a FET can be adjusted by changing the channel width
W. Suppose that we have an nFET with an aspect ratio (W/L)n that gives
a resistance Rn, to get a pFET with the same resistance value, we must
go for aspect ratio of pFET (W/L)p > (W/L)n that compensates for the
differences in mobilities . This is accomplished by selecting
However the gate areas are different with AGp > AGn
W  W 
   r  due to increased channel width of pFET, assuming
 L P  L n the channel lengths are same CGp = r CGn, since areas
are proportional to channel width
Design
Example
• An nFET with aspect ratio (W/L)n = 4 is constructed
in a process where mobility ratio = r = 2.4
• To create a pFET with the same resistance we must
select (W/L)p = 2.4(4) = 9.6
• Rounding to the nearest integer (W/L)p=10
• With this the gate capacitance of pFET is larger than
that of nFET by the same ratio r = 2.4
• CGp = 2.4 CGn

Design
• The electrical characteristics of transistors
determine the switching speed of a VLSI -Circuit
• At the physical level this translates to the device
aspect ratios of every FET in the circuit
• A useful starting point is to define a unit transistor
• One choice for a unit transistor is the minimum-size
MOSFET, which is the smallest transistor that can be
created using the design rule set
• The drawn channel length is the minimum allowed
poly width - Wp, while the drawn channel width is
minimum allowed active width - Wa

Design
W  Wa CG  CoxWaWp
  
 L  min W p
AG  WaWp
The minimum size device is the
smallest transistor, so that in theory it
allows highest packing density.
However it does have the largest
resistance of any FET, so it may not be
the best choice for every circuits

Design
In the basic minimum size FET with active contacts
allows metal-1 connections with which the
dimensions change
dc = dimension Sa-ac = spacing between active and active
contact
of the contact
Here channel width W < dc + 2Sa-ac

Design
Scaling
• Once a unit FET has been selected, it is useful to allow it to be
scaled in size
• If 1X transistor is used as the reference, then 2X and 3X versions
are with channel widths multiplied by 2 and 3 to that of the
channel width of reference 1X transistor
• If resistance and gate capacitance of 1X device is R1X and C1X
respectively with its channel width W1, then larger FETs are
created using a scaling factor S ≥ 1 such that WSX = SW1X
• Example setting S = 4 gives W4X = 4W1X, describes a 4X transistor
and its resistance and capacitance are R4X = R1X/4 and C4X = 4C1X
• In general resistance and capacitance of scaled transistor with a
scaling factor S are RSX = R1X/S and CSX = SC1X
• Since pFETs have different conduction characteristics than nFETs, it
is common to introduce unit transistors for each type, but the
scaling relations remain the same regardless of the polarity

Design
The reference unit transistor need not have its aspect ratio = unity, any value
can be used and the scaling relations are applied using that reference
transistor with scaling factor S > 1

Design
Resistance of series connected FETs
• In scaled series connected FETs the total resistance is the sum
of the individual resistances
• Series connected FETs are usually made larger than individual
FETs to reduce the overall end-to-end resistance
• There are occasions where aspect ratios reach 100 or more. A
single device with a large channel width W will have a long
rectangular shape and may not easily fit into the overall
layout, or the resistance of the gate material may slow down
the signal
• Most common solution is to use a group of parallel connected
FETs, all having the same channel width W and all the gates
are connected together so that the effective channel length is
channel length of a single device in the group multiplied by
the total number of transistors in the group

Design
There are four devices connected in parallel each having the same
channel width W, because all the devices gate terminals are wired
together, the effective channel length of the group of 4 transistors
acting together is 4L between sides A and B
An advantage of
this approach of
using large devices
is that the overall
layout geometry
can be adjusted to
square or nearly
square shape

Design
• The concept of scaling is not restricted to individual transistors, it may
be used to define series and parallel groups of FETs as 1X – reference
units

Design
Input is in metal-1 with a poly-contact, output is directly in
metal-1, aspect ratio of both nFET and pFET are equal and
so inverter switching is not symmetrical
FET orientation is horizontal

Design
The extra contact cut between n-well and VDD; between p-
substrate and GND are included to avoid latch-up problem

Design
Channel width Wp of pFET is greater than Wn of nFET by the
ratio of carrier mobility r
Ratio of
mobility r ≈ 2,
so to make
the
resistance of
pFET equal to n
that of nFET r
the channel p
width of pFET
is two times
the channel
width of
nFET,

Design
VDD to
n-well in n-well
yellow contact
Poly
contact
Shared ploy patterns in red colour
GND to p-substrate
contact

Design
Two series connected n-FETS of NAND2 gate and p-FETs of NOR2 gate
are sharing the same active regions, while parallel connected p-FETs
of NAND2 and n-FETs of NOR2 gates use separate active regions
n-well to
VDD
contact
Poly
contact
Shared poly patterns
GND to p-substrate contact

Design
For series connected FETs the channel width must be increased to
compensate for the series FET resistances that get added up. This is
required for the two nFETs in the pull-down block of NAND-2 and two
pFETs in pull-up block of NOR-2 gate
Wn of both Wp of the two

series parallel
connected connected pFETs
nFETs is same is double that Wn
and is = Wp of of two parallel
two pFETs connected nFETS

Design
out  ( x  y)  z
x y z

Design
General comments on layout
• Design a MOSFET logic circuit
• Use the transistor circuit to create a routing diagram where only
wiring paths and levels are important
• Use the routing diagram as the basis for the final physical design of
the gate that includes proper sizes for all features and sticks to the
design rules
• Some complex designs are tricky even for an experienced designer
• Final acceptance of a cell depends on its satisfying all electrical
and size specifications
• VLSI designers attempt to place as much circuitry on a given area
as possible
• At the engineering level this is accomplished by using the ideas of
regular, repeated patterns and mastering the CAD tools
• Design automation tools are becoming quite powerful and more
intelligent, and are helping designers to design circuits of
incredible complexity
Design
Design Hierarchies
• VLSI Systems are created using the concept of design
hierarchy, where simple building blocks are used to design
more complex circuits
• The simplest cell consists of only polygons, in which every
object is independent of every other object. A cell with this
property is said to be flat
• In a flat cell it is possible to alter any polygon without
affecting anything else
• A large number of flat cells are created and stored in the cell
library
• Once the library is established, instances of the library cells
are used to create new layout
• New cells created in this 2nd level can be also stored in the cell
library

Design
• In cell hierarchy, level-1 consists of only polygons representing the
material layers
• Level-2 consists of polygons and instances of level-1
• Level-3 may contain instances from level-1 and level-2 and
polygons
• The last group is made up of polygons and instances from any of
the lower level
• An instance is a copy of a simpler entity and its internal structure
cannot be altered at a higher level
• Example a level-2 cell is invariant when instanced in level-4
• The library created by a CAD tool vender is used by most users
• If a user can change the contents of an instance by decomposing
into polygons used the flatten command
• After the cell is flattened, all references to the original cell are lost
and individual features of the circuit can be modified

Design
Design
Every time a new cell is created it can be stored in the
library to be used in any design at a later point of time

Design
Level-1 is the bottommost and level-4
is the topmost in the hierarchy
Polygons
and
instances
from the
preceding
level of
hierarchy

Design
Contents of an instance can be changed by decomposing into
polygons using flatten command. After a cell is flattened all
references to the original cell are lost and individual features of the
circuit can be modified

Design
• Concept of building chips with millions of transistors
becomes possible by breaking down complex systems
into manageable sections
• Many libraries are built and maintained for use in many
different projects
• As layout is process dependent, a new library must be
built every time a new fabrication plant goes on-line
• Unless the new process is radically different, the old
cells are used as a starting point for the new group
• Sometimes it is possible to simply scale the dimensions,
which is the basis for the concept of cell reuse
• Many designs are created with reuse in mind and that
reduces the time to create a new chip
Design

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Unit 3 of Section B

Elements of Physical Design

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

• The actual fabricated structure on the chip will

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

• Drawn and Effective values in MOSFETs: The critical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

here W is drawn value and W is the total reduction in

unit- 3 of section B - Elements of Physical

Every contact is characterized by a resistance in ohms, Rc = contact

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

The nMOSFET to The nMOSFET to

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

The three different contact cuts are indicated by following different

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

Digital VLSI chips are based on hierarchical design. Individual transistors

The example function is implemented using the simple cascade of cells

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

Looking into the gate

unit- 3 of section B - Elements of Physical

It is possible to decrease channel resistance of an ON transistor by

Channel dimensions establish the resistance and capacitance of a FET

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical

unit- 3 of section B - Elements of Physical