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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics

A Family of Single-Phase Hybrid Step-Down PFC

Converters
Junming Zhang, Senior Member, IEEE, Chengdong Zhao, Student Member, IEEE, Siyang Zhao,
and Xinke Wu, Member, IEEE

Abstract—Buck Power Factor Correction (PFC) has attracted
a lot of research interests for its low output voltage and high
efficiency at low input condition. However, the traditional Buck
PFC converter usually has low power factor (PF) and poor
harmonic performance due to the inherent dead angle of the
input current, especially at low input condition. To solve this
problem, this paper proposes a family of hybrid PFC converter
topologies combining the advantages of step-up PFC and step-
down (Buck) PFC converters, which features low output voltage
and continuous input current (high PF). The derivation
methodology is presented in detail and two topologies are
selected as typical examples to explore their performances. With
the improved peak current control scheme, the two proposed
converters can achieve high PF under universal input range, and
their input current harmonics can easily meet the IEC61000-3-2
Class C limits. The optimal design considerations are presented
and two 150W prototypes are built to verify the theoretical
analysis.
converter will much lower at low input condition for such
wide input condition [6].
Recently, using a Buck (step-down) converter as a front-
end PFC converter has been introduced in [6]-[27]. The Buck
PFC converter has higher low-line efficiency and lower EMI
noise compared to the Boost PFC converter [6], [14]. The
traditional Buck PFC converter and its steady state operation
waveforms are shown in Fig. 1. Due to the inherent dead time
in the input current when the input voltage is lower than the
output voltage, the Buck PFC usually has limited PF and high
current distortion, which is hard to meet the current harmonic
requirements, especially for lighting applications.

Index Terms—Hybrid converters, power factor correction

(PFC), peak current control, class C, high efficiency.

I. INTRODUCTION

The ever-present trend of size reduction of power supplies

requires even higher efficiency and power density. For power
supplies above certain power rating, a front-end PFC
converter is necessary to meet the harmonic current and
power factor (PF) requirements, such as IEC61000-3-2 and
Energy Star specifications [1]-[2]. At present, the Boost (step-
up) converter is the most popular PFC topology due to its
simplicity and good performance [3]-[5]. However, the output
voltage of Boost PFC converter should be higher than the
maximum input peak voltage. It is preferred that the AC input
voltage range of a power supply should be wide to cover Fig.1. The traditional Buck PFC converter and its steady state
different applications in different countries. For typical waveforms: (a) Buck converter. (b) Steady state waveforms.
universal input, the AC input voltage ranges from 90Vrms to
A lot of researches have been conducted to analyze and
264Vrms considering the voltage variation. However, the
improve the PF performance of the Buck PFC converter [8]-
input voltage will be even wider for some applications like
[26]. One method to improve its PF is using improved control
LED lighting, which may connect to 277Vrms grid or even
scheme. An improved Variable On-Time (VOT) control
480Vrms grid (the North American industrial power grid).
scheme is introduced in [24]. This control scheme can reduce
Therefore, the output voltage will be unbearably high for
the harmonic current contents and improve the PF compared
Boost PFC converter. Besides, the efficiency of a Boost PFC
to the traditional Constant On-Time (COT) control scheme.
Manuscript received March 26, 2016; revised June 23, 2016; accepted However, the parameters should be very carefully designed
August 22, 2016. This work was supported by National Natural Science and the harmonic current contents margins are small to meet
Foundation of China under Grant 51277161, Grant 51522704, and Grant IEC61000-3-2 Class C limits. In literature [25], an improved
51477154, Fundamental Research Funds for the Central Universities
peak current control scheme is presented. Although the PF
(2015XZZX004-27).
The authors are with the College of Electrical Engineering, Zhejiang and harmonic current contents are better than the traditional
University, Hangzhou 310027, China. (e-mail: zhangjm@zju.edu.cn; control scheme, it is still hard to meet IEC61000-3-2 Class C
zhaocd@zju.edu.cn; 21410173@zju.edu.cn; wuxinke@zju.edu.cn). limits due to the dead angle of the input current.

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Transactions on Power Electronics
Another method is compensating the current during the
dead time to further improve its PF performance, and an extra
converter can be integrated with the Buck PFC converter [10],
[17]-[20]. A Buck PFC with an active buffer was proposed in
[18] and almost unity power factor can be achieved, but the
circuit needs extra active switches and bulky high voltage
capacitor and inductor. A Buck PFC integrated with a Buck-
Boost and a Flyback circuit has been proposed in [19] and
[20], respectively. Unfortunately, no systematical derivation
methodology has been proposed to give a thorough insight for
these kinds of topologies.
In order to solve the issues mentioned above, this paper
proposes a family of single phase hybrid step-down PFC
converters with high power factor. The objective of hybrid
PFC converter is to combine the advantages of the step-up
PFC and the Buck PFC to further improve their performance.
In Section II, the derivation methodology of hybrid step-down
PFC converters is discussed and two optimal topologies are
selected to further disclose their operation principles. The
control method and design considerations of the two proposed
converters are presented in Section III. Finally, the
experimental results from two 150W prototypes with
universal AC input and 80Vdc output voltage are presented in
Section IV. Section V concludes this paper.
II. HYBRID STEP-DOWN PFC CONVERTERS
In this section, a family of hybrid step-down PFC
converters is presented and the derivation methodology is
discussed [28]. The main idea is integrating a step-up
converter with the Buck converter to compensate the input
current during the dead time, which is referred as the hybrid
method in this paper. The step-up converter can be a Boost
converter or a Buck-Boost converter (also a Flyback converter
as its isolated version).
Generally, there are two ways to integrate a step-down
converter with a step-up converter, i.e. cascade connection
and parallel connection, respectively.
A. Cascade Connection
The circuit diagram of a hybrid PFC with cascade
connection is shown in Fig. 2(a). The circuit shown in Fig.
Fig. 2. Hybrid PFC with cascade connection: (a) Circuit diagram. (b)
Four-switch Buck-Boost converter.
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2(b) is an example of cascade connection, which is a kind of
traditional four-switch Buck-Boost converter [29]. When the
input voltage is lower than the output voltage, Q1 is always on
and the circuit operates as a Boost converter. While the input
voltage is higher than the output voltage, Q2 is off and the
circuit operates as a Buck converter. However, the circuit has
large device counts, high conduction loss and needs a high-
side (HS) gate driver, which is not preferred in practical
applications.
B. Parallel Connection
The circuit diagram of a hybrid PFC with parallel
connection is shown in Fig. 3. In this structure, the step-up
converter should have the input and output disconnecting
capability, simple structure and the capability of sharing some
components with buck converter. Since the Boost converter
does not have the disconnection capability between the input
and the output terminals, it cannot be adopted in parallel
connection structure. The Buck-Boost converter is a good
candidate since it has the disconnection capability, low device
counts and similar structure with the buck converter. As
shown in Fig. 4, the Buck converter and Buck-Boost
converter have very similar input structure (shown in green
dash box) and output structure (shown in red dash box), so
they can share part of the components during the integration.
Based on the shared components, there are three ways to
integrate the two converters to derive a new hybrid PFC
converter.
Fig. 3. Circuit diagram for hybrid PFC with parallel connection.
Fig. 4. Similarity between Buck and Buck-Boost converters: (a) Buck
converter. (b) Buck-Boost converter.
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1) Sharing the input block
Fig. 5 shows the derived hybrid PFC converter based on
Buck converter and Buck-Boost converter by sharing the
input block (the active switch and the input full-bridge
rectifier (FBR)). It can be seen that this topology need two
independent inductors, two freewheeling diodes (D1 and D2)
and two extra diodes (D3 and D4). D3 is used to avoid the
output capacitor discharging when D2 is on, and D4 is used to
prevent inductor L1 charging up when D1 is on.
Fig. 5. Hybrid PFC converters with parallel connection – sharing the
input block.
When the input voltage is higher than the output voltage,
the Buck converter and Buck-Boost converter work
simultaneously. When Q1 turns on, L1 is charged up through
Q1, D3 and D4, and L2 is charged up through Q1. When Q1
turns off, L1 freewheels through D1, D4 and output, L2
freewheels through D1, D2 and output. If the input voltage is
lower than the output voltage, the Buck converter stops
working because D4 is reverse biased, and only the Buck-
Boost converter operates as before. From the operation
described above, the topologies shown in Fig. 5 has high
conduction loss and large component counts. They are usually
Fig. 6. Hybrid PFC converters with parallel connection – sharing the output block.
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not suitable for practical applications.
2) Sharing the output block
Fig. 6 shows the hybrid PFC converters by sharing the
output block (inductor and diode). For Buck topology, since
the Buck switch Q1 and inductor L1 can be placed in the low
side or the high side, there are total four configurations for a
Buck converter.
For hybrid PFC converters based on Buck and Buck-Boost,
by adding two input rectifier diodes and a switch to each
Buck topology to provide another charging path for the
inductor L1, there are four hybrid PFC topologies, i.e.
topology 1 to topology 4 as shown in Fig. 6 (a) to (d).
Since the Flyback converter is the isolated version of the
Buck-Boost converter, it can also be integrated with a Buck
converter using a coupled-inductor, as shown in Fig. 6 (e) to
(h). Theoretically, there will be total eight configurations. In
order to get a non-floating output, the inductor and the buck
switch should be at the same side (both at the low side or the
high side). Thus, only the topologies based on topology 1 and
topology 3 are presented here. It can be recognized that
topologies 5 and 8 are the corresponding ones to topology 1.
And topologies 6 and 7 are the corresponding ones to
topology 3. The other four topologies corresponding to
topologies 2 and 4 are not presented since they have same
performance except the floating output when compared to
topologies 5 to 8.
Among these topologies, topology 2 and topology 7 are
already proposed in [19] and [20]. All the topologies except
topology 7 need high-side gate driver. Besides, for topologies
1 and 3, the Buck switch should be always on for Buck-Boost
mode operation, so the conduction loss of the Buck switch
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will be high. Furthermore, for topologies 2 and 4, the output
terminal is always floating in both Buck mode and Buck-
Boost mode, which will increase the EMI noise. For topology
1, 3, 5 and 7, the output terminal only floats in Buck-
Boost/Flyback mode, compared to topologies 2 and 4, the
EMI noise may be a little reduced. And for topologies 6 and 8,
the output terminal is not floating.
The topologies shown above only need one inductor
(coupled inductor), which is attractive for size reduction.
However, the differential mode (DM) filter must be located in
the AC side, which will increase the size of the EMI filter.
Furthermore, the conduction loss of the input rectifier diodes
will be high due to the input current with the switching
frequency component flowing through it.
3) Sharing the input FBR & the output block
The hybrid PFC converters by sharing the input full-bridge
rectifier (FBR) and the output block are shown in Fig. 7,
Fig. 7. Hybrid PFC converters with parallel connection – sharing the
FBR & the output block.
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which includes the topologies corresponding to the ones in
Fig. 6 with a modification where the positive or negative half
of the FBR associated with the Buck-Boost/Flyback switch is
removed, and instead, the Buck-Boost/Flyback switch is
directly connected to the output of the input FBR. In order to
avoid the output capacitor discharging when the switch Q 2 is
on, the switch Q1 should be a unidirectional switch, so a
Schottky diode D2 in series with Q1 can be used. It can be
recognized that topologies 9 and 10 are the corresponding
ones to topologies 2 and 4 after the above modification. In the
same way, topology 11 corresponds to topologies 6 and 7, and
topology 12 corresponds to topologies 5 and 8. Particularly,
the above modification cannot be applied for topologies 1 and
3.
For topologies shown in Fig. 6, the differential mode (DM)
filter must be located in the AC side. However, by sharing the
input FBR, the DM filter can be located in the DC side
because the input current of Buck and Buck-Boost/Flyback
mode both flows through the same FBR. In this way, the sizes
of DM capacitors can be largely reduced and the conduction
loss of the FBR can also be reduced.
A summary of the derived hybrid step-down PFC
converters based on Buck converter and Buck-Boost/Flyback
converters is shown in Table I. Among all the topologies, the
topologies 9 and 11 are easy to drive (do not need high-side
gate driver), need the least extra components and the DM
filter can be located in the DC side, which are attractive for
practical applications. Besides, topology 9 utilizes the
magnetic core more efficiently because only one inductor
winding is needed. For topology 11, the common mode (CM)
interference is small because the output terminal is not
floating. In this paper, these two topologies are taken for
further evaluation, where the topology 9 is referred as
Buck+Buck-Boost converter and the topology 11 is referred
as Buck+Flyback converter, respectively.
III. CONTROL METHOD AND DESIGN CONSIDERATIONS
In order to achieve a seamless transition between the Buck-
Boost/Flyback mode and the Buck mode operation, an
improved peak current control scheme for the proposed
topologies are presented in this section. All the calculations
and analysis below are based on two 150W prototypes with
90-265Vac universal input. The output voltage is set to 80Vdc
for the balance of high-line and low-line efficiency [25]. The
converter is operated in critical conduction mode (CRM) with
peak current control scheme. The operation mode transition
voltage Vswitch for the Buck mode and Buck-Boost/Flyback
mode is usually the same as the output voltage, which means
when the instant input voltage is below this value, the
converter operates in step-up mode, otherwise it operates in
Buck mode.
A. Improved Peak Current Control Scheme
Both the harmonics and power factor are determined by the
average input current. In this work, the peak input current is
controlled using a multiplier as shown in Fig. 8, which is
widely used in low power PFC converters. Vref1(t) and Vref2(t)
are the current waveform references to control the peak
current in Buck-Boost/ Flyback mode and Buck mode, and
the symbol MUX is a multiplexer deciding whether Vref(t) is
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TABLE I COMPARISON OF HYBRID PFC CONVERTERS WITH PARALLEL CONNECTION

HS Driver needed Step-up operation EMI filter Extra Components Floating Output

Topology 1 YES Q1: On, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 2 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 3 YES Q1: On, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 4 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 5 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 6 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch NO

Topology 7 NO Q1: Off, Q2: PWM AC side 2 diodes, 1 switch YES

Topology 8 YES Q1: Off, Q2: PWM AC side 2 diodes, 1 switch NO

Topology 9 NO Q1: Off, Q2: PWM DC side 1 diode, 1 switch YES

Topology 10 YES Q1: Off, Q2: PWM DC side 1 diode, 1 switch YES

Topology 11 NO Q1: Off, Q2: PWM DC side 1 diode, 1 switch NO

Topology 12 YES Q1: Off, Q2: PWM DC side 1 diode, 1 switch NO

Fig. 8 Main circuits with improved peak current control scheme: (a) Buck+Buck-Boost converter (Topology 9). (b) Buck+Flyback converter (Topology 11).

equal to Vref1(t) or Vref2(t). With proper selected peak current i peak _ buck (t )  Vref 2 (t ) Vcomp / Rcs
reference, a smooth transition between two operation modes 
can be achieved. Vref 2 (t )  kb1  (Vin sin t  kb 2 Vo ) (3)
The average input current iavg(t) of the proposed hybrid 
kb1  Rv 4 / ( Rv 3  Rv 4 )
PFC converter in half a line cycle can be calculated as k  R / ( R  R )
1 Vo  b2 v1 v1 v2

 2  i peak _ buck (t )  V sin t t0  t    t0 i peak _ flyback (t )  Vref 1 (t ) Vcomp / Rcs
 in

1 nVo Vref 1 (t )  k f Vin sin t (4)
iavg (t )    i peak _ flyback (t )   0  t  t0 and
2 Vin sin t +nVo 
   t0  t   ) k f  RL 2 / ( RL1  RL 2 )
 Vin is the peak input voltage, Vo is the output voltage.
 (1) ipeak_buck(t) and ipeak_flyback(t) represent the instant peak current
of Buck and Buck-Boost/Flyback operation in the proposed
where hybrid converters, respectively. ωt0 is the transition point
Vswitch between Buck-Boost/Flyback mode and Buck mode operation.
t0  arcsin (2)
Vin Parameter n is the turns ratio (N2/N1) of the coupled inductor
in topology 11 (Buck+Flyback) as shown in Fig. 8 (b), while
it is equal to 1 in topology 9 (Buck+Buck-Boost). Vcomp is the
output of the voltage feedback loop, which is related to the
output power and keeps almost constant during half a line

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 i peak _ buck (t )  Lm
 t0  t    t0
 V o

 i (t )  n  Lm
Toff (t )   peak _ flyback  0  t  t0 and  (8)
 V o
   t0  t   )


Due to the CRM operation, the switching frequency varies
with the input voltage and load condition. Similar to most
traditional CRM PFC design method, the inductance is mainly
Fig. 9 Theoretical current waveforms with proposed control scheme designed based on the switching frequency at full load
condition. At low input voltage, the switching frequency
cycle. kb1, kb2 and kf are the ratio of the resistor dividers R v3 should be above 20 kHz to avoid audible noise. At high input
and Rv4, Rv1 and Rv2, RL1 and RL2, respectively, which are voltage, the switching frequency should not be too high
used to generate the peak current waveform references from considering the EMI performance, it’s better to keep the
input and output voltage. In topology 11, the two references switching frequency at high input condition be below 150 kHz
Vref1(t) and Vref2(t) can be obtained from input and output or even 75 kHz for better EMI performance.
voltages by the resistor dividers, and the parameters kb1, kb2 Since the proposed hybrid converter is mainly operated in
and kf are given in (3) and (4). In topology 9, Vref2(t) is Buck mode, the switching frequency of Buck mode is much
generated by a subtracter, and the component kb1*kb2*Vo is more important for the converter performance. Fig. 10 shows
obtained by a fixed DC voltage Vb2 as shown in Fig.8 (a), the switching frequencies in Buck mode with different PFC
while kb1 and kf still keep the same as given in (3) and (4). inductance. The switching frequency is proportional to the
In order to achieve a smooth transition between Buck mode input voltage and inversely proportional to the inductance.
and Buck-Boost/ Flyback mode, the input voltage and average From Fig. 10 (a), it can be found that a smaller inductance
input current should meet (5) at the transition point ωt0 such as 120μH is preferred for a higher minimal switching
Vin sin t0  Vswitch
 frequency at 90Vac input. Nevertheless, a larger inductance
 (5) such as 150μH is preferred for better EMI performance, as
iavg _ buck (t0 )  iavg _ flyback (t0 )
 shown in Fig. 10 (b). It is reasonable to design the inductance
Generally, Vswitch is designed to be the same as Vo from (5), between these ranges. In this work, Lm is chosen as 135μH for
the relationship between kb1, kb2 and kf can be obtained as the prototypes.
1 n
kf   kb1  (1  kb 2 ) (6)
n
As long as the parameters kb1, kb2 and kf satisfy equation (6),
a smooth current transition between Buck-Boost/ Flyback
mode and Buck mode can be achieved, which is not affected
by the variation of the input voltage. The theoretical current
waveforms under different input voltages are shown in Fig. 9.
B. Design Considerations of the Inductance Lm and the Turns
Ratio n
In the hybrid PFC converter, the switching frequency is
mainly determined by the PFC inductance Lm. The turns ratio
n only affects the switching frequency in the Flyback mode
operation. According to the peak current control scheme and
voltage-second balance, Ton and Toff in the two operation
modes can be expressed in (7) and (8)

 i peak _ buck (t )  Lm
 t0  t    t0
 Vin sin t  Vo
 i peak _ flyback (t )  n 2  Lm
Ton (t )    0  t  t0 and  (7)
 Vin sin t
   t0  t   )

 Fig. 10 Calculated switching frequency in the Buck mode versus
different input voltages: (a) Vin=90Vac. (b) Vin=220Vac.

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Fig. 13 Calculated input current waveforms with different parameter kb2.

Fig. 11 Normalized output power distribution in Buck mode and

Flyback mode operation.

For topology 11, the normalized output power carried by

Buck mode and Flyback mode can be calculated according to
(9). Fig. 11 shows the calculated output power distribution in
Buck mode and Flyback mode with n varies from 0.1 to 10. It
can be seen that the turns ratio n only slightly affects the power
distribution between these two modes.
  t0 k f Vcomp  nVo  (Vin sin t )
2

  Po 0
 Pflyback _ nor (n) 
 Vin sin t  nVo
P
 buck _ nor (n)  1  Pflyback _ nor (n)
(9)
where η is the efficiency of the converter, Po is the output
power.
Fig. 12 shows the calculated switching frequency in half a
line cycle with n=0.5, 1 and 2. It can be seen that the turns
ratio n has a strong influence on the frequency in the Flyback
mode. A smaller n will lead to a higher frequency in Flyback
mode, for example, when n=0.5, the highest frequency will be
above 1MHz theoretically. On the other hand, a bigger n will
increase the coupled inductor size because more turns are
required for the Flyback winding. Generally, n=1 is an
appropriate turns ratio for topology 11. Therefore, topology 9
and topology 11 have the same main circuit parameters and
control scheme.
C. Harmonics Analysis and Design Considerations for
Parameter kb2
The parameter kb2 determines the peak current waveform in
the Buck mode, so it also determines the average input current
Fig. 12 Calculated switching frequency with different turns ratio n.
d t
Fig. 14 Calculated harmonics and THD varied with the parameter kb2: (a)
3rd and 5th harmonic. (b) 7th and 9th harmonic. (c) THD.
waveform. Therefore, the input current harmonics and the
THD are affected by this parameter. Fig. 13 shows the
calculated average input current waveforms with kb2=0.5, 0.7
and 0.9.
The harmonic spectrum of the input current waveform can
be calculated by using Fourier decomposition. To compare
with the IEC61000-3-2 Class C limits, the odd-order
harmonic current contents from 3rd to 9th varied with the
parameter kb2 are shown in Fig. 14 (a) and (b). The higher
order (greater than 9th) harmonic current contents can also be
analyzed in the same way, which are not repeated here
because they are usually much easier to meet the IEC61000-3-
2 Class C limits in the proposed converters.
Fig. 14 can be used to select the appropriate parameter kb2
for the proposed converters. As shown in Fig. 14 (a) and (b),
the 3rd and 7th harmonic current components are always below
the limits. The 5th and 9th harmonic current contents will be
below the limits when kb2 is below 0.92. Besides, as shown in
Fig. 14 (c), the minimal THD is about 4.5% when the
parameter kb2 is around 0.7. Thus, kb2=0.7 is an optimal value
for the harmonic performance of the proposed converters.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics

IV. EXPERIMENTAL RESULTS
Two 150W prototypes using topology 9 and topology 11
with universal AC input and 80Vdc output are built to verify
the proposed hybrid PFC converters and the control method.
The main circuits and control schemes of these two topologies
are shown in Fig. 8. The PQ2625 ferrite core is adopted for
the inductor in topology 9 and the coupled inductor in
topology 11. For these two topologies, the PFC inductance is
set to 135μH and the parameter kb2 is set to 0.7. For topology
11, the turns ratio n of the coupled inductor is set to 1 as
discussed above. Considering the output voltage ripple, the
switching voltage Vswitch for the Buck mode and Buck-
Boost/Flyback mode is set to 85Vdc in the prototypes. For
comparison, a 150W prototype of the traditional Buck PFC
converter with same parameters is also built up. The key
TABLE II KEY PARAMETERS OF THE TWO PROPOSED PROTOTYPES
parameters of the prototypes are shown in Table II.
The input voltage and input current waveforms of the
traditional Buck PFC and the two proposed hybrid PFC
converters with full load at 110 and 220Vac inputs are shown
in Fig. 15. It can be seen that the dead time of the input
current is eliminated in the two proposed converters, and the
current waveforms are almost the same for the two proposed
topologies.
The measured PFs of the traditional Buck PFC converter
and the two proposed hybrid PFC converters are shown in Fig.
16. Obviously, the PF is greatly improved in the proposed
converters at low line voltage. The measured harmonic
contents of the input current at 110Vac and full load condition
are shown in Fig. 17. It can be seen that the proposed
converters can easily meet the IEC61000-3-2 Class C limits
with large margins.

Parameters Symbol Value

AC input voltage Vin 90-265V (RMS)

Output Vo/ Io 80V/1.875A

Switch S1, S2 IPA60R160P6

PFC diode D1 MUR860

Auxiliary diode D2 MBR30H150

Inductor/Coupled inductor L/ T 135μH

Rectifier bridge B GSIB1560

Output capacitor Co 100V/940μF

Controller Q L6562D Fig. 16 Measured PF at different input voltages and full load.

Fig. 15 Measured input voltage and input current of traditional Buck PFC and the two proposed hybrid PFC converters: (a), (b), (c) Traditional Buck,
Topology 9, Topology 11 at 110Vac input. (d), (e), (f) Traditional Buck, Topology 9, Topology 11 at 220Vac input.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics

The measured THD of the traditional Buck PFC at 110Vac

input is 28.3% while it is reduced to 4.8% and 7.6% in
topology 9 and topology 11, respectively. The THD of
topology 9 is lower than that of topology 11, and it is much
closer to the theoretical calculated value given in Fig. 14 (c).
The difference is mainly caused by the peak current reference
waveforms for Buck mode. The current reference for topology
9 is derived from a subtracter as discussed above, i.e. the
rectified input voltage minus a constant DC voltage. For
topology 11, the reference is directly obtained from the
rectified input voltage minus the output voltage, which is
indicated as Vref2(t) in Fig. 8 (b), and it contains 100Hz output
voltage ripple.

Fig. 20 The waveforms of output voltage ripple at 110Vac input and full
load: (a) Buck converter. (b) Topology 9. (c) Topology 11.

Fig. 17 Measured harmonic contents of the input current at 110 Vac

and full load.
The waveforms of mode transient between Buck mode and
Buck-Boost/Flyback mode are shown in Fig. 18 and Fig. 19,
respectively. Fig. 18 (a) and Fig. 19 (a) shows the transition
process from Buck-Boost/Flyback mode to Buck mode. Fig.
18(b) and Fig. 19 (b) shows the transition process from Buck

Fig. 21 Measured full-load efficiencies under different input voltages.

mode to Buck-Boost/Flyback mode. As shown in Fig. 18 and

Fig. 18 The waveforms of Vin, Vswitch, VDS_buck, and VDS_buck-boost in
Buck+Buck-Boost (topology 9) converter: (a) Transition from Buck-
Boost mode to Buck mode. (b) Transition from Buck mode to Buck-
Boost mode.
Fig. 19 The waveforms of Vin, Vswitch, VDS_buck, and VDS_flyback in
Buck+Flyback (topology 11) converter. (a) Transition from Flyback
mode to Buck mode. (b) Transition from Buck mode to Flyback mode.
19, the transition processes between the two modes are
controlled by the transition signal Vswitch. The transition points
are symmetrical and the transition processes are smooth and
natural.
The output voltages Vout of the prototypes are also
measured, as shown in Fig. 20. It can be seen that the output
voltage ripples are reduced in the proposed converters due to
the elimination of the input current dead time.
The efficiencies of Buck converter and the two proposed
converters under different input voltages and full load are
given in Fig. 21. The efficiency of the traditional Buck
converter is slightly higher than that of the proposed
converters. Besides, the efficiency of topology 9 is 0.2%
higher than that of topology 11 due to the higher utilization of
the magnetic core.
Fig. 22 shows the measured conduction noise of topology
11 with the same DM filter located in the AC side or the DC
side under 220Vac input. The DM filter is a LC filter as
shown in Fig. 8, the values of which are 350μH and 2.2μF.
Compared Fig. 22 (a) with Fig. 22 (b), it can be seen that the
EMI result of the converter with a DC side DM filter
performs a little bit better and both of them can pass the
EN55022B standard. However, the size of DM filter can be

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2604845, IEEE
Transactions on Power Electronics
Fig. 22 EMI measurements of topology 11 with 220Vac input and full
load: (a) DM filter in the AC side (b) DM filter in the DC side.
Fig. 23 The photo of the prototypes
greatly reduced when it is located in the DC side because no
large X-cap is required. The photo of the prototypes is shown
in Fig. 23, the two prototypes are exactly the same except the
inductor.
V. CONCLUSION
This paper derives a family of hybrid step-down PFC
converters based on Buck converter and Buck-Boost (or
Flyback) converter. Two novel hybrid topologies with simple
structure and good performance are proposed. Both of the
switches in the converters are easy to drive and the EMI filters
can be placed in the DC side to improve the power density and
conversion efficiency. With the improved peak current control
scheme, the PF is above 0.9 in the full input voltage range and
the input current can easily meet the IEC61000-3-2 Class C
limits as well, which are quite attractive for industrial
applications like LED drivers. The experimental results from
two 150W prototypes with universal AC input verify the
theoretical analysis and the advantages mentioned above.
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Particularly, topology 11 is much more recommended for its
non-floating output.
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