DOC/LP/01/28.02.

02

LP – CS6303
LESSON PLAN
LP Rev. No : 00
Sub Code: CS6303
Date : 20/06/2014
Sub Name: COMPUTER ARCHITECTURE

Unit : I Branch : BE(CSE) Semester : III Page: 01 of 06

UNIT I OVERVIEW & INSTRUCTIONS

Eight ideas – Components of a computer system – Technology – Performance – Power wall –

Uniprocessors to multiprocessors; Instructions – operations and operands – representing instructions–
Logical operations – control operations – Addressing and addressing modes.

Objectives:

 To make students understand the basic structure and operation of digital computer.

Teaching
S.NO. Topic to be covered Duration Reference
Method
Introduction
1 50 minutes Text Book BB/PPT
Eight Great Ideas in Computer Architecture
Components of a Computer System,
2 50 minutes Text Book BB/PPT
Technologies for Building Processors and Memory
Performance: Defining Performance, Measuring
Performance, CPU Performance and Its Factors,
3 50 minutes Text Book BB/PPT
Instruction Performance, The Classic CPU
Performance Equation
4 Power Wall 50 minutes Text Book BB/PPT

5 The Switch from Uniprocessors to Multiprocessors 50 minutes Text Book BB/PPT

Instructions: Operations of the Computer Hardware

6 50 minutes Text Book BB/PPT
Operands of the Computer Hardware
7 Representing Instructions in the Computer 50 minutes Text Book BB/PPT

Logical Operations
8 50 minutes Text Book BB/PPT
Control Operations
9 Addressing and Addressing Modes 50 minutes Text Book BB/PPT

1
 DOC/LP/01/28.02.02

LP – CS6303
LESSON PLAN
LP Rev. No : 00
Sub Code: CS6303
Date : 20/06/2014
Sub Name: COMPUTER ARCHITECTURE

Unit : II Branch : BE(CSE) Semester : III Page: 02 of 06

UNIT II ARITHMETIC OPERATIONS

ALU - Addition and subtraction – Multiplication – Division – Floating Point operations – Subword
parallelism.

Objectives:

 To familiarize the students with arithmetic and logic unit and implementation of fixed point
and floating-point arithmetic operations.

Teaching
S.NO. Topic to be covered Duration Reference
Method
10 ALU: Addition and Subtraction 50 minutes Text Book BB/PPT

11 Multiplication 50 minutes Text Book BB/PPT

12 Division 50 minutes Text Book BB/PPT

13 Floating Point Representations 50 minutes Text Book BB/PPT

14 Floating Point Addition 50 minutes Text Book BB/PPT

15 Floating Point Multiplication 50 minutes Text Book BB/PPT

16 Subword Parallelism: Data Level Parallelism 50 minutes Text Book BB/PPT

2
 DOC/LP/01/28.02.02

LP – CS6303
LESSON PLAN
LP Rev. No : 00
Sub Code: CS6303
Date : 20/06/2014
Sub Name: COMPUTER ARCHITECTURE

Unit : III Branch : BE(CSE) Semester : III Page: 03 of 06

UNIT III PROCESSOR AND CONTROL UNIT

Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining –

Pipelined datapath and control – Handling Data hazards & Control hazards – Exceptions.
Objectives:

 To expose the students to the concept of pipelining.

S.NO Teaching
Topic to be covered Duration Reference
. Method
Basic MIPS implementation Text Book BB/PPT
17 50 minutes

18 Building Datapath, Creating a Single Datapath 50 minutes Text Book BB/PPT

Control Implementation scheme: The ALU Control, Designing the Text Book BB/PPT
19 Main Control Unit
50 minutes

20 The Simple Datapath with the Control Unit 50 minutes Text Book BB/PPT

An Overview of Pipelining, Single Cycle versus Pipelined Text Book BB/PPT

21 50 minutes
Performance
22 Pipelined version of Datapath 50 minutes Text Book BB/PPT

23 Pipelined control: Adding Control to the Pipelined Datapath 50 minutes Text Book BB/PPT

24 Handling Data hazards: Datapath to Resolve Hazards via Forwarding 50 minutes Text Book BB/PPT

25 Data hazards and Stalls 50 minutes Text Book BB/PPT

Control hazards: The Impact of Pipeline on the Branch Instruction , Text Book BB/PPT
26 Reducing the Delay of Branches, Dynamic Branch Prediction
50 minutes
Exceptions: How Exceptions are Handled in the MIPS Architecture,
27 Exceptions in Pipelined Implementation 50 minutes Text Book BB/PPT

LP – CS6303
LESSON PLAN

3
 DOC/LP/01/28.02.02

Sub Code: CS6303 LP Rev. No : 00

Sub Name: COMPUTER ARCHITECTURE Date : 20/06/2014

Unit : IV Branch : BE(CSE) Semester : III
Page: 04 of 06

UNIT IV PARALLELISM

Instruction-level-parallelism – Parallel processing challenges – Flynn's classification – Hardware

multithreading – Multicore processors

Objectives:

 To expose the students to the concept of parallelism

Teaching
S.NO. Topic to be covered Duration Reference
Method
Parallelism via Instructions-Instruction-level-parallelism: Software Text Book BB/PPT
28 based approach to exploiting Instruction Level Parallelism
50 minutes

29 Hardware based approach to exploiting Instruction Level Parallelism 50 minutes Text Book BB/PPT

30 Parallel processing challenges 50 minutes Text Book BB/PPT

31 Flynn's classification: SISD, MIMD, SIMD, SPMD and Vector 50 minutes Text Book BB/PPT
Hardware multithreading: Fine-Grained Multithreading, Coarse- Text Book BB/PPT
32 Grained Multithreading
50 minutes

33 Simultaneous Multithreading 50 minutes Text Book BB/PPT

Multicore processors: The need for Multicore, Multicore Basics, CMP Text Book BB/PPT
341 Architecture
50 minutes

351 Intel Multi-core architecture, Homogeneous vs. Heterogeneous Cores 50 minutes Text Book BB/PPT

361 Cell Processors, Multicore Challenges 50 minutes Text Book BB/PPT

LP – CS6303
LESSON PLAN

4
 DOC/LP/01/28.02.02

Sub Code: CS6303 LP Rev. No : 00

Sub Name: COMPUTER ARCHITECTURE Date : 20/06/2014

Unit : V Branch : BE(CSE) Semester : III
Page: 05 of 06

UNIT V MEMORY AND I/O SYSTEMS

Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache
performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts,
I/O processors.
Objectives:

 To familiarize the students with hierarchical memory system including cache memories and
virtual memory.
 To expose the students with different ways of communicating with I/O devices and standard
I/O interfaces.

Teaching
S.NO. Topic to be covered Duration Reference
Method
37 Memory hierarchy - Memory technologies 50 minutes R1 BB/PPT

38 Cache basics, Mapping Functions 50 minutes R1 BB/PPT

Measuring and improving cache R1 BB/PPT
39 Performance
50 minutes

40 Virtual memory Organization 50 minutes R1 BB/PPT

41 Address Translation, TLB(Translation Lookaside Buffer) 50 minutes R1 BB/PPT

42 Input/output system: programmed I/O 50 minutes R1 BB/PPT

43 DMA(Direct Memory Access)- Arbitration Techniques 50 minutes R1 BB/PPT

44 Interrupts 50 minutes R1 BB/PPT

45 I/O Processors 50 minutes R1 BB/PPT

5
 DOC/LP/01/28.02.02

LP – CS6303
LESSON PLAN
LP Rev. No : 00
Sub Code: CS6303
Date : 20/06/2014
Sub Name: COMPUTER ARCHITECTURE

Branch : BE(CSE) Semester : III Page: 06 of 06

Course Delivery Plan

Week 1 2 3 4 5 6 7 8 9 10 11 12

Unit I I I I I II II II III III III III III III IV IV IV IV IV V V V V V

Outcomes: Upon Completion of the course, the students will be able to

 understand the basic structure and operation of digital computer.

 understand the hardware-software interface.
 familiarize the students with arithmetic and logic unit and implementation of fixed point
 and floating-point arithmetic operations.
 familiarize the students to the concept of pipelining.
 familiarize the students with hierarchical memory system including cache memories and
virtual memory.
 familiarize with different ways of communicating with I/O devices and standard I/O
interfaces.
TEXT BOOK:
1. David A. Patterson and John L. Hennessey, “Computer organization and design’, Morgan
Kauffman / Elsevier, Fifth edition, 2014.
REFERENCES:
1. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer Organisation“,
VI th edition, Mc Graw-Hill Inc, 2012.
2. William Stallings “Computer Organization and Architecture” , Seventh Edition , Pearson
Education, 2006.
3. Vincent P. Heuring, Harry F. Jordan, “Computer System Architecture”, Second Edition,
Pearson Education, 2005.
4. Govindarajalu, “Computer Architecture and Organization, Design Principles and
Applications",first edition, Tata McGraw Hill, New Delhi, 2005.
5. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata Mc Graw
Hill,
1998.
6. http://nptel.ac.in/.
Approved by
Prepared by
Signature

Prof.S.Muthukumar
Name Dr.V.Vidhya
Ms.B.Jayalakshmi

Professor /CS
Designation HOD / CS
Asst.Professor / CS