VLSI Design Assignment 2

1. A store has one express register and three regular ones. It is the store policy that the express
register be open only when two or more of the other registers are busy. Assume that the
Boolean variables A, B, and C reflect the status of each of the regular registers (1 busy, 0 idle).
Design the logic circuit, with A, B, and C as inputs and F as output, to automatically notify the
manager (by setting F = 1) to open the express register. Present two solutions, the first using
only NAND gates, the second using only NOR gates.
2. Consider the logic circuit shown in Fig. 1, with VTO(enhancement) = 1 V, VTO(depletion) = - 3
V, and γ= 0.
(a) Determine the logic function F.
(b) Calculate WL/LL such that VOL does not exceed 0.4 V.
(c) Qualitatively, would WL/LL increase or decrease if the same conditions in (b) are to be
achieved but γ = 0.4 V0.5?

3. Design a two input XOR gate with AOI and OAI and comment on the number of transistors
used in each implementation.
4. Design a 4:1 MUX using transmission gates.
5. Implement F = (AB+CD)’ and find an equivalent CMOS inverter circuit for simultaneous
switching of all inputs, assuming that (W/L)p = 15 for all pMOS transistors and (W/L) = 10 for
all nMOS transistors.