Online estimation of IGBT junction temperature (Tj) using gate-emitter

voltage (Vge) at turn-off

V Sundaramoorthy1, E Bianda1, R Bloch1, I Nistor1, G Knapp2, A Heinemann2

1
ABB Switzerland Ltd, Corporate Research
1
Segelhofstrasse 1 K
1
5405 Baden, Switzerland
2
ABB Switzerland Ltd, Business Unit Power Conversion
2
Austrasse
2
5300 Turgi, Switzerland
Telephone: +41 (0)58 586 7122
Email: vinoth.sundaramoorthy@ch.abb.com
URL:www.abb.com

Keywords
«Device characterization», «Diagnostics», «Estimation technique», «IGBT», «Power semiconductor
device».

Abstract
The paper presents a novel method for online estimation of the junction temperature (Tj) of
semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the
IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend
linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for
estimating the junction temperature even during converter operation – without the need of additional
thermal sensors or complex Rth network models. A measurement circuit was implemented at gate
level to measure the involved time duration and its functionality was demonstrated for different types
of IGBT modules.

Introduction
The junction temperature (Tj) of semiconductor chips in IGBT modules during operation of a
power electronic converter is an important parameter, which provides information on the operating
status of the IGBT module. Information about the thermal cycles of the IGBT modules during
operation could be thus directly available. From this, important information could be extracted e.g.,
prediction and evaluation of the remaining lifetime of IGBT modules. Normally, the junction
temperature of the IGBT modules is measured using techniques such as infra-red camera, mounting a
thermocouple inside the package directly or next to the chip or by measuring the internal gate
resistance of the chip. These techniques either involve direct access to the chip inside the package or
require specially designed IGBT chips & modules [1]. Alternatively, there are also methods reported
to estimate Tj based on complex thermal network models [2-4]. However, these methods are prone to
evaluation errors and do not include the aging effects of modules. Most of the existing methods
presented in the literature are not suitable to determine the Tj in real time or when the converter is in
operation . The chosen technique has to be applicable to a wide range of voltage classes and module
types/suppliers, and should not involve extensive alterations of the gate driver, or the need to use
specially designed packages. This paper introduces a novel approach for determining Tj using a
method, which can be implemented directly at the gate drive level, thus being suitable for use during
converter operation.
The most suitable approach to extract the junction temperature is to focus the attention on
“external” electrical parameters that can be measured at the gate driver level. These are parameters
that can be measured outside the module and thus will not involve modifying the package to introduce
additional sensors (thermal or optical). Electrical characteristics of IGBTs change with Tj of the
device due to their dependence on basic material properties (e.g., electron mobility, carrier lifetime,
intrinsic carrier concentration) [5]. The intrinsic carrier concentration and carrier lifetime increases
with temperature, and the electron mobility decreases with temperature. Although these basic material
characteristics are not easily accessible, they lead to macroscopic changes of electrical parameters
called temperature sensitive electrical parameters (TSEP), which can be measured. The most important
TSEPs are turn-on and turn-off delay times, collector emitter current (Ice), on-state voltage drop (Vce-
on) and gate-emitter voltage (Vge) [6-10]. The criteria considered to select the most important TSEP
were (a) the temperature sensitivity, linearity and degree of error in the measurement technique, (b)
the complexity of the measurement technique, (c) the requirements for the data recording and (d) the
dependence on the external circuit and converter design. Among the most relevant TSEPs, the gate-
emitter voltage (Vge) during the turn-off was found to have good sensitivity and linearity with
temperature, at a feasible level of complexity in terms of measurement and data recording
requirements. It is also independent of the external circuitry and converter design.

In this paper, the temperature variation of gate-emitter voltage during turn-off is explained
along with its physical background. Then, the experimental results are explained to reiterate further
dependencies of Vge, other than temperature. The variation of temperature sensitivity of Vge for
different types of modules is also explained. Then, a circuit to measure the temperature variation of the
Vge is proposed and discussed. Finally, the experimental results of the modules measured using the
proposed circuit are illustrated.

Physical background
A typical waveform of Vge during IGBT turn-off is shown in figure 1. It can be seen that for a
temperature span of 75 oC, a reproducible shift in the Vge waveform can be seen right after the end
phase of the Miller plateau. This shift can be detected by using a time counter triggered between the
first falling edge and second falling edge of the Vge-off curve. Such a circuit can be implemented at
the PCB level and integrated in the gate unit.

15
1 00 A -6 0 0 V -2 5 C
1 00 A -6 0 0 V -5 0 C
10 1 00 A -6 0 0 V -7 5 C
1 00 A -6 0 0 V -1 0 0C
Vge_off (V)

5 Trigger 1
Trigger 2
0
Miller Plateau (time difference)
-5

- 10
Δt = f(Tj)
38.50 3 8 .7 5 39.00 3 9 .2 5 39.50 39.75
t im e O F F (μ s )
Figure 1: Vge waveform at different temperatures for Module A measured at 600 V, 100 A switching
condition

Possible factors inducing this shift can be the temperature dependency of the internal gate
resistor of the IGBT chips, changes in the mobility of electrons in the MOS channel of the IGBT as a
function of temperature, or changes in the internal parasitic capacitances of the chip. To understand
the physical mechanism, a single IGBT chip was analyzed at different temperatures using TCAD
simulation. The charge concentration inside the IGBT chip during turn-off process was studied. The
cross-section of the IGBT chip after 1 µs during the turning-off process depicting the distribution of
holes is shown in figure 2 for temperatures, 350 K, 400 K and 450 K. It can be seen that the holes are
present for a shorter depth at lower temperatures, i.e., the holes are present for a shorter depth inside
the drift layer of the IGBT chip at 350 K than at 400 K and 450 K. Hence, the space charge region
(SCR) expands to a larger depth at 350 K when compared at 400 K and 450 K. This can be clearly
seen from figures 3 (a) and (b), where the space region depth and the holes distribution inside the chip
are shown as a function the drift layer depth. The space charge expands up to a depth of ~170 µm,
~160 µm, ~150 µm at 350 K, 400 K, 450 K, respectively (figure 3 (a)), and hence the holes are
present only from a depth of ~170 µm, ~160 µm, ~150 µm in the drift layer at 350 K, 400 K, 450 K,
respectively (figure 3 (b)).

SCR SCR SCR

Holes Holes
Holes

(a) (b) (c)

Figure 2: Cross section of the IGBT showing the distribution of hole density within the IGBT chip at
1µs after turn-off for different temperatures, (a) 350 K, (b) 400 K, (c) 450 K.

1.0x1014 5x1015

450 K 4x1015 450 K

H o le d e n s it y (c m ^ -3 )

8.0x1013
400 K 400 K
S p a c e C h a r g e (c m ^ -2 )

350 K 350 K
6.0x1013 3x1015

4.0x1013 2x1015

2.0x1013 1x1015

0.0 0
100 120
160 180 200 220 240 140 100
160 120180 140
200
Y (um) Y (um)
Figure 3 (a): The expansion of the space charge Figure 3 (b): The distribution of hole density
region within the IGBT chip at 1µs after turn-off within the IGBT chip at 1µs after turn-off for
for different temperatures at 350 K, 400 K and different temperatures at 350 K, 400 K and 450
450 K. K.
 This means that at 350 K, the plasma (mixture of mobile electrons and holes) is present only
between the depth of 170 µm up to the end of the n- drift layer, whereas the plasma is present from the
depth of 160 µm and 150 µm in the n- drift layer at 400 K and 450 K, respectively. The amount of
plasma present in the IGBT increases with higher temperatures and hence, more charge has to be
removed during the turn-off process before blocking voltage can be supported again. The plasma
volume inside the chip increases at higher temperatures, due to the increase of intrinsic carrier
concentration and the carrier lifetime with temperature. Therefore, at a given time during the turn-off
process, the volume of remaining plasma inside the chip is higher at higher temperatures and this
causes the space charge region to expand less at 450 K (see figure 2 (c) and figure 3 (a)).
Due to the higher volume of plasma in the drift layer at higher temperatures, the depletion
capacitance (Cdep) of the drift layer is also high, as seen per equation (1) [6],
ε .e0 . N A . N D
Cdep = A. (1)
2.Vdc .(N A + N D )
where NA and ND represents the acceptor and donor doping concentration respectively, is the
dielectric constant, e0 is the unit charge, Vdc is the DC-link voltage and A is the surface area of the
capacitance. It can be seen from the equation (1) that at higher temperatures, as the donor and acceptor
concentration (plasma) increases, the depletion capacitance also increases. The increase in the
depletion capacitance at higher temperatures in turn causes the Miller capacitance or the gate-collector
capacitance (CGC) to increase, as the Miller capacitance is the combination of the gate-oxide
capacitance (Cox) and the depletion capacitance (Cdep) of the drift layer. Higher Miller capacitance in
turn gives rise to the larger Miller plateau width at higher temperatures, according to equation (2) [11],
RG .CGC .(Vdc − Von )
t diff = (2)
⎛ IL ⎞
⎜⎜ + Vth ⎟⎟
⎝ gm ⎠
where tdiff is the duration of the Miller plateau, RG is the gate resistance (internal + external), CGC is the
gate-collector capacitance (Miller capacitance), Vdc is the DC-link voltage, Von is the on-state voltage,
IL is the load current, gm is the transconductance, and Vth is the threshold voltage.
It can be seen from equation (2) that the duration of the Miller plateau is directly proportional
to CGC, which is the dominating factor in tdiff. The effect of temperature variation on other factors like
Von is negligible, as VDC is much higher than Von. The temperature variation of (IL/ gm) and Vth partly
counteract each other. Also RG would increase with temperature, as electron mobility decreases with
temperature, thereby increasing the internal gate resistance. Hence, the duration of the Miller plateau
(tdiff) increases at higher temperatures due to the temperature variation of CGC and RG. Therefore, the
duration of the Miller plateau in the Vge waveform can be used as a parameter to estimate the junction
temperature of the IGBT chip.
From the estimated junction temperature of the IGBT chip, the thermal stress and thermal
load cycle to which the chip is currently subjected, can be extracted. Using this information, the
thermal cycles that has already been experienced by the IGBT can be counted using a suitable
algorithm [12-14]. A rain flow algorithm is one such method to count the cycles from the mission
profile [15]. Then the thermal cycle count is compared with the nominal cycle count of the IGBT,
which is acquired by suitable power cycling tests together with a lifetime thermal model [16]. From
this data, the consumed lifetime and hence, the remaining lifetime of the IGBT can be estimated.
Hence, the estimated Tj of the IGBT chip can be used as a diagnostic tool to predict the imminent
failure of IGBT modules.

Experimental results
The time difference (tdiff i.e., the time duration between the first and second falling edge of the
Miller plateau, thus the “width of the Miller plateau”) as a function of the measurement temperature is
shown in figure 4. It can be seen that tdiff varies linearly with the measurement temperature. A
temperature sensitivity (change in time delay) of 1.2 ns/oC has been found for this module when
measured at 600 V, 100 A.
Furthermore it was found that the width of the Miller plateau does not depend on the
temperature only, but also on the collector current, as well as on the DC-link voltage. This is
illustrated in figure 5. From this curve, the sensitivity of the Vge curve (change in time delay) with
respect to current was found to be between 0.12 ns/A and 0.18 ns/A, depending on the DC-link voltage
and temperature. The sensitivity of the Vge curve with respect to DC-link voltage decreases from 0.17
ns/V to 0.11 ns/V for currents varying from 100 A to 400 A, respectively. These dependencies on
current and voltage, if not taken into account, can distort the temperature estimation significantly.
Therefore precise measurements of the turn-off collector current and DC-link voltage are required,
coupled with a fast electronic circuit for the measurement of time differences. Time variations below 1
ns can be detected with modern electronics. Therefore, the proposed technique has the potential to
deliver information on chip temperature with a precision of around ±1 oC (considering a temperature
sensitivity of 1.2 ns/oC), at a known current and voltage level.

780 660

Time difference 600 V, 25 C

760 640 300 V, 25 C

Time difference (ns)

T im e d iffe ren ce (n s)

740
620
1.2 ns/C
720
600

700
580

680
560
660
540
20 30 40 50 60 70 80 90 100 100 150 200 250 300 350 400
Temperature (C) Current (A)
Figure 4: Time difference between the first Figure 5: Time difference between the first
falling edge and second falling edge of Vge falling edge and second falling edge of Vge as a
waveform at 600 V, 100 A switching condition function of current and DC link voltage at 25 oC
(Module A) (Module A)

Table I: Variation of sensitivity for different types of modules from various manufacturers

Module rating Sensitivity (ns/°C)

Module A - 1.2kV 300A 3.4 @ 600V, 100 A

Module B - 1.2kV 400A 1.48 @ 600V, 100 A
Module C - 1.2kV 300A 1.15 @ 600V, 100 A
Module D - 1.2kV 200 A 1.32 @ 600V, 100 A
Module E - 1.2kV 400A 2.4 @ 600V, 100 A
Module F - 1.2kV 300A 2.13 @ 600V, 100 A
Module G - 3.3kV 1500A 0.8 @ 1800V, 1500 A
Module H - 3.3kV 1500A 1 @ 1800V, 1500 A
Module I - 6.5kV 400A 1.4 @ 30V, 200 A

The variation of the sensitivity for modules from different manufacturers was also
investigated. The sensitivity of tdiff with chip temperature changes largely for modules with same
ratings from different manufacturers, due to different internal chip structures (comparing modules A
and C in table 1). Also, the sensitivity of tdiff with chip temperature changes for modules with different
ratings from same manufacturers (comparing modules A and B in table 1). It was found as well that
the temperature sensitivity of tdiff also changes significantly for different generations of the module
(comparing modules C and F in table 1). It was also found that the sensitivity of tdiff with respect to
the DC-link voltage and the turn-off collector current changes for different types of module.
Hence, to include all these dependencies and reach a good precision of the temperature
estimation, a look-up table is required. The look-up table can be created prior to mounting the IGBT
module in the converter, in a standard double pulse tester. Here, the described time difference in the
Vge waveform is acquired for different test conditions (e.g. collector currents and DC-link voltages)
for a given module at many chip temperatures. This look-up table with required algorithms can then be
uploaded directly on the gate drive and will be used to estimate the Tj during the converter operation.

Measurement circuit implementation

A measurement circuit to measure the width of the Miller plateau was designed and connected
to the gate drive unit. Goal of the circuit is to generate two pulses from the stepped falling edges of the
Vge signal. The circuit generates a first pulse at trigger 1 (see figure 1) and a second pulse again at
trigger 2 (see figure 1) on the falling edges of the Vge signal. The block diagram of the logic circuit is
shown in figure 6. The whole circuits consist of 3 distinct parts, namely the differential stage, the
comparator and the signal amplitude detector.

VGE
Differential stage Comparator

Signal
amplitude
detector

Figure 6: Block diagram of the Vge measurement logic circuit

The detailed picture of the implemented circuit is shown in figure 7. The functionality of the
three blocks is explained briefly.
Differential stage: The differential stage is the heart of the circuit. With a simple C-R
network, a differential transformation of the stepped input signal is generated. Thus each negative
flank of the input signal generates its own single negative pulse. The capacitor C4 makes the
differentiation. The resistors R11 and R13 are the output load for C4. Since, a unipolar supply voltage
was used; the circuit internal zero was set to half of the supply voltage with the resistors R11 and R13.
The capacitor C6 is used to connect resistor R11 HF right to ground ‘GND’. The resistor R12 limits
the output current of this circuit. The pulse amplitude depends on the input signal rise time. The time
difference between the two pulses is the wanted parameter, tdiff .
Comparator stage: In order to correctly transfer both the analog pulse of the differentiator
stage to a digital counter, it is necessary to convert the analog pulses to a logic form that is compatible
to the counter input. To do this, a comparator with a small hysteresis is needed. The comparator circuit
uses a 7 ns, rail to rail comparator. The input signal from differential stage goes to the negative input
of comparator U3, and hence it is inverted as the output. The reference voltage is connected to the
positive input of U3 through the resistor R20. The reference switch voltage for the comparator is set to
the half of the differential stage output signal. The reference voltage is at the middle point of the slope
for both the falling edges before and after the Miller plateau. Since the output amplitude of the
differential stage depends on the rise time, this signal amplitude will change with many parameters.
For this reason, a fix reference voltage is not feasible. Hence, a variable reference voltage was used,
which depends on the output amplitude of the differentiator stage. This voltage is generated by the
signal amplitude detector. The resistors R18, R19, R20, and R21 make a voltage divider for the
reference voltage. Thus the reference voltage is nearly half of the output of the signal amplitude
detector stage. The resistors R18 and R21 set the working voltage to half of the supply voltage. The
resistor R19 creates the necessary hysteresis. Capacitor C17 helps to speed up the switching of the
comparator output.

Signal
Amplitude
Detector

Differential
Stage

Comparator

Figure 7: Detailed picture of the Vge measurement circuit

Signal amplitude detector stage: In order to set a correct reference switch value for the
comparator, a negative pulse detector was used to measure the amplitude of the differentiator stage
output signal. To reset this detector, a time constant has been used to discharge the memory
capacitance. The output voltage of this stage is divided by two and forwarded to the comparator as
reference voltage. This circuit uses a 250 MHz, rail to rail operational amplifier. The amplifier U2A
with the diode V7 and the output buffer U2B make a negative peak detector. The amplifier U2A drives
the diode V7 negative as long as the voltage of the output buffer U2B is not equal to the value of the
input voltage. As soon as the input voltage goes positive, the diode V7 disconnects the output of the
amplifier U2A from the capacitors C5 and C7. At this point, the maximum negative value is stored in
capacitors C5 and C7. This voltage is buffered with U2B, then divided by two and forwarded as
reference voltage to the comparator. Without signal, the capacitors C5 and C7 would be discharged to
(V+/2) V with R10 and R14. The discharge time constant is 1.5 ms, and this is slow enough for
converters switching at 4 kHz and higher. Both capacitors C5 and C7 are needed in order to have a fast
start-up at power on. The diode V8 prevents the saturation of amplifier U2A in the store state.
The total cost of implementation of this circuit in real converters would depend on the
complexity involved with the interfacing circuit. The cost of the measurement circuit itself is cheap, as
it uses only operational amplifiers and simple passive components. To keep the costs low, it is
recommended to place the Tj measurement circuit on the gate drive unit for simplified interfacing.
Measurement circuit results
The output of the Vge measurement logic circuit is shown in figure 8. It can be clearly seen
that the first pulse is generated at the beginning of the Miller plateau and the second pulse is generated
after the second falling edge of the Miller plateau. A counter calculates the time difference between
the rising edge of these two pulses and indicates the width of the Miller plateau. The time difference
between these two pulses varies with temperature and hence, allows to derive Tj of the IGBT chips as
shown earlier. Once the algorithm with the required look-up table is implemented, the information
about the junction temperature of the IGBT module can be extracted.
The measurement circuit was used to measure the width of the Miller plateau while the IGBT
module was heated by changing the base-plate temperature. Modules from different manufacturers
have been measured. The measurement of time difference for low voltage modules A –D is shown in
figure 9. The measurement of time difference for medium voltage modules G - H and high voltage
module I is shown in figure 10. It can be seen that the time difference between the two pulses is linear
with temperature for all the measured modules. The temperature sensitivity ranges from 0.8 ns/oC to
3.35 ns/oC, depending on the module type. The measurement circuit was able to measure the time
difference for all the tested modules. Hence, the Tj of the IGBT module can be estimated online using
this measurement circuit along with the appropriate algorithm and look-up table.

Figure 8: Output of the Vge measurement circuit implemented to generate two pulses, one at the
beginning and the second at the end of the Miller plateau.
1600
Module A, 1.2kV / 300A
Module B, 1.2kV / 400A
1400 Module C, 1.2kV / 300A 3.35 ns/oC
Module D, 1.2kV / 200A
Time Difference (ns)

1200 1.22 ns/oC

1000 1.1 ns/oC

800 1.32 ns/oC

600

0 20 40 60 80 100 120
Temperature (C)
Figure 9: Time difference between the two pulses measured with the circuit for low voltage modules
A-D (All modules measured at 600 V, 100 A, except Module B which was measured at 600V, 200A)
 1800
0.8 ns/C
1700
Time Difference (ns)
1600 1.42 ns/C
1500
Module G, 3.3 kV, 1.5 kA
Module H, 3.3 kV, 1.5 kA
1400 Module I, 6.5 kV, 400 A

1300
1 ns/C
1200

1100
0 20 40 60 80 100 120 140
Temperature (C)
Figure 10: Time difference between the two pulses measured with the circuit for medium voltage
modules G & H (measured at 1800 V, 1500 A condition) and high voltage module I (measured at
3290 V, 200 A condition).

Conclusion
We have shown that the novel technique proposed in this paper can be used to estimate Tj of
any IGBT module type during converter operation. The proposed method does not need any
modifications of the module, and does not use any complex thermal models. The width of the Miller
plateau in the Vge curve was found to vary with the measurement temperature and thus can be used to
measure the junction temperature of the IGBT. The temperature sensitivity of Vge curve to both the
collector current and the DC-link voltages implicates the need to add compensating measures.
A logic circuit was designed to measure the time duration or the width of the Miller plateau.
Many types of modules were measured using the logic circuit and the time duration was accurately
measured corresponding to the applied temperature. Typical temperature sensitivity varied from 0.8
ns/°C to 3.5 ns/°C for different types of modules measured at various test conditions. Using this
technique, look-up tables can be generated and bench marked for each module type with the values of
time duration, current, DC-link voltage and the corresponding temperature. From the created look-up
tables, the junction temperature of the IGBT at a known test condition can be estimated directly using
the Vge measurement circuit and the appropriate algorithm. This method has the potential to
significantly boost the diagnostics capabilities of the PE converters during operation.

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