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D
Digital E
Electron
nics

State
S E
Equatio
ons & Diagra
D ams
A statte euqtion is an algeebraic exprression thaat specifiess the
condittion for a flip-flop sttate transittion. The left
l side off the
equatio
on denotess the next state of th
he flip-flop
p and the right
r

m
side of the equattion is a Boolean exp
pression that specifiess the

co
nt state an
presen nd input co
onditions tthat make the next state
equal to
t 1.

n.
′
1 ; 1

io
State Table:
T

at
The State Table consists off four sectiions labeled present sstate, inputt, next state,
uc
and ouutput. The present staate column
n shows thee states of the flip-flo
ops and
at any given timee . The neext state co
olumn show
ws the statees of the fliip-flops on
ne
ed

clock period lateer at time 1, for given valuee of . Th

he output section
s givees
hi

the value of fo
or each present state. B
Both the next
n state an
nd output sections wiill
have tw
wo sub collumns, onee for 0 and the otther for 1.
ks

Prresent Next Staate (NS) Ou

utput
a

S
State
.s

(PS)
(
w
w

0 0 0 0 0 1 0 0
w

0 1 1 1 0 1 0 0

1 0 1 0 0 0 0 1

1 1 1 0 1 1 0 0

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In general, a sequential circuit with flip-flops, and input variables, will have
2 rows, one for each state. The next state and ouput columns will have 2
columns one for each input combination.

State Diagram:

The information available in a State Table can be represented graphically in a

m
state diagram. In this, a state is represented by a circle, and the transition between
states is indicated by directed lines connecting the circles. The state diagram

co
provides the same information as the State Table. The binary number inside each
circle represent the state of the flip-flops. The directed lines are labeled with two

n.
binary numbers separated by a slash. The input value during the present state is

io
labeled first and th number after the slash gives the output during the present

at
state. A directed line connecting a circle with itself indicates that no change of
state occurs.
uc
ed
hi
a ks
.s
w

Flip-flop input functions:

w

The logic diagram of a sequential circuit consists of flip-flops and gates. The
w

knowledge of the type of flip-flops and a list of the Boolean functions of the
combinational circuit provide all the information needed to draw the logic
diagram. The part of the combinational circuit that generates external outputs is
described algebraically by the circuit output functions. The part of the circuit that

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generaates the inp
puts to flip
p-flops are described algebraicallly by a sett of Booleaan
functio
ons called flip-flop
f inp
put functio
ons.

m
co
n.
The fliip-flop input function
ns for the aabove circuuit are

io
′ ′ ′
;

at
uc
State Diagrams
D s and Statee Tables off flip-flopss:

SR Fliip-flop:
ed
hi
a ks
.s
w

P
Present N
Next Statee (NS)
State
w

(PS)
w

0 0 0 1

1 1 0 1

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JK Fliip-flop:

m
P
Present N
Next Statee (NS)
State

co
(PS)

n.
0 0 0 1 1

io
1 1 0 1 1

at
uc
D Flip
p-flop:
ed
hi
a ks
.s

Next Sttate
w

P
Present
State (NS))
w

(PS)
w

0 0 1

1 0 1

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T Flip
p-flop:

m
co
Next Sttate

n.
P
Present
State (NS))

io
(PS)

at
0 0 1
uc
1 1 0
ed

State Reduction
R and
a Assign
nment:
hi

Any dessign processs must con

nsider the problem
p off minimizin
ng the costt of the final
ks

circuit. The
T two most
m obviouus cost reduuctions are reductionss in the num
mber of flip
p-
flops an
nd the num
mber of gaates. The reduction
r o the num
of mber of flip
p-flops in a
a
.s

sequentiial circuit is
i referred to as the sstate reduction probleem. Since flip-flop
ps
producee 2 states, a reductio
on in the number of states
s may result in a reduction in
i
w

the num
mber of flip-flops.
w

“ Two states
s are saaid to be equivalent iff, for they give exactlly the samee output an
nd
w

send thee circuit eitther to the same state or to an eqquivalent state.” Wheen two statees
are equivvalent, onee of them can
c be remo
oved.

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Example:

m
co
n.
io
at
uc
State Table for the given state diagram:
ed
hi

Next State
Output
ks

PS (NS)
a
.s

a a b 0 0
w

b c d 0 0
w

c a d 0 0
d e f 0 1
w

e a f 0 1
f g f 0 1
g a f 0 1

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In the above State Table, e and g are equivalent and hence g can be removed and in
place of g, e is placed. Then, again we look for equivalent states and we see that d
and f are equivalent. Hence, the reduced Table will consists of 5 states and requires
3 flip-flops again.

Next State
Output
PS (NS)

m
co
a a b 0 0

n.
b c d 0 0
c a d 0 0

io
d e d 0 1

at
e a d 0 1
uc
State Assignment:
ed

State assignment procedures are concerned with methods for assigning binary
values to states in such a way as to reduce the cost of the combinational circuit that
hi

drives the flip-flops.

a ks

Three possible binary State Assignments

.s

State Assignment 1 Assignment 2 Assignment 3

w

a 001 000 000

w

b 010 010 100

w

c 011 011 010

d 100 101 101

e 101 111 111

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Reduced State Table with Binary Assignment 1

Next State Output

Present State
x=0 x=1 x=0 x=1

001 001 010 0 0

010 011 100 0 0

m
011 001 100 0 0

co
100 101 100 0 1

n.
101 001 100 0 1

io
at
uc
ed
hi
a ks
.s
w
w
w

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