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DIGITAL LOGIC
FLIP FLOP
 WHAT IS FLIP-
FLOP

It is a sequential circuits which has two states and

can be used to store state information:

It has 4 types:
• S-R FLIPFLOPS
• D FLIPFLOPS
• JK FLIPFLOPS
• T FLIPFLOPS
SR FLIPFLOP
(SET/RESET)

The SR flip flop stands for "Set-Reset" flip flop. The reset
input is used to get back the flip flop to its original state
from the current state with an output 'Q'. This output
depends on the set and reset conditions, which is either
at the logic level "0" or "1". It has two outputs, the main
output 'Q' and the complements of the main output ' Q' '.
The SR Flip-Flop is a storage element with only one bit.
SR FLIPFLOP The circuit is similar to the SR latch except for the
clock signal and two AND gates. The SR flip-flop
CIRCUIT circuit responds to the positive edge of the clock
pulse to the inputs S and R.
DIAGRAM
SYMBOL OF SR FLIP-FLOP

SR FLIP-FLOP
TRUTH TABLE
'S' and 'R' are the two inputs to the SR flip-flop. The Qn represents the state of the SR
flip-flop before applying the inputs, and Qn+1 represents the state of the SR flip-flop as
output. The truth table for SR flip-flop is shown below:
CHARACTERISTIC EQUATION FOR
SR FLIP-FLOP
The characteristic equation is an algebraic expression for
the characteristic table's binary information. It specifies
the value of the next state of a flip-flop in terms of its
present state and present excitation. To obtain the
characteristic equation of SR flip-flop, the K-map for the
next state Qn+1 in terms of present state and inputs is
shown as:
EXCITATION TABLE
OF SR FLIP-FLOP
The truth table of flip-flop refers to the operation
characteristic of the flip-flop. Still, in the designing of
sequential circuits, we often face situations where the
present state and the next state of the flip-flop are
specified, and we must determine the input conditions
that must exist in order for the intended output
condition to occur.
The excitation table of SR flip-flop lists the present state,
and the next state and the excitation table of SR flip-flop
indicate the excitations required to take the flip-flop
from the present state to the next state. The excitation
table of SR flip-flops is as follows:
JK FLIPFLOPS
WHAT IS JK
FLIPFLOP
JK Flip Flop is one of the most used
flip-flops in digital circuits. The
universal flip flop has two inputs, 'J'
and 'K.' The JK Flip Flop is a gated SR
Flip-Flop with a clock input circuitry
that prevents the illegal or invalid
output when both inputs S and R are
equal to logic level "1."

JK flip flop full form is Jack Kilby flip

flop. It is named after its inventor Jack
Kilby. They invented the integrated
circuit in 1958.
 RIMBERIO CO

JK FLIP-FLOP
CIRCUIT DIAGRAM
The logic diagram of JK Flip-Flop
with data input J and K ed with O
and Q respectively to obtain S and
R inputs that is:
RIMBERIO CO

JK Flip-Flop Truth Table

The JK Flip-Flop truth table has the hold state,
reset state, set state, and toggle state. As this is a
refinement of SR flip flop, the truth table of SR
flip flop is refined to make the truth table of jk
flip flop. The truth table of the JK Flip-Flop has
two inputs, J and K, Qn denotes the current state,
and Qn+1 denotes the next state in the table
given below:
 Characteristic Table of JK Flip-
Flop

The characteristic table of the JK Flip-Flop has the hold

state, reset state, set state, and toggle state. The
characteristic table has the input J and K, Qn and Qn+1
denote the current state denotes the next state in the
characteristic table given below:

JK Flip-Flop Characteristic
Equation
The characteristic equation of the JK Flip-Flop from
the above characteristic table that has the hold state,
reset state, set state, and toggle state is as follows
using the three variable k-map. In the k-map, the
column K'Qn is common, and the JQ' is common. So,
the characteristic equation is:
RIMBERIO CO

EXCITATION TABLE OF JK
FLIP-FLOP

The excitation table of the JK Flip-Flop has

the current state denoted by Qn, and the
next state is denoted Qn+1. It has the J
and K inputs for each transition in the
excitation table of the JK Flip-Flop are as
follows:
 RIMBERIO CO

T FLIPFLOP

The toggle, or T, flip-flop is a two-input flip-

flop. The inputs are the toggle (T) input and a
clock (CLK) input. If the toggle input is HIGH,
the T flip-flop changes state (toggles) when
the clock signal is applied. If the toggle input
is LOW, the T flip-flop holds the previous
state.
RIMBERIO CO

T FLIP-FLOP CIRCUIT
DIAGRAM

With the little modification, the JK

flip-flop can be used as a T flip-
flop.
POSITIVE SYMBOL OF T FLIP-FLOP

T FLIP-FLOP TRUTH
TABLE
'The symbol which is shown above is the symbol of the positive edge triggered flip-flop.
The triangle in the symbol indicates that, the flip-flop responds to the input only at the
rising edge of the clock. Similarly, the symbol of the negative edge triggered ? T flip-flop
is next page.
NEGATIVE SYMBOL OF T FLIP-FLOP

T FLIP-FLOP TRUTH
TABLE
 Characteristic Table of T Flip-
Flop
The characteristic equation of the flip-flop is the algebraic
representation of the next state of the Flip-Flop (Qn+1) in terms of
the present state (Qn) and the current input (T).
That means, here the input variables are Qn and T, while the output
is Qn+1 .
From the truth table, as you can see, the output Q n+1 is 1 for two
different input combination of Qn and T.

T Flip-Flop Characteristic
Equation
Let’s write down these two input combinations in the
K-map, and let’s try to simplify the Boolean
expression. From the K-map, the two minterms are T
Qn ‘ and T ‘ Qn . That means the characteristic
equation of the T flip-flop is
 EXCITATION TABLE OF T
FLIP-FLOP

Ihe excitation table of the flip-flop shows the

required excitation to the flip-flop, or the required
input to the flip-flop, to go from the given state to
the next particular state. For the T input, when T = 0
then the flip-flop remains in the same state and
when T = 1 then the output of the flip-flop toggles at
every clock pulse. The excitation table of the T flip-
flop is shown below.
 D FLIP-FLOP

The D flip flop is the most important flip flop from other clocked types. It
ensures that at the same time, both the inputs, i.e., S and R, are never
equal to 1. The Delay flip-flop is designed using a gated SR flip-flop with
an inverter connected between the inputs allowing for a single input
D(Data).

This single data input, which is labeled as "D" used in place of the "Set"
input and for the complementary "Reset" input, the inverter is used. Thus,
the level-sensitive D-type or D flip flop is constructed from a level-
sensitive SR flip flop.
CIRCUIT DIAGRAM
We know that the SR flip-flop requires two
inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an
inverter, we can set and reset the outputs
with only one input as now the two input
signals complement each other. In SR flip
flop, when both the inputs are 0, that state
is no longer possible. It is an ambiguity
that is removed by the complement in D-
flip flop.
 SYMBOL OF T FLIP-FLOP T FLIP-FLOP
TRUTH TABLE

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to 1, the flip
flop would be set, and when it is set to 0, the flip flop would change and become reset. However, this would
be pointless since the output of the flip flop would always change on every pulse applied to this data input.
The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip flop's latching
circuitry. When the clock input is set to true, the D input condition is only copied to the output Q. This forms
the basis of another sequential device referred to as D Flip Flop.
When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1. So it will not
change the state and store the data present on its output before the clock transition occurred. In simple
words, the output is "latched" at either 0 or 1.
CHARACTERISTIC
AND K MAPS
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