AD2000User'sManual

ffi RealTimeDevices,
Inc.
" Accessing
theAnalog World',"

ISO9001 and AS9100 Certified

 An?noo
L .l-Lt -t \t \, \,

User'sManual

ffi
REALTIMEDEVICES,INC.
Drive
820 NorthUniversity
PostOfficeBox906
StateCollege,Pennsylvania16804
Phone: (814')234-8087
FAX:(814)234-5218
 Publishedby
RealTime Devices,Inc.
820 N. University Dr.
P.O.Box 906
StateCollege,PA 16804

Copyright @ 1990by Real Time Devices,Inc.

All rights reserved

Printedin U.S.A.

Rev.B 9241
 TABLE OF CONTENTS

Page
INTRODUCTION
How to Use This Manual....... .................i-2
When You Need Help. .........i-2

CHAPTER I - QUrCK START-GETTTNG YOUR AD2000 RUNNTNG

What ComesWith Your AD2000............... ................1-l
The Hardware.............. ...........1-l
Functions You CanSet............. ....'.....l-1
Setting the Base I/O Address .............1-2
InstallingttreAD2000in YourComputer.... ................... 14
TheSoftware ....... 16
D e m oD i s k . . . . . . . . . . . ..........16
Backing Up YourDisk........... ............. 1{
InitializingYour AD2000 ........l:7
Selectingan Analog Input Channe1................ .............1-8
Settingthe Input Gain........... ................1-9
Takingan A/D Reading...... ....1-10

CHAPTER 2 - FUNCTIONAL DESCRIPTION

Analog-to-DigitalConversionCircuitry............... ........2-I
Multiplexers................. .....................2'l
GainConrolCircuitry..... ...................2-2
SampleandHoldCircuitry..... ..............2-2
AID Converter .................2-2
Programmable
Peripherallnterface...... .........2-3
IntervalTimer(PIT)
Programmable .............2-3

CHAPTER 3 _ JUMPER SETTINGS

S1- AnalogInputSignalTypeDIP Switch.. ................3-2
P2- BaseVO AddressHeaderConnector.... ...................
3-2
P3 * ProgrammableIntervalTimer (PIT) VO HeaderConnector.... .......................3-2

P4,P5,andP7 - IntemrptHeaderConnectors.. ..............34

P4- EXTINTandPPIINTRAIntemrpts.... ............3-5
P5 - PIT Output Interrupts.... .........3-5
P7 - A/D End-of-Convert (EOC) Interrupt...... .......................3-5
P6- End-of-Convert(EOC)MonitorHeaderConnector .....................36
-
P9 AID Converter VoltageRangeHeaderConnector.... ...................36
 Page
CHAPTER 4 - PROGRAMMING YOUR AD2OOO
Selectingan Analog Input Channe1................ .............4-1
Settingthe Input Gain........... '...............4-1
Takingan A/D Reading...... .....4-1
Programmingthe Programmable PeripheralInterface................ .......4-1
Programming theProgrammableInterval
Timer......... ......4'2
lntemrpts
Ilardware ............'....4-3
(EOC)Signa1.........
A/D End-of-Convert .................4-3
PPIIntemrps ..................4-3
PITIntemrps ..................4-3

CHAPTER 5 - CALIBRATION PROCEDURES

RequiredEquipment,............. ..................'..
5-1
A/D Catibration.............. ..'....5-1
UnipolarCalibration.. .......5-2
BipolarCalibnation.. .........5-2
GainCircuiry Calibration .......5-3

APPENDIX A - AD2000 Specifications ...........A-l

APPENDIX B - Connector Pin Assignments................. .....81
APPENDIX C - ComponentData Sheets................ ............C-1
APPENDIX D - Configuring the AD2000 for SIGNAL*MATH ..........D-l
APPENDIX E - Configuring the AD2000 for ATLANTIS....... ............E-l
A P P E N D I XF - W a r r a n t y . . . . . . . . . . . ......F-l

tl
 LTSTOF ILLUSTRATIONS

Figure Page
i-1 Typical LaboratorySetup.......... ......i-l
1-1 AD2000 Board Layout........ ...........1-2
L-2 BaseI/O AddresHeaderConnectff,I2 .................14
1-3 AID Conversion WordFormat........ ....................1-10
2-l AD2000FunctionalBlock Diagram ....2-l
2-2 EOC Timing Diagram. ..................2-z
3-1 AD2000 Board Layout........ ...........3-l
3-2 D I P S w i t c h5 1 . . . . . . . . . . . . . . .................32
3-3 PIT VO HeaderConnector I{l ............3-3
34 PlTFunctionalBlockDiagram ..........34
3-5 IntemrptHeaderConnecorP4 ...........3-5
34 IntemrptHeaderConnecorP5 .. ....... . . 3-5
3-7 InterruptHeaderConnectorPT ...........3-6
3-8 EOCMonior Header Connector P6.............. ........36
3-9 AID ConverterVoltageRangeHeaderConnectorP9 .................. 3-6
4-r PPIModeDefinitionFormat........ .....4-2
5-1 AD2000 Board Layout........ ...........5-1

,lt
iv
 LIST OF TABLES

Table Page
1-1 AD2000BoardFunctions andSettings ..................1-3
t-2 AD2000VO Map...... .... 1-5
5-1 A/D ConverterBit Weights ...............5-3
5-2 A/D ConverterReadingsfor GainCalibrarion.. ....... 5-3
INTRODUCTION
This manualshowsyou how to operateandprovidestechnicaldatafor RealTime Devices'AD2000 multifunctiondata
acquisitionboard.The AD2000features12-bithigh-speed multichanneldifferentialor single-ended analog-o-digital
conversion.This versatileinterfaceallows your IBM PCIKT/AT or compatible computer to effectively operatein the
real-timeenvironment of data acquisitionand controlto and
sense generate
analog and digital Figure
signals. i-l shows
a typical laboraory setup using a PC for datacollection.

0N
rU0SKSrnrl
[RSORnT0RT
llflf,OtltflRt tBMPCor sIrTUf nE
CompEtible

S l g n a lc o n d l t l o n l n gD s c g u i s l t l o nd, o t a r e d u c t l o n ,
grdphlcs,onalgsls,conlrol, data storsge

RUTOHRTION
L R BOERTORT

Fig. i-1 - Typical LaboratorySetup

The AD2000 featuresa high-resolution(12-bit) analog-to-digitaland converter,digital VO, and timer/countersthat

provide flexibility for many applications.Its six-layer construction,including sep:uatepower and ground planes,
enhances boardperformanceandlow-noisecharacteristics. It plugsdirectly into anyunusedexpansionslot (shortor full-
size)in the computer.All externalI/O connections,includingPC bus-sourcedpower,areaccessibleat therearpanelof
the computerwhen the boardis installed.
Severalof ttreAD2000's functionscanbe readily adaptedfor your specificrequirements.Throughprogrammingand/
or jumper or switch settingsmadeon the board,you can:
. Selectthe baseVO address,
. Choose8 differential or 16 single-endedanaloginput channels,
. Selectthe activechannel,
. Selectthe channelgain,
. Selectthe analoginput voltagerangeandpolarity,
. Conrol 16TTL/CMOS-compatible digital VO lines,
. Control three l6-bit, 8 MHz timer/countercircuits (theprogrammableinterval timer),
. Monitor theA/D conversionusingtheend-of-convert (EOC)signal,
. Generateintemrptsignals.
Many of these functions are set up at the factory, basedon typical data collection requirementsand customer
specificationswhenordering.Therefore,you cansuccessfullyinstall andrun theAD2000 with minimal understanding
aboutchangingandcontrolling them.On the otherhand,you may want to understandeverythingahut your boad so
that you caneffectively useeachfeature.With this in mind, this manualprovidesbasicinformationto get theboardup
andrunning,aswell asdetailedinformationfor a full understanding of eachfunction.

i-1
How to UseThis Manual
Thismanualis designedto helpyouinstallandgetyourAD2000runningquickly,while alsoincludingsufficientdetail
abouteachboardfunction. Begin by readingChapterI in ordero useyour boardasquickly aspossible.This chapter
andtheaccompanyingdemonstration softwareincludedwithyourAD2000packagewillallow youto promptlyuseyour
interface.To fully understandandcontrol the AD2000 functions, read 2
Chapters through 4. Chapter5 containsboard
calibrationprocedures.
The chaptersand appendixesin this manualaredescribedin denil below.
Chapter1, "Quick Start--Geuing Your AD2000 Running," providesthe instructionsnecessaryto
insall theboardanduseits basicfunctions.Theinformationcontainedin this chapterdoesnot cover
how !o changethe boardseurp,exceptfor thebaseICI address.
Chapter2, "Functional Description,"providesa block diagnm and a functional discussionof the
board.
Chapter3, 'Tumper Settings,"describeseachheaderor jumper circuit on the board and how it is
controlled.
Chapter4, "ProgrammingYour AD2000,' describeshow the board canbe programmedusing the
demonstrationsoftware.
Chapter5, "Calibration Procedures,"providesinstructionsfor boardcalibration.
Appendix A, "AD2000 Specifications,"containsa completelisting of boardspecifications.
Appendix B, "ConnectorPin Assignments,"conlainsthe pinous of the externalVO connecorsand
the matingconnectors'part numbers.
Appendix C, 'Component Data She€ts,"contains manufac[rers' data sheetsfor major board
components.
Appendix D, "Configuring the AD2000 for SIGNAL*MATH," containsinformation aboutseuing
boardjumpers and and initializing the board to run the SIGNAL*MATH acquisitionand analysis
program.
Appendix E, "Configuring the AD2000 for ATLANTIS," coniainsinformationaboutsettingboard
jumpersto run the ATLANTIS dataacquisitionandreal-timemonitoringprogram.
Appendix F, "Warranty," containsboardwarrantyinformation.

When You NeedHelp

Whenyou areworking with the AD2000 interfaceboard,this manualandthe demosoftwareincludedin your package
will providesufficientinformationto properlyconnol all of theboard'sfunctions.If, however,aftercarefullyreviewing
1fus66p'ral,youareunabletoobtainproperresponses fromtheboard,Real TimeDevices'technicalstaffisreadyoassist
you. For assistance,call (814) 234-8087during regularbusinesshours,easternstandardtime or easterndaytght time,
or senda FAX requestingassistance to (814) 234-5218.Be sure!o includeyour company'sname,your name,your
telephone number, anda brief descriptionof the problem.

i-2
 CHAPTER 1

RUNNING
QUICK START_GETTING YOUR AD2OOO
To get startedusingyour AD2000 interfaceboard,you must:
- Selectby jumpera baseI/O addresswhich doesnot contendwith any ottrerperipheraldevice.
- Installtheboardino yourPC.
- Connecta signalto oneofthe analoginputchannels.
- Run the AD2000 software.
Unlessyou haveotherrequirements,thesestepsareall that are necessaryto useyour AD2000 board.
This chapterexplainshow to insrallyoru AD2000anduseits basicfunctions.You will learnhow to:
. Changethe baseVO addresssetring,
. Install the boardin your PC,
. Initialize the board,
. Selectthe analoginput channeland gain,
. Take an A/D reading.
This chapterallows you to immediately start using the basic functions of your AD2000 board for daa collection
applications.This chapterdoesnot explainhow !o controlthemoreintricateboardfunctionssuchastheprogrammable
intervaltimer,thevariousdigitalVOconfigurations,orintemrpts, nordoesitexplainhowto changehardware-controlled
I/O
seuingsexceptfor the base address. The functionsnot covered herearedescribedin Chapters2 through4.

What ComesWith Your AD2000

The standardAD2000 boardpackageincludes:

1 AD20005.5-inch (1a0mm)interfaceboard(fits short slot)

I AD200Odemodisk
I user'smanual

Additional items, suchas the AD2000 2-cableset (order numberXK40-l), extenderboardsor SIGNAL*MATH or
ATLANTIS applicationsoftware,areavailablefor this boardandare includedon an as-orderedbasis.
All signalson your board are madeeasily accessiblewith Real Time Devices' XB40 VO extenderboard and XC40
expansioncable.The extenderboardhastwo 20-pinterminalstripsanda prototypeareato supportany specialcircuitry
you mayrequireto conditionthesignals.For example,if you areprototypingsolid-staterelaysor optoisolalors,this can
easily be done with an XM0. The expansioncable terminatesin a 40-pin wire-wrap headerconnectorsuitablefor
installationin standard0.1 inch spacingperf-boardmaterialavailablefrom mostelectronicdisributors.

The Hardware
The AD2000 interfaceboard is shownin Figure l-1. A completelisting of the board specificationsis containedin
Appendix A. The AD2000 hasseveralfeatureswhich are user-controlledthroughhardwareor software.Most of the
hardware-controllablefeaturesarejumper-contnolled;theremainingare switch+onnolled.
Allofttreboardcomponentsaremountedona5.5-inchprintedcircuitboardwhichfitsinany unusedexpansion
slot(short
or full-size) in an IBM PC/XT/AT or compatiblecomputer.Two 4Gpin connectorson the board, P8 and Pl5,
accommodateall of theboard'sextemalI/O. In operation,theseconnectorsarecabledsothat all S0linesareaccessible
at the rearpanelof ttrecomputer(seethe boardinstallationinstructionslater in this chapter).

FunctionsYou Can Set

To allow the AD2000 interfaceboardto be adaptedto your needs,severalfunctionscanbe setup to perform specific
tasksby changingthe hardwareconfigurationor throughsoftware.Table l-1 lists eachfunction you can control, the
facory (or default) settingif applicable,and wherein this manualyou can find informationaboutits settings.

l-l
 *-Sy-1lU;tH.t5= U L
lH l-.2-r * ;--7=,. l+ I
* -l
--
ru tui=sr
A -F-"
EIJ=Ff,--d
-r E?

tP2

:nl
ilc- 12-BitA/D Board

Fig. 1-1 - AD2000 Board Layout

The functionswhich you can control throughhardwareare:
- BaseI/O address,
- Analog input channeltype,
- Analog input channelvoltagerangeandpolarity,
- End-of-convert.monitor,
- PIT timerrcounters(hardwareand software),
- Intemrpts.
The functionswhich you cancontrol throughsoftwareare:
- Analog input channelselection,
- Analog input gain selection,
- Digital VO,
- PIT timer/counters(softwareand hardware),
- Boardinitialization.

Settingthe BaseVO Address

Startingwith thebasel/Oaddress (BA), theAD2000boarduses 12address locationsin yourcomputer'sI/O space.Table
1-2 lists the VO map for the AD2000. It is importantto recognizethat someof your computer'sVO addresslocations
will alreadybe occupiedby internalI/O andotherperipherals.If your AD2000boardtries to useI/O addresslocations
alreadyin useby anotherdevicein your syst€m,addresscontentionwill result.Hence,theboardwill not operate,or at
bestwill operateerratically.
VO addresscontentionis one of the most commonproblemsencounteredwhen adding an interfacedevice to your
computersystem.Toavoidthisproblem,abaseVOaddrcssjumpercircuitisprovidedontheAD2000board. By changing
the position of thejumper on the headerconnectorlabeledP2 Qocatedjust to the left of center,nearthe botom of the
board),thebaseI/O addresssettingcanbe changedto any oneofeight locations.

L-2
 Table 1-1-AD2000 Board Functions and Settlngs

FUNCTION FACTORY SETTING USER INFORMATION

Basel/OAddress 300hex(768decimal) To changethis setting,see

"Settingthe Basel/O
Address," Chapter1

AnalogInputChannelType 8 differential
channels To select16 single-ended
channels,seeS1 discussion,
Chapter3

AnaloglnputChannel lable
Software-control See "Selectingan Analog
Selection InputChannel,"Chapter1,
anddemodisk

AnaloglnputGainSelection lable
Software-control See"Settingthe InputGain,"
Chapter1, anddemodisk
AnaloglnputVoltageRange whenordering To changethesesettings,
User-specified see
and Polarity 51 and P9 discussions,
Chapter3.
-Convert(EOC)Monitor Connectedto PA7
End-of See P6 discussion,
Chapter3.
Digitall/O
16 l/OLinesfromPPI lable
Software-control See"Programmingthe PPl,
Chapter4 anddemodisk
Programmable Inverval
Timer
(PlT)Circuitry

Modes lable
Soflware-control See"Programmingthe PlT,"
Chapter4 anddemodisk
l/O Conliguration Clocklnput:5MHz See P3 discussion,
Chapter3
GateInput:+5 V
ClockOutput:To PB

Interrupts Disabled See P4,P5,and P7

discussions,Chapter3, and
"lnterruptConsiderations,"
Chapter4

l-3
FigureI -2 showsthebaseI/O address headerconnector, P2,with thejumperinstalledat thefactory-setlocationof 300
hex.Thejumpermustbeinstalledvertically acrossone of theeightpairsofpinsonP2.ThehexadecimalbaseVOaddress
settingconespondingto each pair of pins,from is
left to right, as follows:

200 240 280 2C0 300 340 380 3C0

For example,if thebaseI/O address is changedto 280hex,thenfor the 12operations listedin Table1-2,BA equals280.
Thus,to sendthechannelselectionandgaindatato port B of thePPI,its addressof BA + 1 becomes281 hex.
If thefactorysettingof 300hexwill causecontentionin yoursystem,positionthejumpertothedesiredbaseVOaddress
setting.OnceyouhavesetthebaseI/O address, makea noteof its valueon thetableinsidethebackcoverof thismanual.
You will needto know this settingfor usein your programs.

N g)
o
o o
o

P2
Fig. 1-2 - Base l/O AddressConnector,P2

Installingthe AD2000in Your Computer

Beforeinstalling the AD2000 in your computer,makesurethat thebaseI/O addresshasbeenproperly selectedandall
thehardwaresettingshavebeenconfiguredo supportyourrequirements. Thischapterexplains how to controlthebase
VO address. Otherhardware are
settings setat thefactory,aslistedin Table 1-1, andremainat their factorysettingsunless
you changethem.The intemrptsgeneratedby your AD2000aredisabled(not connected)whenyou receiveyour board.
If you intendto usetheintemrpts,theymustbeconfiguredappropriately beforeinstallingtheboard.Informationabout
theseandotherfunctionsnot coveredin this chapteris providedin Chapters2 through4. Usethesechaptersasnecessary
to configureyour boardbeforeinstallation.
To install your AD2000, follow thesestep-by-stepprocedures:

1.TURN OFFTIIE POWERTO YOURCOMPUTERFIRST.Referto theowner'smanualfor your

computer,andremovethe top cover.
2. Selectan unusedexpansionslot (shortor full-size)in which to installyourboardandremoveits
correspondingblank bracketfrom therearpanelof the computerby removingtte screwat the
top of the bracket.
3. Beforeplacingthe boardinto the computer,two ribboncableassemblies mustbe inslalledon
boardconnectorsPS andPl5.Ifyouhavepurchased theAD2000cableset,firstinstallthetwisted
pair cableon analogVO connectorP8.Theninstallthestandardcableon Pl5. Eachcableis a
4Oline externalVO cablewhich extendsthroughthe connectorslot in the rearpanelof the
computer.Both cablesrun througha singleslot wheretheyprovide80lines of externalI/O to
theboard.Thisconfiguration allowssubstantialboard I/O throughasingleexpansionportinyour
computer.AppendixB lists the signalcarriedon eachpin of theseconneclors.To install the
cables:
a. Removethestrainrelief clampattachedto theAD2000bracketlocatedon theright sideof
the board.
b. Connectthe socketconnectorto boardconnectorfor eachcable.Wheninstalling,observe
theconnectorkeyingandpressfirmly to makesurethatthesocketconnectoris fully seated
on the board.Each cableprovidedis labeledwith the connector'sP numberfor easy
identification.The cableshavestrainreliefson one connectorandnot on the other.The
connectorwithout the sFainrelief is to be installedon the board.After both cablesare
installedon theboard,positionthemsothattheypassovertheflangein theboard'sbracket.

t-4
 Table 1-2-AD2000 l/O Map

FUNCTION A4 A3 A2 A1 AO R/W BA + HEX

PPI

PortA 0 0 0 0 0 R/W 0
PortB (ChannelSel&Gain) 0 0 0 0 1 W 1
PortC 0 0 0 1 0 R/W 2
ControlWord 0 0 0 1 1 w 3

l/D Conversion
Circuitry

Start12-bitConversion 0 0 1 x 0 w 4or6
Start8-bitConversion 0 0 1 x 1 w 5 or7
ReadMSB 0 0 1 x 0 R 4or6
ReadLSB 0 0 1 x 1 R 5or7

lntervalTimer
Programmable

Counter0 1 0 1 0 0 R/W 14
Counter1 1 0 1 0 1 R/W 15
Counter2 1 0 1 1 0 R/W 16
ControlWord 1 0 1 1 1 W 17

NOTE:x = don'tcaresetting

l-5
 c. Re-at6chtheclampto thebracketusingthehardwaresuppliedwith your AD2000,securing
the ribbon cablesin place.
4. l.J:tercheckingthat the cablesare correctly installedon the board,orient the board inside the
computerso that thecablesextendthroughtherearpanelopeningandthe cardedgeconnector
lines up with the expansionslot connector.Then,pressdown on the metalbrackettab and the
top of the boarduntil the boardis firmly seatedin the expansionslot connector.
5. Securethe bracketbackin placewith the screwandput the coverback on your computer.

Now your boardis readyto beconnectedvia theexternalconnectorsat therearof thecomputer.After theseconnections

havebeenmade,the boardis readyfor operation.

The Software
The AD2000 operatesunder softwarecontrol. Programmingincludesthe analoginput channelselectionand gain,
control of the the A/D conversion,the programmableperipheralinterface,and the programmableinterval timer. The
analoginput channelandgain selectionsandtakingan A7Dreadingarecoveredin this chapter.Digital I/O control and
control of the programmableinterval timer are more complex,and are de.scribedin Chapter4, "ProgrammingYour
AD2000."
Regardlessof what programminglang"age you use, you can write programstlat conEol the AD2000 board. The
demonstrationdisk which accompaniesyour AD2000 containsexamplesin Turbo C, Turbo Pascal,and BASIC.
Nearly all modernMS-DOS-basedPC languageshaveI/O referenceinstructions.Theseare the insructions to control
thedataransfers to andfrom theI/O ports.Consultyour programminglanguagereferenceto find theseinstnrctionsfor
your favorite language.Listed below are the VO referenceinstructionsusedby somecommonlanguages.

BASIC TURBO PASCAL TURBOC

input: INP Port inportb
output: OUT Port ouQortb

DemoDisk
Included with your AD2000 is a demo disk which providesprogramminginstructionsand exampleprogramsfor
controlling the functionsof your interfaceboard.This demodisk is divided ino directories,eachof which is named
accordingto the languageusedto write 0re programsit contains.The files within eachdirectory coniain example
programsanda documentationfile witi generalinformation.In addition,your demodisk containsa README.DOC
file which providesprogramminginformation for your board.
Eachexampleprogxamshowsyou how to controla particularboardfunction,suchasselectingan input channelor input
gain, controlling the A/D converter,controlling digital data Eansfers,and seuing the timer/countercircuitry. These
programsshouldbe usedto becomefamiliar with thesefunctions.

Backing Up Your Disk

Thedemodisk providedwith theAD2000is a double-sidedformatwhich canbereadby all DOSversions1.1andabove.
Beforeusingthe softwareincludedwith your board,makea backupcopy of thedisk. You may makeasmanybackups
as you need.To copy the original to any other DOS-formatteddisk, insert the disk o be copiedinto drive A of your
computer,and from DOS enter:
COPY A:*.* B: (or otherdestinationdrive specifier)

l-6
Initializing Your AD2000
BeforeyoucanoperatetheAD2000,it mustbe initialized.This stepmustbe executedeverytime you startup,reset,or
rebootthecomput€r.This setsup thePPI to properlycommunicate with theA,/Dconvertercircuitry.If theboardis not
andwill probablylock up,requiringyouto rebootyoursystem.
initialized,it will notrespondto thesoftwarecommands
As describedearlier,theAD2000uses12addresslocationsin thecomputer'sI/O space,Theseaddresslocationsstart
with tle baseI/O address(BA) andgo throughBA + 17(hex).BA + 8 throughBA + 13arenotused.Tablel-2 provides
theAD2000I/Omap,definingwhatfunctioneachof the12addresses controls.RecallthatthebaseI/O addressis factory-
setat 300 hex.On thedemodisk, thebaseI/O addressis usuallystoredin thevariable"board."Rememberto usetlre
correctbaseVO addressin tle demodisk programsor yourown programs.Thedemodisk explainshow to changethe
baseI/O addressin the programs.
The AD2000 is inirialized by simply writing a control byte lo the PPI control registermappedat the VO locationbase
address+ 3 (hex).The conrol bytemustconformto this generalform:

lxxx x00x wherex =don'tcare

This ensuresthatthe eightI/O linesmakingup port B of thePPI,which areusedto controlthe multiplexerand gain
circuitry,areconfiguredasoutputs.Thedon'tcare(x) positionscontrolthedirectionof theremaining16digitalI/O lines
availableon thePPI.Theselinescanbe confrguredasinputs,outputs,or in othermorecomplexconfigurations.
For example,whenthecontrolbytebit patternis:

100000000 (decimal128)

the AD2000 is initialized as follows:

out base_address+3,
I 28

Whenthisvalueis usedto initializetheAD2000,theeightport C linesof thePPIwill all be configuredasoutputs.You

cantransferdatato theselineswith thecommand:

out base_ad&ess+2,data

If instead,thedecimalvalue137(10001001)is usedto initializetheAD2000,theport C lineswill be setup asinputs.

You caninput datafrom port C with the command:

data= inp(base_address+2)

Note thatport A, bit 7 (PA7) of the PPI is factory-setto monitorthe end-of-convert(EOC)signal.The PPI mustbe
programmedso thatport A is an inputif you aregoingto monitortheEOC signalthroughPA7. Theconnolbyte must
thenconformto thegeneralform of lxx! x00x,wheretheunderlinedI is thedatabit which setsup port A asaninput.
A functionaldescriptionof thePPIis containedin Chapter2,'Functional Description,"andhardwareconfigurations
are
describedin Chapter3, "JumperSettings."Informationabouthow you cancontrolthediginl I/O linesis containedin
Chapter4, "ProgrammingYour AD2000,"andis not coveredherebecauseof its complexity.
As mentionedearlier,theeightlinesof port B areusedto selecttheanaloginputchannelandgain.The four LSBs,PB
(forPortB) 0 throughPB3,controlthechannel selection,andthe
fourMSBs,PB4throughPBT,control thegainselection.
Thebit assignment of thisport is:

t-'7
 MSBs LSBs
7654 3210 P P IP o r t B ( B a s e A d d r e s s + 1 )
\-rJ +.-'
gainselect channelselect

0000= 1x 0000= channel1

0001= 2x 0001= channel2
0 0 1 0= 4 x 0010
0100= 8x 0011
1 0 0 0= 1 6 x 0100
0 10 1
0 11 0
0111
1000
1001
1010
1 0 11
11 0 0
11 0 1
1 1 1 0= c h a n n e1l5
1 1 1 1= c h a n n e1l6

After theAD2000 is initialized, theport B registeris loadedwith thedefaultsettingof 00000000.This selectschannel

I as the input channelwith a gainof 1. To changethis value,for example,lo a gain of2x on channel16,enterthese
commands:

BA + I (hex) selectsport B
0001 1111 sesgainto2xandchannelo
16

Recallthattheboard'sdefaultchannelsettingis eightdifferentialchannels.Therefore,only the channelselectbinary

valuesforchannelsI through8 apply.Channels9 through16areusedin thesingle-ended channelmodeonly.
Now yourboardisinitializedandready ooperate.Thefollowingsectionsdescribehow toselecttheanaloginputchannel,
setthe input gain,and takean A/D reading.Masteringtheseoperationswill allow you to effectively useyour boardfor
dataacquisitionapplications.

Selectingan Analog Input Channel

After theAD2000hasbeeninitializedyou canselecttheanaloginputchannel.Theanaloginputchannelis selectedby
writing !o port B of the PPI, mappedat I/O locationbaseaddress(BA) + 1.
The inputchannelandtheinputgaincanbe setindividuallyby settingonly thefour LSBs (channelselect)or only the
four MSBs Gain) of tie eight-bitcontrolword sentto port B. Beforeyou changeeitherthe input channelor thegain,
you MUST preservetle currentstateof port B. Failure trodo so will resultin changingboth the channelselectandthe
gainwhenyou intendedo changeonly oneof thesetwo settings.
Thegeneralalgorithmfor settingtlechannel(changing just thefourLSBsof thecontrolwordwhilepreservingthefour
MSBs)is:

l-8
 1. Readthecurrentstateof port B:
curent_state= inpoase_address+1)
2. Preservetheupperfour bits sincetheycontaingaindata:
current_s[ate= current-slateAND $F0
3. LogicallyOR thecurrent_statewith thedesiredchannelnumberminus 1:
curenr-state curent_stateOR (channel- l)
=
4. Write it backout to port B:
l,current_state
out base_address+

A BASIC programto selectchannel2 is:

100BASE-ADDRESSTo= 768
110CHANNELVo =2
=
120STATUSTo INP(BASE-ADDRESSTo+ l)
130STATUSTo= STATUSToAND &HFO
140STATUSTo= STATUSToOR (CHANNELTo-l)
150OUT BASE-ADDRESSTo + I,STATUSTo

Settingthe Input Gain

Thegainis setbywritingtotheupperfourbitsofportBatBA + l. Thebitpatternforeachof thefivegainvaluessupported
by the hardwareare:

0000 = gain of I
0001= gainof2
0010= gainof 4
0100= gainof 8
1000= gainof 16

It is recommendedthat no otherbit patternsbe usedwhen settingthe gain.

The generalalgorithm for settingthe gain is:

1. Readthecurrentstateof port B:
current-state= inp(base_address+
1)
2. heserve the lower four bits sincetheycontainchannelinformation:
current-sCate= CUrrg[t-StateAND $0F
3. Ingically OR thecurent_statewith a bit pattemthatactivatesthedesiredgain:
current_state= currgnt_State oR gain bit pattern:
lx bit pattern= 0
2x bitpattern= 16
4x bit pauern= 32
8x bit Pattern= 64
l6xbitpattern= 128
4. Write the current_stateback to port B:
out base_addrcss+ l,current-state

r-9
A BASIC programto seta gainof 2 is:

100BASE-ADDRESSTo = 768
110GAINTo= 2
120STATUSTo= INP(BASE-ADDRESSTo+ l)
130STATUSTo= STATUSToAND &H0F
140IF GAINTo= I GOTO 160
150STATUSTo= STATUSToOR (GAINTo* 8)
+I,STATUS7o
160OUT BASE-ADDRESSTo

Taking an A/D Reading

After you haveselectedan analoginput channeland setthe gain, you can takean A/D reading.It is importantto note
thatoncethegainandchannelareset,theystayat thosesettingsuntil you changethem;thatis, theyarelatched.You
do not haveto setthe gain or channelevery time you takea reading.
Eachtime an A/D conversionis completed,an end-of-convert(EOC) signalis generatedto signify the end of the
conversion.Thissignalcanbeusedinanumberofways.Onewayis to usethislineto monitortheAlDconversionstatus.
SeninguptheEOC signalobe monitoredinvolvesconfiguringbitT ofPPlportAorportC asaninputlineandconnecting
theE@ signalto it. This procedureis detailedin Chapter3,'TumperSettings."The EOC signalis factory-setto be
monitoredthroughPA7 on headerconnectorP6.
The generalalgorithm for taking an A/D readingis:

+ 4 (or 6):
1. Starta l2-bitconversionby writing o base-address
out base-address+4,0
(Note that the valueyou sendis not important.The act of writing to this I/O location is the key
to startinga conversion.)
2.Delay at least20 microseconds or monitorPPI port A or C, bit 7 for a transition.Polling
permits the fastestdataacquisition.
3. Readtheleastsignificantbit from base-address + 5 (or 7):
--
lsb%o inp(base-address%o +5)
4. Readthemostsignificantbit from base_address + 4 (or 6):
=
msbTo inp(base-address7o +4)
5. Combine them into ttre 12-bitresultby shiftingtheLSB four bits o theright. The MSB must
alsobe weightedconectly:
resultVo- (msb7o* 16) + (lsb7ol16)

For a l2-bit conversion,the A/D datareadis left justified in a l6-bit word,with theleastsignificantfour bis equalto
zero,asshownin Figurel-3. Because of ttris,thetwobytesof A7Ddatareadmustbescaledto obtaina validA/D reading.
Onceit is calculated,thereadingcanbecorrelatedlo a voltagevalueby scalingit, in thecaseof bipolarinputranges(t5
or +10 volts),andthenmultiplyingby theappropriate bit weight,asshownin thetableat thetopof thefollowingpage:

MSB LSB
D15 014 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO
D B 1 2DB11 D B l O D89 D88 D87 D86 D85 D84 D83 D82 DB1 0 0 0 0

Fig.1-3- A/D Conversion

WordFormat

l-10
 Input Range ScaleFactor Bit Weight
+5 volts Subtract
2M8 2.4414mY
+10 volts Subnact2048 4.8828mV
0 to +10 volts None 2.4414mY

For example,if theA/D readingis 1024andthe inputrangeusedis *5 volts,theanaloginput voltageis calculatedas

follows:
00z. - 2&18)bits * 2.4414mv/bit = -2.49999volif,.

For a tlO volt input range,the voltageis calculatedasfollows:

(l0U - 2048)bits * 4.8828mv/bit = -4.99999volts.

For a 0 to +10 volt inputrange,no scalingis requiredandthe voltageis calculatedasfollows:

1024birs * 2.4414mV/bit = 2.49999volrs.

The input voltagerangeandpolarity arefactory-setaccordingto customerspecificationswhen orderingthe board.Il

afterreceivingyourboard, youwishtochangetheinputvoltage,seeChapter3,'TumperSettings."Wheneverthevoltage
polarity is changed(unipolarto bipolaror vice versa),theA/D convertershouldberecalibratedasdescribedin Chapter
5, "Calibrationhocedures."
Notethateight-bitA/t) conversions canalsobeperformed.This is accomplished by writing to I/O locationBA + 5 (or
7). While aneight-bitconversionhasa lowerresolutionthanthe 12-bitconversion,it is performedmuchmorerapidly,
in about13microseconds. A 12-bitconversion takesabout20 Therefore,whenspeedis essential,
microseconds. youcan
usetheeight-bitconversioncapability.

t-11
 CHAPTER 2

FUNCTIONALDESCRIPTION
Thischapterdescribes Figure2-1showsablockdiagnm of ttteboard.
themajorfunctionsof theAD2000interfaceboard.
The functionsdiscussedin the following sectionsare:
. Analog-to-digitalconversioncircuiry
. Programmableperipheralinterface(PPI) circuiry
. Programmableinterval timer (PIT) circuitry

Analog-to-DigitalConversionCircuitry
The main function of the AD2000 interfaceboardis to provide high-speedanalog+odigital conversioncapability for
dataacquisition.The analog-to-digital(AlD) conversioncircuitry receivesinpus from eight differential or 16 single-
endedanalogchannels, selectsoneactivechannel,andperforms ananalog-to-digitalconversionof thevoltagevalueread
at that channel.The conversionthroughputrateis typically 38 kIIz.

Multiplexers
Two eight-bit analogmultiplexersareusedto connecteitheroneof 16 single-endedor one of eight differential analog
channelso the gain circuiry. The leftmostthreeswitcheson DIP swirchS1 setup themultiplexerat IC locationU9 !o
receiveeither single-endedor differential inputs.Whenthesethreeswitchesare up, the multiplexer is configuredfor
single-endedinputs,andwhentheyaredown, themultiplexeris configuredfor differential inputs.Note thatthesethree
swirchesare alwayssetas a gloup to the sameposition(see"Sl SwitchSettings,"Chapter3). A channelis selected
throughsoftwarecontrol, by writing to port B of the PPI, asdescribedin Chapterl.

16AilAlG NruTS
€V TO+$r
0 TO+10\,
-'l0VTO+t0V
tlFF./ t5 s.t

Fig.2-1- AD2000Functional
BlockDiagram

2-l
Gain Control Circuitry
Theprogrammable gaincontrolcircuiry canprovideagainfactorof 1,2,4,8,or 16.Thegainselectionis madeby writing
to port B of the PPI, asdescribedin Chapter1. The gain facor is conrolled by the settingof four analogswitches.For
againof2,4,8, or 16, thiswriteoperationwill closeoneof thefourswitches;foragain factorof 1,all switchesareopen.
Note that programming gain facors other tlnn the five listed hereis not recommended.

Sampleand Hold Circuitry

A sampleand hold (SAD amplifier is usedbenveenthe gain control circuiry output and tlte A/D input to ensurethat
dynamicanalogsignalsareaccuratelydigitizedby theA/D converter.The .001pF hold capacitorusedin this circuit is
apolystyrenetypeselectedfor is low dielecnicabsorption.Its low valueminimizestheacquisitiontime (6 microseconds,
typical),andminimizeshold stepvoltageanddroop.Thesampleandholdtimeandratearedeterminedby theEOCsignal
generatedby the A/D converterand fed backinto the SAI circuir WhentheEOC signalis high (logic 1), the amplifier
samplesthe analoginpuq when the EOC signalis low (logic 0), the amplifier holdsthe inpur

A"/DConverter
TheA/D converteris a high-speed l2-bit conversionIC whichperformsconversions in approximately20 microseconds.
Eight-bit conversionscanalsobe performedwhenspeedis morecritical thanresolution.An eight-bit conversiontakes
about 13 microseconds,allowing rapid conversionsof dynamicanaloginputs.The convertersupports10- or 20-volt
analoginput signals;however,it cannotsupporta 20-volt unipolarinputrangebecauseits supplyvoltagein theAD2000
applicationis only +12 volts. The analoginput voltagenmgessupportedby the AD2000 arelisted in the specifications
in AppendixA. Calibrationcircuiry is includedfor unipolarandbipolar calibrationof the A/D converter.Calibration
proceduresaredescribedin Chapter5.
An 8- or 12-bitconversionis initiatedby a write operationto theappropfutelO address.Oncea conversionis begun,
the conversionstatuscanbe monitoredby readingthe AID converterstatus(STS)signalwhich is ouput from the A/D
converterIC andinvertedbeforebeingmadeavailableto othercircuitry on theboardasttteend-of-convert@OC)signal.
The EOC signal canbe monitoredby one of nro digital input lines on the PPI, PA7 or PC7. Note that if either line is
selectedasthe EOC monitor, a jumper mustbe installedfor the selectedline on P6 andthat line mustbe configuredas
an input. The EOC signalis factory-setto be monitoredthroughPA7 on P6. The EOC signalis low (logic 0) during a
conversion.Figure 2-2 showsthe EOC timing diagram.Also, the three-state A/D outputbuffersremainin a high-
impedance state,and,therefore,datacannotberead. Whileaconversion anytransitionsof thedigitalinpus
is inprogress,
whichcontroltheconversionwill beignored,sothattheconversion cannotbeprematurelyterminatedor restarted. Once
theconversionis complete@OCis now high,or logic 1),theA/D datacanbereadin two bytes,theMSB andtheLSB,
in anyorder.Fora l2-bitconvenion,tie dataisleft-justifiedin a l6-bit word.In thecaseof aneight-bitconversion, the
datais completelycontainedin theeight-bitMSB.
Referto Chapterl, "Taking an A/D Reading,"andthe demodisk for moreinformationaboutusingthe AID converter.

A/Dcs
v
Eoc- tl
r---, fi-
Data 14
Fig.2-2-EOC TimingDiagram

aa
ProgrammablePeripheralfnterface
The hogrammablePeripheralInterface@PI) provides16TTL/CMOS digital VO lines which canbe configuredin a
numberof waysto supportuserrequirements.Thelinesavailablefor digital I/O areport A andport C. The8255PPI has
antalof 24 digitalI/O lines,eightof whichareusedto connoltheA/D channelselectionandgaincircuiry, andtherefore
arenotavailableto theuser.Theremaining16linesareavailableatextemalVO connecorPl5. The24linesaregrouped
into threeeight-bit ports,port A, port B, and port C. Port C is further suMivided into two four-bit ports,port C lower
(PC0-PC3)andport C upper(PC4-PC7)in certainmodesof operation.The PPI datasheetis includedin Appendix C.
The eight bits ofport B arereservedfor A/D channelselectionandgain control, andcannotbe configuredfor I/O use.
PortsA and C can be configuredin any of the threeoperatingmodesdescribedbelow:

Mode 0 - Basic input/outpur Providessimple input and output operat"ions for eachport. Data is
written to or readfrom a specifiedport.
Mode I - Srobed inpuUoutput.Providesa meansfor transferringlO datzto or from port A or port
B in conjunctionwith strobesor handshaking signals.
Mode2 -Suobedbidirectional input/output.Providesabidirectionalmeansof communicating with
anotherdeviceon a singleeight-bitbus.Handshaking signalsaresimilarto mode1.Thismodeapplies
to port A only.

In mode0, all four ports (A, B, C lower, andC upper)areavailableasVO lines. Sixteenconfigurationsarepossiblein
tlfs mode,andanyportcanbeconfiguredasaninputoranoutput.Theouputsarelarched,buttheinpusarenotlarched.
In modeI , thefour portsaregfoupedinto two groups.Eachgrcupcontainsoneeight-bitdataport (port A or port B) and
onefour-bit control/dataport (port C lower or port C upper)which is usedfor controlandstatusof theeight-bitport. The
eight-bit dataport in eachgroup canbe configuredasan input or an outpul Both inputsand outputsare latched.
In mode2, port A is an eight-bitbidirectionalbusandport C is a five-bit controlport PortB cannotbeusedin this mode,
but is availablefor usein mode0 or modeI while port A is in mode2. Both inputsandoutputsarelarched.
The PPI is configuredby writing a control word to the appropriateVO addresslocation, as describedin Chapter4,
"ProgrammingYour AD2000."
The control word canalsobe usedto individually setor resettheport C bis. This featureallows any bit of port C to be
setor resetwithout affecting the otherport C bits. The datasheetincludedin Appendix C explainsthis feature.
ThePPIcanalsobeusedo generateinterupts in modeI or mode2operation.Inthesemodes,theintemrptenable (INTE)
maskis usedto enabletheINTRA andINTRB interruptsignals.NotettrattheINTRB signalfor PPIcannotbe usedsince
portB of thisPPIis alwaysconfiguredasmode0 outputandis reservedfor channelselectionandgaincontrol.Intemrpt
functionsare further explainedin the datasheetin AppendixC.
The AD2000 boardprovidesa headerconnectorwhich canjumper the A/D converterend-of-convert(EOC) signal!o
a PPI bit whereit canbe monitoredto provide A/D conversionstatus.The EOC signalcanbejumperedto eitherPA7
(portA, bit 7) or PC7(portC, bit 7). Thedefaultsettingof thejumperis PA7.Theport usedto moni[orttreEOC signal
mustbe configuredasa mode0 input port.

ProgrammableInterval Timer (PIT)

Theprogrammable intervaltimer@IT) canbe configuredfor a varietyof timingandcountingfunctions.This versatile
IC containsthreeindependently clockedl6-bit timer/countercircuis, TC0, TCl, and TC2, which operateas down
counters.Thesedown counterscanresolvetime incrementsdown to 125nanoseconds. This circuit's mostcommon
applicationis to provide accuratetime delaysunder softwarecontrol. Upon command,the PIT can count out a
programmeddelay andinterruptthePC whenithasfinisheditstasks.All threecounteroutputsarebroughtouttoexternal
I/O connectorP15.
The three16-bittimer/counters areeachloadedby two one-bytewrite operationsto the appropriateI/O location.fire
bytesarelatchedintoa l6-bit internalcountregister,
wheretheyarestoreduntil thecountsequencestarts.Thecountdown
stafiswhenthecountregistercontentsaretransferred(in parallel)to thedowncounter.The timer/countercircuitscan
be programmedfor binaryor BCD countdowns.

2-3
A 5 MlIz crystaloscillatoron the AD2000 canbe usedto clock any timer/countercircuit Or, the timer/countercanbe
clockedbyasourceexternalto theboardthroughexternalVO connectorPl5.Ratesof dc to 8 MIIzcan beusedaoclock
thetimerrcounters.
Eachtimer/countercanbe configuredfor oneof six modesof operation.Thesemodesare:
Mode0 - Interrupton endof count.TheOUT signalchangesfrom low to highwhentltecountdown
is completed.
Mode1- Re-triggerable one-shot.A low-levelpulseriggeredby theGT inputis outputon theOUT
pin.
Mode2-Rategenerator.
Mode 3 - Squarewavegenerator.
Mode 4 - Sofnrare-triggeredstrobe.
Mode 5 - Hardware-triggeredstrobe(re-triggerable).
Thetimer/countercountmodes, aswell asthecounttype(binaryor BCD),read/writemode,andcounter/timerselection
mode,areall part of the control word which is written o the PIT control registerto initialize tle circuir When the PC
is poweredup, thetimer/countercircuits arenot defineduntil theappropriatecontrolwordsarewritten to thecircuits !o
programthemforoperation.Initializationisrequired onlyonceafterapower-upresetoccurs. Detailedinformation about
thePIT, including theconnol word format,is given in thedatasheetin AppendixC. AppendixD containsprogramming
notesfor somePIT applications.
The threetimerrcountercircuifs areindependent.However,they canbe cascadedfor countdownswhich arelongertlnn
one 16bit field cansupporLFor example,TCO'SOUT signalcanbe connected to TCI's CK signal,andTCl's OUT
signal can be connectedto TC2's CK signal.When configuredttris way, the PIT can accommodateextremelylong
countdowns.This configurationis describedin the applicationnotesin Appendix D.
Oneof the threetimer/counteroutputs,TCOOUT, TCI OUT, or TC2 OUT, canalsobe usedasa PC intemrpt. These
signalsarebroughtout to boardheaderconnectorP5whereone(andonly one)canbe.selectedfor connertion[o anyone
IRQ channel,RQ2 throughIRQ7. Chapter3, "JumperSettings,"and Chapter4, "ProgrammingYour AD2000,"
describetheseintemrptsin moredetail.

24
 CHAPTER 3

JUMPERSETTINGS
Thischapterdescribes theAD2000boardsettingsyoucancontrolon DIP switchSI andvariousheaderconnectors. You
canusethischapterto tailor your board'sfunctions to yourspecificapplicationbefore installing it in your or
computer,
to changetheboard'sconfigurationas you learn more about.its operation
and specialfeatures. In this you
chapter, will
leamabouteachsettingandhowto setswitchesor installjumpersto achievethedesiredoperationof yourboard.Before
changingany settings,you shouldhavea functionalknowledgeof the circuit you are settingup (seeChapter2).
Remember thatall of thesettingsdescribed in thischapterhavebeenfaclory-set,or, asin thecaseof theintemrptsignals,
aredisabled.Therefore, do you not have to do any furtherset-upof ttreboardin orderfor it to operatein your system
in
asdescribed Chapter 1. The descriptions thischapterallow you to changefactorysettings,or to tailor your board
in
to takefull advantage of built-in versatility.
its
ThereareoneDIP switchandseveralheaderconnectorswhich allow you to controlvariousboardfunctions.Theseare
shownin theboardlayoutof Figure3-l andarepresented asfollows:
Sl * AnalogInput SignalType DIP Switch
P2 - BaseI/O AddressHeaderConnector
P3 - ProgrammableInterval Timer (PIT) I/O HeaderConnector
P4, P5, andP7 - Intemrpt HeaderConnectors
P6 - Endof-Convert(EOC)Monitor HeaderConnector
W - A/D ConverterVoltageRangeHeaderConnector

H,H'Flffiffif
Y r 6 . \ t
G
\ I WPE POL CA

l"ll-li
lll l:;rTld
=Jll |;r-"nf
-
t
llUilc pqr (-)c,.
Yl,*jB?."?.

Fig.3-1- 4D2000BoardLayoul

3-1
51 - AnalogInput SignalType DIP Switch
DIP switchSl, shownin Figure3-2,configuresthe multiplexersfor single-ended or differentialinputsandselectsa
unipolaror bipolarinput volage range.The fint threeswitcheson Sl operateasa group.Whenthesearein the UP
position,themultiplexersareconfiguredfor single-ended inpus; whentheyarein theDOWNposition,themultiplexers
areconfiguredfor differentialinputs.Notethatthesethreeswitchesmustall be setto thesameposition(UP or DOWN)
for the multiplexersto functionproperly.Theremainingswitch,Sl-4, controlsthe input voltagepolarity.Whenthis
switchis in theUP position,theinputvoltagerangeis unipolar;whenit is in theDOWN position,thevoltagerangeis
bipolar.This switch,coupledwith thevoltagerangeselectionseton headerconnectorP9,determines theanaloginput
voltagessupportedby theAID converter.Notethatwheneverthepolarily is changed,theAID convertercircuitry should
be calibratedas describedin Chapter5. The switch settingsareclearly labeledon the board to eliminateerrorswhen
configuringS1.

TYPE POL

1
S.E.

DIFF.
NNEE +l-

Fig.3-2 - DIP SwitchSl

P2 - BaseVO AddressHeader Connector

HeaderconnectorP2 controlsttre 12 computerI/O addresslocationsusedby the board.The baseVO addresslocation
is setby jumperingoneof theeightpositionson theP2 headerconnector.ThebaseI/O address is factory-setto 300hex
(768decimal),wittr thejumper installedacrossthepair of pins fifth from theleft on theconnector.ThebaseI/O address
seuingis fully explainedin Chapter1,"BaseI/O AddressSetting,"andis not repeatedhere.Note theimportanceof this
seningwith respectto thepossibilityof addresscontentionwith otherdevicesin yourcomputer.Be sureto examinethis
possibility if you experienceboardfailure when you first auempt!o operatetheboardin your computer.

P3 - ProgrammableInterval Timer (PIT) VO HeaderConnector

HeaderconnectorP3, shownin Figure3-3, controlsthe programmable intervaltimer @IT). The PIT containsthree
independentl6-bit timer/countercircuits,asdescribedin Chapter2. Eachtimer/counterhasthreeVO signalsassociated
witlr iu a clock, a gats,andan output.P3 canbe configuredin a numberof waysto providemaximumversatilityin
applying this deviceto your particularapplication.Eachtimerrcounteris factory-setfor XTAL clock input, +5V gate
input,andCO output.Figure3-4 showsa block diagramof thePIT.
For easein configuringthis circuitry,the headerconnectoris partitionedinto threefunctionalgroups:TCO,TCl, and
TC2, whichconespondto timer/counter 0, timer/counter1, andtimer/counter2, respectively.Thesedesignations
also
correspondto the manufacturer's designations, asshownon thedatasheetincludedin AppendixC. Sarting from the
top of P3, the first groupof pins on theright sidearelabeledCK0, GTO,andOUTO,the threeI/O signatsfor TCO.The
signalson theleft sidefor TCOarelabeledXTAL, ECO,+5V, EGO,CO0,andC-O0(thissignalhasa barovertop of the
signalnameon theboardastheinversedesigration).Thegroupsof signalsfor TC 1andTC2 areidenticalto TCO,except
that eachhasa CK input on the left sideof the headerconnector.Note thateachsignalnameon the right sideof the
connector(CK, GT, andOUT) spansa groupof two or threepins.Eachgroupcanhaveonly onejumperinstalledat any
time.Thefollowing paragraphs describehow thesesignalscanbe usedin thePIT circuit.An "x" is usedin placeof 0,
1, or 2 in thesignalnameswheneverthe applicationcanbe appliedto any or all of thethreetimer/countercircuits.

3-2
 XTAL
EC0 ls
+5V
EGO ls
co0
cTo
cK1
XTAL
ls
ls
EC1
+5V
EG1
l3
col
co1
cK2 l:
XTAL
EC2 ls
+5V
EG2 ls
c02
c02 ls
Fig.3-3 - PIT l/O HeaderConnectorP3
Counter Inputs:
XTAL - This input to all threetimer/countercircuits is from the 5 MlIz crystaloscillator,labeledYl, locatedin the
upperleftareaoftheboard.By connectingXTAL to theCKxinputontherightsideof theconnectorwithajumperplaced
horizontallybetweenthe pins, the 5 MHz clock is appliedto the timer/countercircuit. If requiredby your application,
theXTAL frequencycanbe changedby installinga differentcrystaloscillaor at Y I . Note, however,that themaximum
frequencyat which the PIT will operateis 8 MHz.
ECx-This inputallowsanexternalclock,otherthantheXTAL signal,to controlthetimingof thecorresponding timer/
countercircuir This pin canbe horizonally jumperedto theCKx input on theright sideof theconnector,in placeof the
XTAL souce. The ECx signals are brought onto the board through externalVO connectorPl5 (seeTable B-3 in
AppendixB).

GateInputs:
+5V - This input, if connectedo theGTx input by placinga jumperhorizontallybetweenthe two pins,placesthe
associatedtimer/countercircuit in an enabledstateat all times.
EGx -This inputcanbehorizontallyjumperedto theGTx inputontherightsideof theconnector!oprovideanextemal
gateinputinsteadof the+5 volts input TheEGx signalsarebroughtontotheboardthroughexternalVO connectorPl5
(seeTableB-3 in AppendixB).

CounterOutputs:
COx - This output canbe horizontallyjumperedto the correspondingOUT pin on the right sideof the connectorso
that theclock outputsignalcanbe routedto externalI/O connectorP15(seeTableB-3 in AppendixB).
CO" - This outputcanbe horizonallyjumperedto thecorrosponding OUT pin on theright sidoof the connectorto
providetheinverseof theclock outputsignalto externalI/O connectorPl5(seeTableB-3 in AppendixB).

3-3
CKx - This input connectstheoutputof onetimer/counterto theclock input of thenexttimer&ounter.CKx is provided
for TCl andTC2 only, andis connecM to theoutputof theprevioustimer/counter(tCO or TCI) by placinga jumper
horizontallybetweenthepins.Theseconnectionsareusedto cascadethe timer/countersfor longertime delaysthanare
supportedby a single timer/countercircuit.

P15 P3 8255PtT
U5
*ro1--kl-
EC0
*sv---Id
EGO t)o
co0 <d
c-ool
o
cKll I
XTALI
EC1
+sv-aQ
EG1
co1 <------rc
co1lo

XTALIO
EC2 t>o
..5y-€
EG2
co2 {-O .4,
to'r-u

Fig. 3-4 - PIT FunctionalBlock Diagram

P4.P5. and P? - Interrupt HeaderConnectors

HeaderconnectorsP4, P5, and F7 are usedto jumper varioussignalsgeneratedby the AD2000 circuitry !o the PC's
interruptchannels.Theintemrptchannelsavailableon theboardareIRQ2 throughIRQ7.Note thatonly oneintemrpt
in thecomputersystemcanbe connectedto an intemrptchannelat any giventime.
Beforeattemptingto useintemrpts,you shouldbe familiar with theprocedurefor initializing the intemrpt vectorsand
thePC's interruptcontroller,andsettingup theintemrpthandlingroutines.Theseprocedures arebeyondthe scopeof
this manual,but mustbe understoodo effectivelyuseintemrptsin you computersysiem.
Be carefulto avoid contentionwhenselectingthe intemrptchannelsused,both with the signalson the AD2000 aswell
aswith otherdeviceswithin your computer.To avoidcontention,usethetableinsidethebackcoverof this manualto
recordttreintemrptchannelsyou usewith theAD2000board.
It is alsovery importantto notethat theAD2000intemrptsourcesareTTL totem-pole(push/pull)typeoutputs;they are
not open-collector. Therefore,do not att€mptto connectoneof theseintemrpb to any otherintemrptoutput.
The following paragraphsdescribethe interruptsavailableon your AD2000 board.

34
P4 - EXTINT and PPI INTRA Interrupts
HeaderconnectorP4 is usedto selectEXTINTorPPIINTRA for connectionto oneof thecomputer'sintemtptchannels
IRQ2 throughIRQ7. EXTINT is providedto accommodatean interrupt signalgeneratedexternalto the AD2000 and
routedontotheboardthroughexternalI/O connectorP15(seeTableB-3 in AppendixB). PPI INTRA (labeledPC3on
theboard)is generatedby thePPI.Thisintenuptis generated
duringPPImode1or mode2 operationonly.Oneof these
two signalscanbejumperedto oneof theavailablecomputerintemrptchannels IRQ2 throughIRQTby firstplacinga
jumperverticallyacrossttrepinsof thesignalchosenandthenplacinga secondjumperverticallyacrossthepinsof the
selectedIRQ channel.Figure3-5 showsheaderconnectorP4with jumpersinstalledsothatPPIINTRA is connected to
RQ2.

F
z
FGI IRQ
xc) ( o t )st
ul o. I\

P4

Fig. 3-5 - Interupt HeaderConnectorP4

P5 - PIT Output Interrupts

HeaderconnectorP5, shownin Figure3-6,is usedto jumperoneof thethreePIT outputs,OUT0,OUTI, or OUT2,to
oneof thecomputer'sintemrptchannelsIRQ2 throughIRQ7.As in the caseof P4, two jumpersmustbe installedto
First,installajumperhorizontallyacrossthepinsof thePlTouput selected.
connectaPlToutputto aninterruptchannel.
Theninstallasecondjumperacross Figure3-6showsjumpeninstalledsothat
thepinsof theintemrptchannelselected.
OUT2 is connectedto IRQ3.

P5 7
6
5
4
3
2
ol
118
21-{

Fig.3-6 - InterruptHeaderConnectorP5

Yl - ND End-of-Convert(EOC)Interrupt
HeaderconnectorP7, shownin Figure3-7,is usedto jumpertheA/D converter'send-of-convert (EOC)signalto one
of thecomputer'sintemrptchannelsIRQ2throughIRQ7.TheEOCsignalis connected to an RQ channelby installing
a singlejumperhorizontallyacrossthepins of theIRQ channelselected.
Figure3-7 showstheEOC signalconnected
ro IRQ4.

3-5
 7
6
5:0
4o
3
2

Fig. 3-7 - InterruptHeaderConnectorP7

P6 - End-of-Convert(EOC)Monitor HeaderConnector
As describedabove,the A/D converterend-of-convert@OC) signalcanbe usedto generatean intemrpL If this signal
isnotusedasanintemrpt,itcanbeusedasastatusmonitoroftheA/Dconversionprocess. HeaderconnectorP6provides
twolinesthroughwhich tleEOCcanbemonitoredfromthePPI,PATorPCT. Oneofthesenvodigitall/Olinesisselected
for EOC monitoringby installingajumper horizontallyacrosstheappropriatepair of pins.The digital VO line selected,
PA7 or PC7, mustbe configuredasa mode0 input (seeChapter4, "ProgrammingYour AD2000"). Figure 3-8 shows
P6 with a jumperinstalledin thefactory-setpositionfor EOC monioring throughPA7.

!
o

!
{

Fig. 3-B- EOC MonitorHeader ConnectorP6

P9 - A/D ConverterVoltageRangeHeaderConnector
HeaderconnectorP9, showninFigure3-9,is usedtoselecttheanalog inputvoltagerangeof theA7Dconverter.Ajumper
is installedvenically acrossthe pins markedlOV to supporta l0-volt range(0 to 10 volts or -5 to +5 vols), or across
thepinsmarked20V to supporta 20-voltrange(-10 to +10 volts).The settingof ttrisjumper,coupledwith thesetting
of DIP switch S14 which selecsa unipolaror a bipolarrange,determinestheinput voltagerangeof theAID converter.
P9 is configuredat the fac[ory accordingto thecustomer'sspecificationsfor theinput voltagerange.The valid seuings
of P9 and Sl-4 are summarizedin the able below:

Range P9 Setting S1-4Setting

-5 to +5 vols lOvGish| DOWNOipolar)

0 to +10 volts lOV (right) LJP(unipolar)
-10 to +10 volts 20V (left) DOWNOipolar)

Fig.3-9- A/D ConverterVoltageRangeHeaderConnectorP9

3-6
 CHAPTER 4

PROGRAMMING YOUR AD2OOO

All communicationwith the AD2000 interfaceboard is done by strobingdata o and from the board using the VO
referenceinstructions.Most operationsinvolve the transferof data to or from the components'internal registers.
However,someoperationsrequireonly that a particularVO addressbe written to; the datawritten is irrelevant.These
VO locationsarereferencedto the AD2000 baseI/O address@A) determinedby thejumper settingof connectorP2.
Chapter1 describesthe baseI/O addressconsiderationsandconfiguration.
The datacollection and supportfunctionsconrolled throughsoftwareincludethe analoginput channelselectionand
gain, control of the ttreA/D conversion,the programmableperipheralinterface,and the programmableinterval timer.
Becausetheyareintegralto thebasicoperationofthe board,theanaloginput channelandgain selectionsandtakingan
A/D readingarecoveredin Chapter1.Digital I/O conrol throughthePPIandcontrolof theprogrammableintervaltimer
aremorecomplex,andare describedin this chapter.
Thedemonstration disk which accompanies your AD2000containexamplesin TurboC, TurboPascal,andBASIC.
Nearly all modemMS-DOS-basedPC languageshaveVO referenceinstructions.Theseare the insructions to control
thedaa ransfers to andfrom theI/O ports.Consultyour programminglanguagereferenceto find theseinstructionsfor
your favorite language.

Selectingan AnalogInput Channel

Seethis sectionin Chapter1.

Settingthe Input Gain

Seettrissectionin Chapterl.

Taking an A/D Reading

Seethis sectionin Chapter1.

Programmingthe ProgrammablePeripherd fnterface

Theprogrammableperipheral interface@PI)hasthreeeight-bitparallelI/O ports,portA, portB, andportC,whichcan
be configuredfor a varietyof applications.ThePPI has16linesavailableat externalVO connectorP15;theeightbis
ofport B (PB0-PB7)areusedfor channelselectionandgaincontrolandcannotbe usedfor otherfunctions.
ThePPI portscanbe operatedin oneof threemodes.The modeof operationandthe signaldirectionof eachport (input
or output)arecontrolledby aneight-bit control word written to aninternalregisler.Two bits definethemodeselection:
mode0, mode 1, or mode2. Four bits configurethe I/O direction:onebit to control PAO-PA7,onebit o control PBG'
PB7,onebit o controlPCO-PC3, andonebit to controlPC4-PC7.PortC is dividedinto two four-bitfieldssothatit can
providestatusandcontrolfor port A if desiredin yourapplication.The controlword is definedin Figure4-1.
ThePPI is configuredby writing a control word to it's intemalconsol register.Upon power-up,all portsarcconfigured
asmode0 inputs.ThePPI is wriuen to duringboardinitialization sothatport B is setup asa mode0 ouput to configure
it for channelselectionand gain control functions.ChapterL, "Initializing Your AD2000," describesthis procedure.
Becausethe PPI canbe configuredfor a wide rangeof operatingmodesandprogrammingrequirements,it is heavily
dependenton conectly understandinghow to usethepropercontrolbyte to configurethePPI for your application.The
demodisk includesexamplepro$ams that showhow to selectthecommonoperatingmodes.Readingthe sourcecode
is highly recommended.
For moreinformation aboutthe operationof thePPI, seethe datasheetincludedin Appendix C.

4-L
 D7 D6 D5lD4lD3lD2lD1lD0
I
GROUPB

PORTC (LOWER)
I = TNPUT
0 = OUTPUT
PORTB
1= INPUT
0 = oUTPUT

MODESELECTION
0 = lvlODE0
1 = [4ODE1

GROUPA

PORTC (UPPER)
1 = INPUT
O= OUTPUT

PORTA
1= INPUT
O= OUTPUT

MODESELECTION
00 = MODE0
01 = MODE1
lX = I/IODE2

MODESETFI.AG
1 = ACTIVE

Fig.4-1- PPIModeDefinition
Format

Programmingthe ProgrammableInterval Timer

The programmable intervaltimer @IQ canbe configuredfor a varietyof timing andcountingfunctions.The PIT's
versatilityis supplemented by theuseof headerconnectorP3 for jumperingvariousI/O options.Chapter3, "Jumper
Settings,"describesthis connector.
ThePlTconsistsofthreeindependent l6-bitdown counters. Thecountersareinitializedforoperationinanyof six modes
by writing datato theappropriatecontrol word for eachcounter.Counterdatais thenwritten to or readfrom eachof the
countersby accessingthree additional internal registers.The datais set up in a two-byte format, eachbyte serially
accessible on the databus.The I/O locationsthatcontrolthePIT arc listedbelowfrom Table 1-2.

PIT FUNCTION A4 A3 A2 A1 AO R/W BA + HEX

0
Counter 1 0 1 0 0 R/W 14
1
Counter 1 0 1 0 1 R/W 15
2
Counter 1 0 1 1 0 R/W 16
ControlWord 1 0 1 1 1 W 17

4-Z
Your specificrequirementswill determinehow the individualtimer/counters shouldbe conhgured.The datasheet
includedin AppendixC providestheinformationrequiredto controlthepIT.
Thesoftwareincludedon thedemodisk showsexampleprogramsfor controllingsomeof thePIT operatingmodes.In
addition,sometypical applicationsarepresentedin theprogrammableinterval timer applicationnotesin AppendixD.
Includedare examplesrequiring two or morecouniersto be cascaded.
Thesignalsgenerated by theOUT pinsfor anyof thecountersmaybe connected to oneof thePC's intemrptchannels
usingjumpersinstalledatconnectorP5. Referto the"HardwareIntemrpts"sectionbelowfor moreinformationon using
theOUT signalsto generateintemrpts.

HardwareInterrupts
Threejumper connectors,P4, P5, and P7, are provided on the AD2000 to enableintemrpts generatedby the A/D
converter,thePIT,thePPI,andanexternalsourcetothePC'sintemrptchannels IRQ2throughIRQ7.Chapter3,"Jumper
Settings,"explainshow theseheaderconnectorscanbe configured.
Beforeyou attemptto useinterrupts,be sureyou arefamiliar with ttreprocedurefor initializing theintemrpt vectorsand
thePC's interupt controller,andseuingup theintemrpt handlingroutines.ReferenceI in AppendixE providesa good
descriptionof thePC's systemintemrpts.

A"/DConverter End-of-Convert(EOC) Signal

TheA/DconverterEOCsignalcanbeusedtogenerateanintemrpttothePC. Anintemrptwilloccur(throughtheselected
interruptchannel)to indicatea conversionis completeapproximately20 microsecondsafter theconversionis initiated.
The EOC signal is inverted before being applied to the intemrpt channel.It makesa low-to-high ransition at the
completionofeachconversioncycle,andremainshighuntilanotherconversionisinitiated. ThetimingoftheEOCsignal
is shownin Figure2-2,Chapter2.

PPI Interrupts
ThePPIINTRA(PC3)intenuptgeneratedinPPl model andmode2operationcanbejumperedtoanyof thePCintemrpt
channelsIRQ2 throughIRQ7. Thetiming of this intemrptis shownon thePPI datasheetincludedin AppendixC.
ThePPI intemtpt mustbe enabledby writing a "1" to the INI|E maskbil of thePPI asdescribedin the datasheetunder
"Intenupt,ControlFunctions."The INTE maskbit is disabledduringpower-upresetand wheneverthe PPI modeis
changed.

PIT Interrupts
One of ttreOUT0, OUTI, or OUT2 signalsgeneratedby the PIT can be jumperedto a PC intemrptchannelusing
connectorP5.
When usinga PIT OUT signalasan intemrpt"you mustbe very carefulto ensurethat the PC system'sprogrammable
interruptcontroller@IC) is properlyconfiguredto ignoreintemrptson the selectedintemrptchannelimmediatelyafter
power-up.This is necessarybecausethePIT mustfirst be initialized to define the desiredmode(s)of operation. Prior
to initialization,themode,count,andoutputof all countersareundefined.If thesysteminterruptsarenot disabled,the
counteroutputsmay causeerraticsystembehavior.

4-3
44
 CHAPTER5

CALIBRATION PROCEDURES
This chaptercontainscalibrationproceduresfor theA/D converterinput voltagerangeandtheA/D convertergain.The
offsetandfull-scaleperformance of theAD2000A/D converteris factory-calibrated
accordingto thespecifications
that
weregivenwhenyourorderwasplaced.Thegaincircuitryis alsofactory-calibrated beforetheboardis shipped.The
following procedureallows you to quickly verify the accuncy of thesecircuits.This procedureshouldbe done
approximately everysix months,wheneverinaccuratereadingsaresuspected, or whenevertle voltagerangeis changed.
Calibrationis performedwith a properlyconfiguredAD2000installedin thePC.Apply powerto thecomputerandallow
the AD2,000circuitry to stabilizefor 15 minutes.

RequiredEquipment
The following equipmentis requiredfor calibration:
. hecision VoltageSource:0 to +10 volts
. Digital Voltmeter: 5-U2 Ctrgit
. SmallScrewdriver(for aimpot adjustment)
Figure5-I showstheboardlayout.Thetrimpotsreferencedin thefollowing proceduresaregroupedin theupperleft area
of the board.

Fig.5-1 - AD2000BoardLayout

A/D Calibration
During this procedure,connectionsmustbe madeto someof theanaloginpus on externalI/O connectorP8, available
at the rearpanelof thecomputer.The pin assignments for this connectoraregivenin TableB-2, AppendixB.
Two adjusrnentsarenecessaryto completelycalibratetheA/D converterfor unipolaror bipolar operation.Theseaffect
theoffsetandfull-scaleperformance of theAD2000circuiry. BothcalibrationstepsareperformedusingtrimpotsTR5
and TR6 or TR6 and TR7. Trimpot TR5 or TR7 is used!o zerothe offset error of the A,/I) converterand trimpot TR6
is usedfor full-scaleadjustment.In thefollowingprocedure,useanaloginputchannel1 andsetit for a gainof 1. This

5-r
is accomplished by writing all zeroesto I/O addresslocationBA + l. Be certainttratposition4 of switch51 is setfor
the desiredpolarity and thejumper on connectorP9 is setfor l0V.

Unipolar Calibration
Two adjustments arenecessary to calibratetheA/D converterfor theunipolarvoltagerangeof 0 to + l0 volts,onefor
offsetandonefor full scale.To adjusttheoffset,a very low analoginputvoltage,shownunderthe "Offset"headingin
the following table,is connectedto thechannelI input of themultiplexer@8-1).Thegroundreferenceof this signal
shouldbe connectedto P8-2.While continuouslydisplaying12-bitA/D conversions, adjustTR7 until the AID data
flickersbetweenthe two valueslistedin the tableunder"Offset."
After theoffsetadjustmentis made,TR6 is usedo adjustthefull-scalevalue.While thefull-scaleinput voltagelisted
in the tableis not the actualfull-scalevoltagefor an ideal0 to +10 volt range,it is ttremaximumvoltageat which the
A/D conversionis guaranteedo be linear.Any valueabovethis voltagemaynot belinearandthusmayadverselyaffect
calibration.After connectingthe full-scale voltagelisted in the table to the channel1 input, adjustTR6 until the data
flickersbetweenthe two valuesin theable under"Full Scale."

UnipolarCalibration
(0 to +10voltsranqe)
Offset(TRn Full Scale(TR6)
Inout Volaee +1.22070millivolrs +9.49829volrs
A/D Data 000000000000 1 1 1m
1 l10010
00m m00 0001 1110 10110011

Bipolar Calibration
Whetheryou areselectingthebipolarinputvoltagerangeof -5 to +5 voltsor - l0 to + 10vols, thefollowingcalibration
procedurecanonly be performedwith theboardconfiguredfor a -5 to +5 volt input voltagerange.This meansthat the
jumperonheaderconnectorP9 mustbeinstalledacross thel0Vpins.If youareusing0re -10to+10voltrange,reposition
the jumper on P9 acrossthe 20V pins after you perform the calibrationproceduresbelow.
Two adjustmentsarc necessaryo calibratethe A/D converterfor bipolar voltageranges,onefor offset andonefor full
scale.To adjusttheoffset"connectthevoltageshownundertle "Offset"headingin thetablebelowto thechannelI input
of the multiplexer.While continuouslydisplayingl2-bit AID conversions, adjustTR5 until thedaa flickersbetween
thetwo valueslistedin thetableunder"Offset."Next,connectthefull-scalevoltagelistedin thecableto thechannelI
input andadjustTR6 until thedataflickersbetweenthetwo valuesin thetableunder"Full Scale."

Bipolar Calibration
(-5 to +5 volts or -10 to +10 voltsranse)
Offset ffR5) FuIl Scale(TR6)
Inout Voltaee 4.99878vols +4.99634volts
A/DDaa 0m 00000000 1 1 1 1l l 1 1 l l 1 0
000000000001 1 1 1 11 1 1 11 1 1 1

Table5-1providesa referencefor theidealinput voltagefor theA7Dconverterfor eachbit weightin eachvoltagerange.

This tableshowsilre idealfull-scale(all ones)valuein thefirst line anddecrements
by onebit weighteachline thereafter.
Note that thesevaluesarefor l2-bit AID conversions,andarenot valid whenusingtheconverterto performmorerapid
eight-bitconversions. Note that thevoltagevaluesin thetablearein millivols.

5-2
 Table5-l - A/D ConverterBlt Welqhts
fdeal Innut Voltace (millivolts)
A/D RitWeisht +5 Volts +10 Volts 0 to +10 Volts
4095(Full-Scale) +4997.6 +9995.1 +9997.6
2M8 0000.0 0000.0 +5000.0
rgu -2500.0 -5000.0 +2500.0
5t2 -3750.0 -7500.0 +1250.0
256 4375.0 -8750.0 +625.00
r28 4687.5 -9375.0 +312.50
& 4M3.8 -9687.5 +156.250
32 492r.9 -9843.8 +78.125
16 49ffi.9 -992r.9 +39.053
8 4980.5 -99ffi.9 +19.5313
4 49n.2 -9980.5 +9.7656
2 4995.t -99W.2 +4.8828
I 4997.6 -9995.r +2.4/.14
0 -sO(n.0 -10m0.0 0.0000

Gain Circuitry Calibration

Fourrimpots,TRl throughTR4,areusedto adjustthegaincircuitry,oneforeachof thegains2,4,8, and16.To calibrate
this circuiry, applyan input voltageof +39.063miltvolrs o theinputof channel1.Next,by writing thecorrc,ctword
to ttre BA +1 I/O location,set the gain to 2 and adjusttrimpot TRl to obtainthe 12-bit A/D converteroutput for your
board's voltagerange,aslisted in Table 5-2. Then,repeatthis procedurefor eachof the remainingthreegain settings,
adjustingthe appropriaterimpot until achievingthe correctvalue listed in the table.

Table 5-2- A/D ConverterReadinqsfor Galn Callbrallon

Inout VoltaeeRange
Gain Trimpot +5 Volts +10 Volts 0 to +10 Volts
2 TRl 100000100000 100000010000 000000100000
4 TR2 100001000000 100000100000 000001m 0000
8 TR3 100010000000 100001000000 000010000000
l6 TR4 10010000m00 100010000000 000100000000

5-3
54
 APPENDIX A

AD2OOO
SPECIFICATIONS
 AD2OOO
SPECIFICATIONS
(TypicalN25"C)

Interface: IBM PC/XT/AT compatible

Jumper-selectable
baseaddress,VO mapped
Jumper-selectable
intemrpts

Analog Inputs: 8 differential or 16 single-endedinputs,switch-selectable

Input impedance, eachchannel ..... >10 megohms
Gains,softwareselectable 1,2,4,8, or 16
Gainerror 0.5Votyp, lvo max
Input options: l0-volt range*(Option1)..........Bipolar+5V
Guaranteed Linearity...............+5V
l0-volt range*(Option2) ..........Unipolar0 to +l0V
Guaranteed Linearity...............
0 to +9.5V
20-voltrange*(Option3)..........Bipolar+10 V
Guaranteed Linearity...............19.5V
Range.......... ..........Jumper-selectable
Polarity Switch-selectable
Settlingtime ............ .3 psecmax
Commonmodeinputvoltage ........+10V
Overvoltageprotection t35 Vdc
*Erratic readingscan occurbeyondspecifiedinput voltagerilnges.

A"/DConverter: Type............ Successive approximation

Resolution: 10-voltrange ........lzbitsQ.44 mVlbit)
2O-voltrange ........12birs (4.88mVlbit)
Chip-selectable conversionspeed: Option0 .... 20 Usectyp,25 trec max
Option | .... 12 psecqrp, 15psecmax
Option2 ....8 psectyp,9 psecmax
Linearity tl bit typ
Sample-and-hold acquisitiontime .6 Fsecmax
Throughput kHz
...............38

Counter/Timer: Three l6-bit, 8 MHz down counters

Digital UO Lines: 16TTL/CMOS-compatible

MiscellaneousI/Os: +12V, +5V, PC bus-sourced

Ground,PC bus-sourced
Oneextemalintemrptinput

Power Requirements: +5 Volts 260 mA

+12 Volts 30 mA
-12 Volts 35 mA

VO Connectors: Two 40-pin box headers(onededicatedto analogsignalsonly)

All 80 signalsexit throughonerearpanelslot in thePC

A-l
 Operatingtemperature 0 to +70oC
Storagetemperature. . -40 to +85"C
Humidity..... 0 tn %)Vonon-condensing

Size: Height .. 3.875"(99 mm)

Width.......... 5.50"(140mm)

A-2
 APPENDIX B

CONNECTOR PIN ASSIGNMENTS

 CONNECTOR PIN ASSIGNMENTS

Table B-l-Mating External IiO Connectorsfor P8 and P15

Connector No. Manufacturer Part Number

P8 3M yr1-7M0
P15 Mil c-83503 M8?sOit-os

Table B-2-P8 Connector Pin Assignments

Pin No. Signal Name Pin No. Signal Name

DIFF / SE
I AINI+ / AIN1 2 GND
J AINI- / AIN9 4 GND
5 AIN2+/ AIN2 6 GND
7 ArN2- / AIN10 8 GND
9 AIN3+ / AIN3 l0 GND
11 AIN3- / AINI1 t2 GND
r3 AIN4+ / AIN4 t4 GND
15 AIN4- / AIN12 r6 GND
T7 AIN5+ / AIN5 l8 GND
19 AINs- / AIN13 20 GND
2r AIN6+ / AIN6 22 GND
23 AIN6- / AINI4 24 GND
25 AINT+ / AINT 26 GND
27 AINT- / AINI5 28 GND
29 AIN8+ / AIN8 30 GND
3l AIN8. / AINI6 32 GND
JJ N.C. 34 GND
35 N.C. 36 GND
JI +12 VOLTS 38 GND
39 .12 VOLTS 40 GND

B-1
 Table B-3-PI"5 Connector Pin Assignments

Pin No. Signal Name Pin No. Signal Name

I GND 2 EXTINT
3 PA7 4 PA6
5 PA5 6 PA4
7 PA3 8 PA2
9 PAl l0 PAO
11 GND t2 GND
13 PC7 t4 PC6
15 PC5 l6 PC4
I7 PC3 l8 PC2
19 PC1 20 PC0
2l GND 22 GND
23 EXTCLKO 24 EXTGATEO
25 CLKOUTO/CLKOUTG 26 GND
27 EXTCLKl 28 EXTGATEl
29 CLKOI-]"TI/CLKOUTI. 30 GND
31 EXTCLK2 32 EXTGATE2
33 CLKOUT2 / CLKOUT2- 34 GND
35 +5 VOLTS 36 +5 VOLTS
37 GND 38 GND
39 +12 VOLTS 40 -12 VOLTS

B-2
 APPBNDIX C

COMPONENT DATA SHEETS

Intel82C55AProgrammable
Peripheral
lnterface
DataSheetReprint
intel' 82C55A
INTERFACE
PERIPHERAL
CHMOSPROGRAMMABLE
I Compatiblewith all Intel and Most I Control Word Read-BackCapability
Other Microprocessors I Direct Bit Set/ResetCaPabilitY
r High Speed,"Zero Wait State" . 2.5 mA DC DriveCapabllltyon all l/O
Operationwith 8 MHz8086/88and Port OutPuts
80186/188
r AvailableIn 40-PinDIP and 44'PinPLCC
a 24 Programmablel/O Plns
r Availablein EXPRESS
t Low PowerCHMOS - StandardTemperatureRange
r CompletelyTTL ComPatible - ExtendedTemperatureRange
The Intel 82C55Ais a high-performance, CHMOSversionof the industrystandard8255A generalpurpose
lt provides
programmablel/O devicewhich is designedfor use with all lntel and most other microprocessors.
Zq ltO pinswhichmay be individuallyprogrammedin 2 groupsot 12 and used in 3 majormodesof operation.
The 82C55Ais pin compatiblewith the NMOS8255Aand 8255A'5.
ln MODE 0, each group of 12 llo pins may be programmedin sets ol 4 and 8 to be inputsor outputs.In
MODE1, eachgroupmay be programmedto have8 linesof inputor output.3 of the remaining4 pinsare used
for handshakingand interruptcontrolsignals.MODE2 is a strobedbi-directional bus configuration.
The 82C55Ais fabricatedon Intel'sadvancedCHMOSlll technologywhich provideslow powerconsumption
with performanceequalto or greaterthan the equivalentNMOSproduct.The 82C55Ais availablein 40-pin
DIP and 44-pinplastic teadedchip carrier (PLCC)packages.

teI r I r I I r i ttt

cs ltsET
dD 0o
Al I D'
N l0
7C' It
rc NC
Po6 0a
rc5 l4 03
PAl t5 o5
t6 o7
tt

PPFEE9FiEFE
}EClaB'IG

231256-1
Flgure1.82C55ABlock Diagram

231256-2
Pinout
Figure2.82C55A
Diagramsare lor pin relerence only. Package
siz€s ar€ not to scale.

S.ptcmbcr 19t7
3-124 Ordcr llumbcn 23 | 2564o.4
 82C55A

Table 1. Pln
Symbol PlnNumber
Dlp Type Nameand Function
PLCC
PAg-o 1-4 2-5 t/o POFT A, PINS0-3: Lowernibbleof an 8-bitdata outputlatch/
butferand an 8-bitdatainputlatch.
m 5 6 I READCONTROL: Thisinputis lowduringCpUreadop€rations.
m 6 7 I CHIPSELECT: A towon thisinputenables the82C5SA to
respondto RE andWFIsignals.ffi andWRareignored
otherwise.
GND 7 8 SystemGround
Ar-o 8-9 9-10 ADDRESS: Theseinputsignals, in conjunction
F-DandWF[,
controltheselectionof oneof thethreeportsor thecontrol
wordregisters.
A1 As m wF' cs InputOperatlon(Read)
0 0 0 1 0 PortA-DataBus
0 1 0 1 0 PortB-DataBus
1 0 0 1 0 PortC-DataBus
I 1 0 1 0 ControlWord- DataBus
OutputOperatlon(Wrlte)
0 0 1 0 0 DataBus- PortA
0 1 1 0 0 DataBus- PortB
1 0 1 0 0 DalaBus- PortG
1 1 1 0 0 DataBus- Control
DisableFunctlon
x X X X 1 DataBus-3-State
X X 1 1 0 DataBus-3-State
Pcz-l 10-13 11.13-15 vo PORTC, PINS4-7: Uppernibbleof an 8-bitdataoutputlatch/
butfer and an 8-bit data input butfer (no latch for input).This port
can be dividedinto two 4-bit ports underthe mode control.Each
4-bit port containsa 4-bit latch and it can be used for the control
signaloutputsand statussignalinputsin conjunctionwith ports
A and B.
PCo-g 14-17 16-19 t/o PORTC,PINS0-3: Lowernibbteof portC.
PBo-z 18-25 20-22, uo PORTB, PINS0-7: An 8-bitdataoutputlatch/butferand an g-
24-28 bit data input butfer.
Vee 26 29 SYSTEMPOWER:* 5V PowerSuppty.
Dz-o 27-34 30-33, t/o DATABUS:Bi-directional,tri-statedatabuslines,connectedto
35-38 systemdatabus.
RESET 35 39 RESET: A highonthisinputclearsthecontrotregisterandall
portsaresetto theinputmode.
wF' 36 40 WRITECONTROI,.:
Thisinputis towduringCpU write
operations.
PAz-a 37-40 41 -44 tlo PORTA, PINS4-7: Uppernibbleot an 8-bitdataoutputtatch/
butferandan8-bitdatainputlatch.
NC 1,12, No Connect
23,34

3-125
intet 82C5sA
DESCRIPTION
82C55AFUNCTIONAL
General
The82C55Ais a programmable peripheral
interface
devicedesigned for usein Intelmicrocomputer sys-
tems.lts function is that of a purpose
general l/O
component to interfaceperipheralequipment to the
microcomputer systembus.The functional configu'
rationof the 82C55Ais programmed by the system
softwareso that normallyno externallogicis neces-
saryto interfaceperipheraldevicesor structures.
DataBue Buffer
butferis usedto inter'
This3-statebidirectionalS-bit
face the 82C55Ato the systemdata bus' Data is
transmittedor receivedby the bufferuponexecution
of inputor outputinstructions by the CPU.Gontrol
words and statusinformationare also transferred
throughthe databusbutfer.
Read/Wrlteand ControlLoglc
The functionof this block is to manageall of the
internaland externaltransfersof both Data and
Gontrolor Statuswords.lt acceptsinputsfromthe
CPUAddressandControlbusses andin turn,issues
commandsto bothof the ControlGroups.
GroupA and GroupB Controlg
The functionalconfigurationof each port is pro-
grammedby the systemssottware.In ossence,the
OPU"outputs"a controlwordto the 82C55A.The
controlwordcontainsinformation suchas "mode",
lhe func'
"bit set", "bit r€sot",etc.,that initializes
tionalconfiguration of the 82C55A.
3-126
Each of the Controlblocks (GroupA and Group B)
accepts"commands"from the Read/WriteControl
Logic, receives "control words" from the internal
data bus and issuesthe propercommandsto its as-
sociatedports.
ControlGroupA - PortA and PortC upper{C7-O4l
ControlGroupB - Port B and PortC lower(C3-C0)
The control word register can be both written and
read as shown in the addressdecode table in the
pin descriptions.Figure6 shows the control word
format for both Read and Write operations.When
the controlwordis read,bit D7 will alwaysbe a logic
"1", as this impliescontrolword mode information.
Ports A, B, and C
The 82C55Acontainsthree8-bitports(A, B, and C).
All can be configuredin a wide varietyof functional
characteristicsby the system softwarebut each has
its own special features or "personality" to further
enhancethe powerand flexibilityof the 82C55A.
Port A. One 8-bit data output latch/butter and one
I'bit input latch butfer. Both "pull-up" and "pull'
down" bus hold devicesare presenton Port A.
Port B. One 8-bit data input/outputlatch/butfer'
Only "pull-up"bus hold devicesare presenton Port
B.
Port C. One 8-bit data output latch/bufferand one
8-bit data input bufler (no latch for input).This port
can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4'bit latch and it
can be used for the control signaloutputsand status
signalinputsin conjunctionwith portsA and B. Only
"pull-up" bus hold devicesare presenton Port C'
for
See Figure4 for th€ bus-holdcircuitconfiguration
Port A, B, and C.
intef 82C55A

m
il

te&l

231256-3
Flgure3.82C55ABlock DlagramShowlngDataBuaBuffer and Read/WrlteControlLogtcFuncilong

I'{TEFI{AL
oATA ll{

IiITgRNAL
o^t (xrr

SITEFIIAL
OATA

'NOTE: wn
231256-4
Port pins loecledwith morethan 20 pF capacitanc€may nol havetheir logic level guaranteed following a hardwaro reset.

Flgure4. Port A, B, C, Bus-holdConfiguration

3-127
 intef 82C55A

DESCRIPTION
82C55AOPERATIONAL coartFoLwonD

o, or D6 oa o2 Dl oo
ModeSelectlon
that can
J
Thereare threebasicmodesof operation
be selectedby the systemsottware:
Mode0 - Basicinput/outPut / oiolr! \
Mode1 - StrobedInPut/outPut
Mode2 - Bi-directionalBus foRTc tKncnl
l. lxPul
0.oUlruT
Whentheresetinputgoes"high"allportswillbe set
to theinputmodewithall24 portlinesheldat a logic foel 3
"one" levelby the internalbus holddevices(see t . lt{PUT
0. OUttUT
Figure4 Note). After the reset is removsdthe
82C55Acanremainin the inputmodewithno addi' XODEEELEC'IOII
0. li{)OC0
Thiseliminates
required.
tionalinitialization the need I . l,lOOEI

for pullupor pulldowndevicesin "all CMOS"de'

signs.Duringthe execution of the systemprogram'
anyof the othermodesmaybe selectedby usinga / oFott ^ \
single output instruction.This allows a single
82C55Ato servicea varietyof peripheraldevices foit c rtttcil
! .lt{'uf
with a simplesoftwaremaintenance routine. 0. OUTruT

The modesfor PortA and PortB can be separately tont a

I . ItitttT
defined,whilePortC is dividedintotwo portionsas 0.OutruT
requiredby the PortA and PortB definitions.All of X(DE 3:LECTlOltl
the outputregisters,includingthe statusflip'flops, O. rrcOl0
O! . |IODE t
willbe resetwhenever the modeis changed. Modes tX.r|OE 2

maybe combinedso that theirfunctionaldefinition

can be "tailored"to almostany l/O structure.For
instance;GroupB canbe programmed in Mode0 to TODEECTFLA6
monitorsimpleswitchclosingsor displaycomputa' l. ASTIVE

tional results,Group A could be programmedin

Mode1 to monitora keyboardor tapereaderon an 231256-6

basis.
interrupt-driven
Flgure 6. Mode Deflnltlon Format

The mode definitionsand possible mode combina'

tions may seem confusingat first but after a cursory
review of the complete device operation a simple,
logical l/O approachwill surface.The design of the
82b55A has taken into account things such as etfi'
cient PC board layout,control signaldefinitionvs PC
layout and complete functional flexibilityto support
almost any peripheraldevice with no extemal logic.
Such design repr€sents the maximum use of the
availablepins.

SlngleBlt Set/RegetFeature
Anyof the eightbits of PortC can be Set or Reset
usinga singleOUTputinstruction. This featurere'
ducessotware requirements in Gontrol'basedappli'
cations.
231256-5 WhenPortC is beingusedas status/controllor Port
A or B,thesebitscanbe setor resetby usingtheBit
andBus
5' BasicModeDefinltions Set/Resetoperationiustas if theyweredataoutput
:.::,-
F.-.r\r-
- -.-.Iigli" lnterface ports.

3-128
intef 82C55A

oot{taot wotD InterruptControlFunctlons

Whenthe 82C55Ais programmed to operatein
mode1 or mode2, controlsignalsareprovided that
canbe usedas interrupt requestinputsto the CPU.
Theinterruptrequ€stsignals,generated fromportC,
can be inhibitedor enabledby settingor resetting
theassociated INTEflip-flop,usingthe bit set/reset
tunctionof portG.
Thisfunctionallowsthe Programmer to disallowor
allowa specificl/O deviceto intenupttheCPUwith-
outatfectinganyotherdevicein the interruptstruc-
ture.
fNTEflip-flopdefinition:
231256-7
(BIT-SETFINTEis SET-Interruptenabte
(BIT-RESET)-INTEis RESET-tntenuptdisabte
Flgure7. Blt Set/ResetFormat
Note:
All Mask flip-flopsare automatically
reset during
modeselection anddeviceReset.

3-129
intet
operailngModes Mode0 BasicFunctional Definitions:
portsandtwo 4-bitports'
Mode0 (BastcInput/output).Thisfunctionat con- :o l:o
figurationprovideisimple'inputano outputopera- AnY-t^o't
portcanbe inputor output'
tionsfor eachof the three ports.No "handshaking" r Outputsare latched.
is required,data is simplywrittento or readfrom a . Inpirtsare not latched.
specified port'
o 16 ditferentInput/output are pos-
configurations
siblein thisMode.

MODE0 (BASTCINPUT)

231256-8

MODEo (BASTC
OUTPUT)

231256-9

3-130
 A B GROUPA GROUPB
Da D3 D1 D6 PORTA PORTC PORTC
(UPPER) # PORTB
GOWER)
0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT
0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT
0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT
0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT
0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT
0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT
0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT
0 1 1 1 OUTPUT INPUT 7 INPUT INPUT
1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT
1 0 0 1 INPUT OUTPUT I OUTPUT INPUT
1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT
1 0 1 1 INPUT OUTPUT 11 INPUT INPUT
1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT
1 1 0 1 INPUT INPUT 13 OUTPUT INPUT
1 1 1 0 INPUT INPUT 14 INPUT OUTPUT
1 1 1 1 INPUT INPUT 15 INPUT INPUT

MODE0 Gonliguratlons
ooNrnot i,oio r0 GOfT|TROLWORO a2

coflTFor Yronotr
D, Da Oi O. O: Dr Or

3-131
 o, o. 05 o. ot o, or Do

cor|'iot roFD a6 coxtRoL fi)ioae

coirrRol rroiD r c(xttoL xoRo rto

o, oa o, D. ot Dr Dr oo

I o 0 0 0 0

coilnot tono aT oot{lRol troio art

o, oc or o. o! D, or Do

0 0 0 I

3-132
inbf 82C55A

IIODE0 ConllguraUona(Continued)

co,llnol woRorta
o, oa or o. Dt D: Or Oo Dr 03 03 O. Dr Or Or Oo

rl0l0lllll0ltl0

ooxttol irotD tt! oofl?tol totD att

Dr%DrDrDlD2DrOo o, or Dr O. D: Dz Dr Do
rl0l0lrlrl0l0lr
ffi

Mode1 BasicfunctionalDefinitions:
Opcretlngtodcr
o Two Groups(GroupA and GroupB).
ilODE 1 (Strobed Input/Output).This functional o Eachgroupcontainsone8-bitdataportandone
configurationprovidesa meansfor transferringl/O 4-bitcontrol/dataport.
datato or from a specifiedport in coniunction
with
strobesor "handshaking" o The 8-bitdataport can be eitherinputor output
signals.In mode1, PortA
and Port B use lhe lineson PortC to generateor Bothinputsandoutputsare latched.
acceptthese"handshaking" signals. r The4-bitportis usedfor controlandstatusof the
8-bitdataport.

3-133
intef 82C554

InputControlSlgnalDeflnltlon
STE (strobe Input). A "low" on this input loads
dataintothe inputlatch. coiltaol woiD
Dr Dr Or O. D, 02 D! DO I trtE !
m^
Li- .i
IBF(lnputBufferFullF/F) tQ.r t!F^

t . ltatt l
A "high"on this outputindicates thatthe datahas 0. OUttUt
beenloadedintotha inputlatch;in essence, an ac- |l{tR^
knowledgement. IBF is set by STBinpg!beinglow RD
and is resetby the risingedgeof the RD input.
r/o

INTR(lnterruptRequest) mE r t;oiYll

A "high" on this outputcan be usedto interruptthe

CPUwhen an inputdeviceis requesting service' o, o: Dt Do r--'1
INTRis set by the STEis a "ono", IBFis a "on6" I IT?E I
It Tr -i - ,
3ll.

andINTEiEa "one". lt is resetby thelallingedgeol t_ ||Fr

FT. nris procedureallowsan input deviceto re-
quest servicefrom the CPUby simplystrobingits
dataintothe port. ItT\

INTEA
Controlledby bit set/resetof PCa.
INTEB 231256-13

Controlledby bit set/resetof PC2.

Flgure8. MODE1 Input

l|t

It

txtt

ntr?lc- - -
tttfiStal

231256-14

Flgure f. ilODE I (Strobcd InPut)

3-134
intef 82C55A

OutputControlSlgnalDeflnltlon
OBF(OutputBuffer Fuil F/F). TheOEFoutputwitl
go "low" to indicatethat the CPUhas writtendata ooirraol roto
outto the specifiedport.The6EF ptp wiil be set by
the risingedgeof the WF inputand resetby ER cf^
Inputbeinglow. r_- 1
I lillE I
tal &-x^
l---J
ffi (AcfnowledgeInput).A "low" on this input
informsthe 82C55AthatthedatafromPortA or port ltfTRa
B hasbeenaccepted. In essenc€,
a response from
the peripheral
deviceindicatingthat it hasreceived
the dataoutputby the CPU.

INTR(lnterruptRequest).A "high"'onthis output

can be usedto int€nuptthe CPUwhen an output
devicehas accapteddatatransmittedbv the CpU. oorniolf,oiD

INTRis set wh€nffi is a "one",OgF--is a "one" ilh

andINTEis a "one".lt is resetby thefallingedgeof
wF. ec
INTEA
rrri|
Controlledby bit set/res€tot pC6.
INTEB
Controlledby bit set/resetof PC2.
231256-15

Flgure10.MODEI Output

231256-16

Flgurell.llODE 1 (StrobedOutput)

3-13s
int€f 82C55A

of MODE1
Comblnatlons
definedas inputor outputin Mode 1 to supporta wide varietyof strobed
PortA and Port B cbn be individually
l/O applications.

?ar'?\

?c. rc7

?c! fc.
OONTBOLv,OFD

fca tc!

Er.r

?srto

?cr .rt
Fcl |lfr

,!co tNlR!

IOiTA-ISTROIEDINPU?I toi? A - tstRoaEDouTPutl

aoRrI - ls?RoeEo
ourrurl roRTs -tsrno6Eorl|rurl

231256-17

of MODE1
Flgure12.Comblnatlons

Operatlng Modes OutputOperatlons

ltlODE 2 (Strobed Bidlrectlonal Bus l/O).This
functional configurationprovidesa means for com'
municatingwith a peripheraldevice or structureon a
single 8-bit bus for both transmittingand receiving
data (bidirectionalbus l/O). "Handshaking"signals
are providedto maintainproperbus flow disciplinein
a similar mannerto MODE 1. Interruptgeneration
and enable/disablefunctionsare also available.
6'F (OutputBulter Full).TheOBF-outputwill go
"low" lo indicatethat the CPUhaswrittendataout
to portA.
AC-K(lctnowledge).A "low" on thisinputenables
the tri-stateoutputbutlerof PortA to sendout the
data.CIherwise, theoutputbutferwillbe in the high
impedance state.

MODE2 BasicFunctionalDefinitions: INTE 1 Ohe INTE Flip-Flop Associated wlth

o Used in GroupA only. O-BF).Controlledby bit set/resetof PC6.
r One 8-bit,bi-directional bus port (PortA) and a 5'
bit control port (Port G). Input Operatlons
o Both inputsand outputsare latched.
SF (StroueInput).A "low" on this inputloads
o The S-bitcontrolport (PortC) is used foi control dataintothe inputlatch.
and status for the 8-bit, bi-directionalbus port
(PortA). IBF(lnputBufferFullF/F).A "high"on thisoutput
indicatesthat data has been loadedinto the input
latch.
Bldirectional Bus l/O Control Signal Deflnltion
INTR(lnterrupt Request).A highon this outputcan
INTE2 (Ihe INTEFlip-FlopAssoclatedwlth IBF).
by bit set/resetof PCa.
Controlled
be usedto interruptthe CPUfor inputor outputoper'
ations.

3-136
 int€f 82C55A

ooiltRot vfoRD

o, D. D! O:

oo-^

ffi^

toaY I
1 .INArT
0 - OUTTUT m^
tSFa
GhOT'BNODE
0'rrcDt 0
I - IrOOEI
231256-18
tlo

Flgure13.MODEControtWord
231256-19

Flgure14.MODE2

D t^tror
c?uto tzctta

rcr

str

tBf

ttit?HtnaL
Bts

lln

oallfH or?a tlol

tcftrartial roarc..l aro|.a ro tgtfircr^r

Figure 15.MODE2 (Btdtrec$onat)

NOTE:
Anysequenceqherewfugcurs beforerER, :ld sTEgccursbeforeHDis permissibte.
(INTR: IBFo Niffi. STB-.FD + 6EF.IiIR o [fi r ffi;

3-137
intef 82C55A

MOOE2 AND MOOEO (INPUT} MODE2 AND MODEO (OUTPUTI

tlri^ rcr

tar,t\

6?^ rg cf^

oarxTtoL toiD E-q q 7m^

DrDrQD.DrDrDtOo 4DrOsD.DtDrOrDo
-aT!^
F-B^ lc.

|lF^ q t!t^

rr'o Er. r,lt

tBr+i!

MOOE2 ANO MODE I (OUTPUT} MODE 2 AND MOO€ 1 (INPUT}

r+.t\

|c? 6-f^
fc' 5-r^
?cr -i^ tcr E-r^

fc. ;fr. lc. 6^

tcr llt^ tct lttr

tt tB! tE".tq

lcr ilFr fc,

RO iE-r lct

tn tit?hr fco

Figure 16.i/IODE1ZCombinatlons

3-138
intef 82C55A

ModeDeflnltlonSummary
MODEO MODE1 MODE2
!N OUT !N OUT GROUPA ONLY
PAo I N OUT IN OUT
PAr IN OUT IN OUT
PAz I N OUT IN OUT
PAg IN OUT IN OUT
PAa IN OUT IN OUT €
PAs IN OUT 1N OUT
PAo tN OUT IN OUT
PAz IN OUT IN OUT
PBo IN OUT IN OUT
PBr IN OUT IN OUT
PBz IN OUT IN OUT
MODEO
PBs IN OUT IN OUT
OR MODE1
PBa IN OUT IN OUT
ONLY
PBs IN OUT 1N OUT
PBe IN OUT IN OUT
PBz IN OUT IN OUT
Pco IN OUT INTRs INTRs vo
PCr IN OUT lBFs oBFB t/o
Pcz IN OUT sTEs Affis l/o
PCg IN OUT INTR1 INTRI INTR6
PCa IN OUT SfEa t/o sfBa
PCs IN OUT lBFl vo lBFa
PCe IN OUT vo 7ffia AfKA
PCt IN OUT uo oBFA oEFA

Speclal Mode GomblnatlonConslderatlons enableflag,the"Set/ResetPort

There are several combinationsof modes possible.
For any combination,som€ or all of the Port C lines
ars used for control or status.The remainingbits are
either inputs or outputs as defined by a "Set Mode"
command.
Durinq a read of Port C, the state of all the Port C
lines,ixcept the AOK-and STE lines,will be placed
on the data bus. In place of the ACK and STB line
states,flag statuswill appearon the data bus in the
PC2, PC4, and PC6 bit positionsas illustratedby
Figure18.
changean interrupt
C Bit" command mustbe used.
Witha "Set/ResetPortC Bit" command, anyPortC
lineprogrammed as an output(includingINTR,IBF
anO6BF) can be written,or an intenuptenableflag
can be eitherset or reset.PortG linesprogrammed
as inputs,includingIffi andSIB lines,associated
withPortC are not atlectedby a "Set/ResetPortC
Bit" command.Writinglc the conesponding PortG
bit positionsof the ACK and STB lines with the
"Set/Reset Port C Bit" commandwill atfect the
GroupA andGroupB intenuptenableflags,as illus-
tratedin Figure18.

Througha "Write Port C" command,only the PortC

pins programmedas outputsin a Mode0 groupcan
be written.No other pins can be atfectedby a "Write
PortC" command,nor can the int€nuptenableflags
be accessed.To write to any Port C output pro-
grammed as an output in a Mode 1 group or to
CurrentDrlveCapablllty
Anyoutputon PortA, B or C cansinkor source2.5
mA.Thisfeatureallowsthe 82C$5Ato directlydrive
Darlingtontype driversand high-voltagedisplays
thatrequiresuchsinkor sourcecunent.

3-139
intef 82C55A

Readlng Port C Status INPUTCONFIGURATION

D7 D5 D5 Da D3 D2 D1 D9
In Mode 0, Port C transfersdata to or from the pe- tlolt/Ol IBFAI INTEAI INTRaI INTEBI IBFBI INTRB
ripheraldevice.Whenthe 82C55Ais programmedto
functionin Modes 1 or 2, Port C generatesor ac- GROUPA GROUPB
cepts "hand-shaking"signalswith the peripheralde-
vice. Readingthe contentsof Port C allowsthe pro- OUTPUTCONFIGURATIONS
grammer to test or verify the "status" of each pe- D7 D5 D5 Da D3 D2 D1 D6
ripheraldevice and change the program flow ac-
cordingly.
GROUPA GROUPB
There is no special instructionto read the status in-
formation from Port C. A normal read operation of Figure17a.MODE1 StatusWordFormat
Port C is executedto oerformthis function.
D7 D5 D5 Da D3 D2 D1 Dq

GROUPA GROUPB
(Defined
ByMode0 or Mode1 S€l€ction)

Flgure17b.MODE2 StatusWordFormat

lnterruDt Enable Flao Posltlon AlternatePortC PinSional(Mode)

INTEB PC2 Afia (OutputMode1)orSTBg(lnputMode1)
INTEA2 PC4 STEI (lnputMode1 or Mode2)
INTEA1 PC6 Affia (OutputMode1 or Mode2
Flgure18.InterruptEnableFlagsIn Modes1 and2

3-140
 intet 82C55A

'Notice:Slressasabovethoselistedunder "Abso-
ABSOLUTE MAXIMUM RATINGS-
lute MaximumRatings"maycausepermanentdam-
AmbientTemperatureUnderBias....0"Cto + 70'C age to the device.Thisis a stressratingonlyand
StorageTemperature -
. . . 65'Cto + 150.C functionaloperationof the deviceat theseor any
supplyVottage 0.5to + 8.0V o,!!::,":!-1't,* abovethoseindicatedin theopera-
tionalsectionsof thisspecificationis not implied.Ex-
operatingVoftage . ' . . + 4V to + 7V posure to absolutemaximumrating conditionsfor
Voltageon anylnput.. . .GND-2V to * 6.5V extendedperiodsmayatfectdevicereliability.
VoltageonanyOutput. .GND-0.5Vto V66 + 0.5V
PowerDissipation . . .1 Watt

D.C. CHARACTERISTICS
T A = 0 ' C t o 7 0 o C , V C C+: 5 V + 1 0 % , G N D : 0 V f i R : -40'Cto t85'CforExtendedTemperture)
Symbol Parameter Mln Max Unlts TestCondltlons
Vt lnputLowVoltage -0.5 0.8 V
Vrn lnputHighVoltage 2.0 Vcc v
Vor OutputLowVoltage 0.4 V lgL : 2.5 mA
Vox OutputHighVoltage 3.0 V lox -2.5 mA
Vss - 0.4 V lox -100pA
I11 InputLeakageCunent *1 pA V1N= Vgg to 0V
(Note1)
lopl OutputFloatLeakageGunent r10 pA V;1 = Vg6 to 0V
(Note 2)
loln Darlington
DriveCunent i2.5 (Note4) mA PortsA, B, C
R6: 500o
Vexl: 1.7V
lpnt PortHoldLowLeakageCunont +50 +300 pA V9g1 : 1.0V
Port A only
lpxn Port Hold High LeakageCunent -50 -300 pA Vggl = 3.0V
PortsA, B, C
lpxuo PortHoldLowOverdrive
Cunent -350 pA V9gr1: 0.8V
lpnro PortHoldHighOverdrive
Gunent +350 pA Vggl : 3.0V
lcc V66 SupplyGunent 10 mA (Note3)
lccsa V66 SupplyCunent-Standby 10 y"A V66 : 5.5V
Vrru= VCCor GND
PortConditions
ll llP = Open/High
OIP : OpenOnly
WithDataBus:
High/Low
Fs: High
Reset= Low
PureInputs:
Low/High
NOTES:
1. PinsA1,Ao,tF, WF, FE, Reset.
ts: <__.-.--- -.?. Data8tlqjfartg-E*-c-._
3. Outputsop€n.
4. Limitoutputcunenl to 4.0 mA.
3-14'l
inbr 82C55A

CAPACITANCE
TA : 25'C,Vcc : GND: 0V
Symbol Parameter Mln Max Unlts TestCondltlons
crH InputGapacitance 10 pF Unmeasured plns
returnedto GND
cvo l/O Gapacitance 20 pF
fc : 1 MHz(s)

NOTE:
5. Samplednot 100o/o
tested.

A.C. CHARACTERISTICS
TA : 0'to 70oC,Vcc : +5V 110%,GND= 0V
TR : -40"C to *85'C for Extended
Temperature

BUSPARAMETERS

READCYCLE
82C554.2 Teat
Symbol Parameter Unlts
llfn llax Condltlonr
tan AddressStableBeforeF-DJ 0 ns
tRR AddressHoldTimeAfterFDf 0 ns
tRn RD PulseWiOtn 150 ns
tno DataDelayfromFDJ 120 ns
tor FDT to Daa Fbating 10 75 ns
tnv RecoveryTimebetweenHD/WH 200 ns

WRITECYCLE
82C55A-2 Teet
Symbol Parametsr Unltr
tln iler Condltlonr
taw AddressStrableBeforeWF t 0 ns
twn AddressHold Time AfterWR f 20 ns PortsA & B
20 ns Port C
tww W-RPulseWidth 100 ns
tow DataSetupTimeBeforeWRf 100 ns
two DataHoldTimeAfterWHT 30 ns PortsA & B
30 ns PortC

g-'t42
intef 82C55A

OTHERTIMINGS

Symbol Parameter 82C55A-2 Unlts

Test
Mln Max Condltlone
twe WFI: l toOutput 350 ns
trR Peripheral
DataBeforeRD 0 ns
txn PeripheralDataAfterffi 0 ns
tnr Affi PulseWidth 200 ns
tsr STB-PulseWidth 100 ns
tps Per.DataBeloreSfB Hign 20 ns
tpx Per.DataAfterSTBHigh 50 ns
tRo Iffi: 0toOuput 't75 ns
txo ffi : 1 to OutputFloat 20 250 ns
twog WFi: l toOBF: O 150 ns
tnog ffi: O t o O B F - :1 150 ns
tstg SfB=OtolBF:1 150 ns
tRra FiD:ltolBF=O 150 ns
tnr ffi:OtoINTR:O 200 ns
tsr SfEi:ltolNTR:1 150 ns
tnn Affi:ltoINTR=1 150 ns
twr WFI:0to|NTR:0 200 ns seenote1
tnes ResetPulseWidth 500 ns seenote2
1{OTE:
1. INTFT may(rccuras earlyas WFt.
2. Pulsewidthol initialResetpulseatterpoweron must be at l€ast 50 pSec. SubsequentReset pulses may be SOOns
minimum.

3-143
WAVEFORMS

xloDE0 (BAslcINPUn

291256-22

lroDEo (BAslcouTPuT)

81256-23
int€t 82C55A

WAVEFORMS(continued)

rroDE1 (STROBED
TNPUT)

r!f

|'{in

tFo

il?urFnff___
?titi{tnat

2312fi-24

roDE I (STROBED
OUTPUT)

(5'

tTt

act

qmtt

3-145
intef 82C55A

WAVEFORMS(continued)

rroDE2 (BIDIRECTIONAL)

DATA iifi
l2t6 TO rO0

Notc:
AnvsequencewhereWFiocctrs beforercR ANDSfE occursbeloreFD is permissible.
(INTR- IBFo fiIASR. SfB. FD + 6EF. NtIffi o flffi offi1

WRITE TIiIING READ TIIIIING

231236-28
231256-27

A.C. TESTINGINPUT,OUTPUTWAVEFORII A.C. TESTINGLOAD CIRCUIT

231256-29
A.C.Teafirg lnputsA?€DrivenAt 2.4VFor A Logic1 And 0.45V
For A Logic 0 Timing MeasurornentsAte Made At 2.0V For A
Looic 1 Ancl0.8 For A Logic0.
= 231256-30
'Vgp ls S€t At VsriousVoltagesDuringT€stingTo Guarantee
Th€ Sp€cification.Cs IncludesJig Capacitance.

3-146
 IntervalTimer
lntel82C54Programmable
DataSheetReprint
intel'
82C54
CHMOSPROGRAMMABLE TIMER
INTERVAL
I Compatlblewlth all Intel and most I ThreeIndependent16-bltcounters
other mlcroprocessors I Low PowerCHMOS
r HfghSpeed,"Zero Walt State" - lcc : 10 mA @8 MHzCount
Operatlonwlth 8 MHz8086/88and frequency
80186/188 r CompletelyTTL Compatlble
I HandlesInputs from DC to 8 MHz r Slx ProgrammableCounterModes
- 10 MHz tor 82C54-2
r Binaryor BCDcountlng
r AvallableIn EXPRESS
- StandardTemperatureRange I StatusReadBack Command
- ExtendedTemperatureRange I Avallableln 24-PlnDIPand 28-PlnPLcc
CHMOSversionof the industry
Thelntel82C54is a high-performance, standard 8254counter/limerwhichis
designedto solvethe timingcontrolproblemscommonin microcomputer systemdesign.lt providesthree
independent16-bitcount€rs,eachcapableof handlingclockinputsup to 10 MHz.All modesare software
programmable.The 82C54is pincompatible withth€ HMOS8254,andis a supersetof the 8253.
Six programmable
timermodesallowthe 82C54to be usedas an eventcounter,elapsedtime indicator,
programmable andin manyotherapplications.
one-shot,
The82C54is fabricated on lntel'sadvanced whichprovideslow powerconsumption
CHMOSlll technology
withperformance HMOSproduct.
equalto or greaterthantheequivalent The82C54is availablein 24-pinDIP
and 28-pinplasticleadedchipcarier (PLCC)packages.

6
f

t0
fD ll
m
|lr.t5tl'tl
Ao
Ar
231214-3
PIASTICLEADEDCHIPCARRIER

O, I Ycc
Oa ? m
Or 3 22 m
D. a Ir e5
Ot 5 ,0 Ar
D, t rt Ao
Dr , tl ctr 2
Do a tt oul 2
ctr 0 I c/ttc 2
our 0 t0 cLt r
2312U-1 OATEO ll OA?E1
Flgure 1.82C54Block Dlagram oro i2 OUI r
231244-2
Dogramsarelor pinret€r€nc€only.
Packag€siz€sarenot to scal€.

Ffgure2.82C54Pinout

Srpt.mb€r 19E9
3-83 O?d.r Iumbcn 2gfzffiOS
intef 82C54

Table 1. Pln Deecrlption

Pln Number Function
Symbol Type
DIP PLCC
Dz-Do 1-8 2-9 t/o databus lines'
Data:Bidirectionaltri-state
connectedto systemdata bus.
CLK O I 10 I Clock0: ClockinPutof Counter0.
OUTO 10 12 o Output0: Outputol Counter0.
GATE O 11 13 I Gate0: Gateinputof Counter0.
GND 12 14 PowersuPPlY
Ground: connection.
OUT1 13 16 o Out1:Outputof Counter1
GATE1 14 17 I Gate 1: Gateinputof Counter1.
CLK1 15 18 I Clock1: Clockinputof Counter1.
GATE2 16 19 I 2.
Gate2: Gateinputof Counter
OUT2 17 20 o Out2: Outputof 2.
Counter
CLK2 18 21 I Clock2: Clockinputof Counter2.
Ar' Ao 20-1I 23-22 Address:Usedto selectone of the threeCounters
or the ControlWord Registerfor read or write
operations.Normallyconnectedto the system
addressbus.
A1 Ao Selects
0 0 Gounter0
0 1 Counter1
1 0 Counter2
1 1 ControlWord Reoister
G 21 24 GhipSelect:A low on this ena:
input ..the82C54
to respondto ffi andWFisignals.F' andWFiare
ionoredotheruise.
m 22 26 I ReadControl:Thisinputis lowduringCPUread
operations.
WF 23 27 I WriteControl:Thisinputis lowduringCPUwrite
ooerations.
Vee 24 28 Power:+ 5Voowersupplvconnection.
NC 1 , 1 1 ,1 5 , 2 5 NoConnect

sired delay. After the desired delay, the 82C54 will

DESCRIPTION
FUNCTIONAL interruptthe CPU.Sottwareoverheadis minimaland
variablelengthdelayscan easilybe accommodated.
General Some of the other counter/timerfunctionscommon
The 82C54is a programmable intervaltimer/counter to microcomputerswhich can be implementedwith
designedfor use with Intel microcomputersystems. the 82C54 are:
It is a generalpurpose,multi-timingelementthat can
o Realtimeclock
be treated as an anay of l/O ports in the system
o Evencounter
software.
o Digitalone-shot
o Programmablerate generator
The 82C54 solves one of the most common prob'
. Squarewave generator
lems in any microcomPutersystem, the generation
o Binaryrate multiplier
of accuratetime delaysunder softwarecontrol.In-
o Gomplexwaveformgenerator
stead of setting up timing loops in software,the pro-
grammerconfiguresthe 82C54to matchhis require- o Complexmotor controller
mentsand programsone of the countersfor the de-

3-84
intef
Block Dlagram
DATABUSBUFFER
This3-state,bi-directional,
8-bitbufferis usedto in-
terfacethe 82C54to the systembus(seeFigure3).
231244-4
Flgure3. Block DlagramShowlngDataBus
Bufler and Read/WrlteLoglc Functlons
READ/WRITE
LOGIC
The Read/WriteLogicacceptsinputsfromthe sys-
tem busand generatescontrolsignalsfor the other
functionalblocksof the 82C54.A1 and Ao select
oneof thethreecountersor theControlWordRegls-
ter to be readfrom/writteninto.A "low" on the RD
inputlells the 82C54thatthe CPll_isreadingone of
the counters.A "low" on the WB input tells the
82C54thatthe CPUis q4!ng eithera ControlWord
or an initialcount.BothRDandWRarequalified by
eS; FD andWF are ignoredunlessthe 82C54has
beenselectedby holdingCSlow.
3-85
82C54
CONTROLWORDREGISTER
The ControlWord Register(seeFigure4) is selected
by the Read/WriteLogicwhen Ar, Ao : 11. lf the
CPU then does a write operationto the 82C54,the
data is stored in the ControlWord Registerand is
interpretedas a Control Word used to define the
operationof the Counters.
The ControlWord Registercan only be written to;
status informationis availablewith the Read-Back
Command.
FO
wt
z
E
231244-5
Flgure4. BlockDlagramShowlngControlWord
ReglsterandGounterFunctlons
couNTER0, couNTER1, COUNTER
2
Thesethreefunctional blocksareidentical
in opera-
tion,so onlya singleCounterwillbe described.
The
internalblockdiagramof a singlecounteris shown
in Figure5.
The Countersare fullyindependent.
EachCounter
mayoperatein a differentMode.
TheControlWordRegister is shownin the figure;it
is not partof the Counteritself,but its contentsde-
terminehowthe Counteroperates.
intef
231244-6
Flgure5.IntemalBlock Diagramof a Gounter
The status register, shown in the Figure, when
latched,containsthe currentcontentsof the Control
Word Register and status of the output and null
count flag. (See detailed explanationof the Read-
Back command.)
The actual counteris labelledCE (tor "CountingEle-
ment"). lt is a 16-bitpresettablesynchronousdown
counter.
oLy and oL1 are two 8-bit latches. oL stands for
"Output Latch"; the subscripts M and L stand for
"Most significantbyte" and "Least significantbyte"
respectively.Both are normally referred to as one
unit and calledjust OL. Theselatchesnormally"fol-
low" the CE, but if a suitable Counter Latch Com-
mand is sent to the 82C54, the latches "latch" the
present count until read by the CPU and thEn return
to "following"the CE. One latchat a time is enabled
by the counter's Control Logic to drive the internal
bus. This is how the 16-bitCountercommunicates
over the 8-bit internal bus. Note that the CE itself
cannot be read; whenever you read the count, it as
the OL that is beingread.
Similarly,there are two 8-bit registers called CRy
and CR1 (for "Count Register").Both are normally
reterredto as one unit and cafled just CR. When a
new count is written to the Gounter,the count is
82C54
storedin the CR and latertransferredto the CE' The
Control Logic allows one registerat a time to be
loadedfrom the internalbus. Both bytes are trans'
ferredto the CE simultaneously. CRy and CRg are
cleared when the Counter is programmed.In this
way, if the Counterhas been programmedlor one
byte counts(eithermostsignificanibyte only or least
significantbyte only) the other byte will be zero.
Note that the CE cannot be written into; whenevera
count is written,it is writteninto the CR.
The ControlLogicis also shownin the diagram.CLK
n, GATE n, and OUT n are allconnectedto the out-
side world throughthe ControlLogic.
82C54SYSTEMINTERFACE
The 82C54is treated by the systemssoftwareas an
arrayof peripherall/O ports;threeare countersand
the fourth is a control register for MODE program-
ming.
Basically,the select inputsAq, A1 connectto the Ag,
A1 addressbus signalsof the CPU.The CS can be
derived directly from the address bus using a linear
select method.Or it can be connectedto the output
of a decoder, such as an Intel 8205 for larger sys-
t€ms.
lr&Elolormm
aacaa
couxr:i oooxttt cotttEi
0t2
'out 'olrt 'our
oatE crx o^t: cr.x' o^TEcrr'
231211-7
Flgure 6.82C54 System Interface
3-86
intef 82C54

DESCRIPTION
OPERATIONAL Programmingthe 82C54
Countersare programmedby writinga ControlWord
General and then an initialcount.The controlword formatis
shownin Figure7.
Atter power-up,the state of the 82C54is undefined.
The Mode, count value,and output of all Counters All ControlWords are writteninto the ControlWord
are undefined. Register,whichis selectedwhen A1, Ao : t1. The
ControlWord itselfspecilieswhich Counteris being
How each Counteroperatesis determinedwhen it is programmed.
programmed.Each Counter must be programmed
beforeit can be used.Unusedcountersneed not be By contrast,initialcountsare writteninto the Coun-
programmed. ters, not the ControlWord Register.The A1, Ag in-
puts are used to select the Counterto be written
into.The formatof the initialcount is determinedby
the ControlWordused.

ControlWord Format
A1,As:11 6:O ffi:1 WFi:0

D7 D5 D5 Da D3 D2 D1 Ds
scl sc0 RW1 RW0 M2 M 1 MO BCD

SC - Select Counter: M - MODE:

scl sco M2 Ml MO
0 0 SelectCounter0 0 0 0 Mode0
0 1 SelectCounter1 0 0 1 Mode 1
1 0 2
SelectGounter X 1 0 Mode2
Read-BackCommand X 1 1 Mode3
1 1
(See Read Operations) 0 0 Mode4
1
1 0 1 Mode5
FW - Read/Wrlte:
RWl RWo
BCD:
0 0 GounterLatchGommand(see Read
Operations) 0 BinaryCounter16-bits
0 1 Read/Writeleastsignificantbyteonly. 1 BinaryCodedDecimal(BGD)Counter
(4 Decades)
1 0 Read/Writemostsignificantbyteonly.
1 1 Read/Writeleastsignificantbytefirst,
then mostsignificantbyte.

NOTE:Don't care bits (X) shouldbe 0 to insure

compatibilitywith future lntel products.

Figure7. ControlWordFormat

3-87
intet 82C54

WriteOperations struction sequence is required.Any programming

The programmingprocedurefor the 82C54 is very
flexible.Only two conventionsneed to be remem-
bered:
1) For each Counter,the Control Word must be
writtenbeforethe initialcount is written.
2) The initial count must lollow the count format
specifiedin the Control Word (least significant
byte only,most significantbyte only,or leastsig-
nificantbyte and then most significantbyte).
Since the Control Word Register and the three
Countershave separateaddresses(selectedby the
Ar, Ao inputs),and each ControlWordspecifiesthe
Counterit appliesto (SC0,SCI bits),no specialin-
sequencethat followsthe conventionsabove is ac-
ceptable.
A new initialcount may be writtento a Counterat
any time without affecting the Counter's pro'
grammedModein anyway.Countingwill be atfected
as describedin the Modedefinitions.The new count
mustfollow the programmedcount format.
lf a Counter is programmedto read/write two-byte
counts,the followingprecautionapplies:A program
must not transfer control between writing the first
and secondbyteto anotherroutinewhichalsowrites
into that same Counter.Othenrise,the Counterwill
be loadedwith an incorrectcount.

A1 Ao A1 Ae
ControlWord- 0
Counter 1 1 ControlWord- Gounter2 1 1
LSBof count- 0
Counter 0 0 ControlWord- Counter1 1 1
MSBof count- 0
Counter 0 0 ControlWord- Counter0 1 1
ControlWord- Counter1 1 1 LSBof count- Counter2 1 0
LSBof count- Counter1 0 1 MSBof count- Counter2 1 0
MSBof count- Gounter1 0 1 LSBof count- Counter1 0 1
ControlWord- 2
Gounter 1 1 MSBof count- Counter1 0 1
LSBof count- 2
Counter 1 0 LSBof count- Gounter0 0 0
MSBof count- 2
Counter 1 0 MSBof count- counter0 0 0

A1 A9 A1 Ao
ControlWord- Counter0 1 1 ControlWord- Gounter1 11
CounterWord- Counter1 1 1 ControlWord- Counter0 11
GontrolWord- 2
Counter 1 1 LSBof count- Counter1 01
LSBof counl- Counter2 1 0 ControlWord- Counter2 11
LSBof count- Counter1 0 1 LSBof count- Counter0 00
LSBof count- 0
Counter 0 0 MSBof count- Counter1 01
MSBof count- Counter0 0 0 LSBof count- Counter2 10
MSBof count- Counter1 0 1 MSBof count- Counter0 00
MSBof count- Counter2 1 0 MSBof count- Counter2 10

NOTE:
In all four examples,all countersare programm€dto read/writetwo-bytecounts.
Theseare only four of manypossibleProgramming seguenc€s.

Figure 8. A Few PosslbleProgrammlngSequences

ReadOperations Latch Command,and the Read-BackCommand.

It is often desirableto read the value of a Counter
withoutdisturbingthe countin progress.This is easi-
ly done in the 82C54.
There are three possiblemethodsfor readingthe
counters: a simple read operation,the Counter
Each is explainedbelow. The first method is to per-
form a simple read operation.To read the Counter,
which is selectedwith the A1, A0 inputs,the CLK
input of the selected Counter must be inhibitedby
using either the GATE input or externallogic. Other-
wise,the count may be in the processof changing
when it is read,givingan undelinedresult.

3-88
inbr
COUNTERLATCH COMMAND
The secondmethoduses the "CounterLatch Com-
mand". Likea ControlWord.this commandis written
to the Control Word Register,which is selected
when A1, Ao : t1. Also like a ControlWord,the
SCO,SC1 bits selectone of the three Counters,but
two other bits,D5 and D4, distinguishthis command
from a Control Word.
A l , A o : 1 1 ;e 5 : O ; F D : 1 ; W F : 0
D7 D5 D5 Da D3 D2 D1 Ds
scl SCO 0 0 X X X X
SC1, SCO- specifycounterto be latched
SCI SCO Counter
0 0 0 READ.BACKCOMMAND
0 1 1
1 0 2 The third method uses the Read-Backcommand.
1 1
Read-BackCommand
D5,D4- 00 designatesCounterLatchCommand
X - don't care
NOTE:
Don'tcarebits (X) shouldbe 0 to insureclmpatibility
withfulureIntelproducts.
Figure 9. Counter Latchlng Command Format
The selectedCounter'soutputlatch(OL)latchesthe
count at the time the Counter Latch Gommandis
received.Thiscountis held in the latchuntilit is read
by the CPU (or until the Counteris reprogrammed).
The count is then unlatchedautomaticallyand the
OL returnsto "following"lhe countingelement(CE).
This allows readingthe contents of the Counters
"on the fly" without aflecting counting in progress.
MultipleCounterLatch Commandsmay be used to
latch more than one Counter.Each latchedCoun-
ter's OL holdsits countuntilit is read.CounterLatch
Commandsdo not affect the programmedMode of
the Counterin any way.
lf a Counteris latchedand then, some tamelater,
latchedagain beforethe count is read,the second
CounterLatchCommandis ignored.The countread
will be the count at the time the first CounterLatch
Commandwas issued.
With eithermethod,the count must be read accord-
ing to the programmedformat; specifically,il the
Counter is programmedfor two byte counts, two
bytes must be read.The two bytes do not have to be
read one right after the other; read or write or pro-
3-89
82C54
grammingoperationso{ other Countersmay be in-
sertedbetweenthem.
Another feature of the 82C54 is that reads and
writesof the same Countermay be interleaved;for
example,if the Counteris programmedfor two byte
counts,the followingsequenceis valid.
1. Read leastsignificantbyte.
2. Write new least significantbyte.
3. Read most significantbyte.
4. Write new most significantbyte.
lf a Counteris programmedto readlwritetwo-byte
counts,the followingprecautionapplies;A program
must not transfercontrol betweenreadingthe lirst
and secondbyteto anotherroutinewhichalso reads
from that same Counter.Othenrvise,an inconect
countwill be read.
This commandallowsthe user to check the count
value,programmedMode, and currentstate of the
OUT pin and Null Count ftag of the setected coun-
ter(s).
The commandis writteninto the ControlWord Reg-
ister and has the format shown in Figure 10. The
commandappliesto the countersselectedby set-
ting their correspondingbits D3,D2,D1: 1.
A0,Al:tt 6:0 RD-:t WF:g
D5:0 = Latch count of selectedcounter(s)
Da:0 : Latch statusot s€lectedcounter(s)
D3: 1 : Selectcounter2
D2: 1 : Selectcounter1
Dr: 1 : S€lectcounter0
Dg:Reservedlor luture expansion;must be O
Flgure 10.Read-BackCommandFormat
The read-backcommandmaybe usedto latchmulti-
ple counter output latches (OL) by setting the
COUNTbit D5:0 and selectingthe desiredcoun-
ter(s).This single commandis functionallyequiva-
lent to several counter latch commands,one for
each counterlatched.Eachcounter'slatchedcount
is held until it is read (or the counter is repro-
grammed).That counteris automaticallyunlatched
when read, but other countersremainlatcheduntil
theyare read.lf multiplecountread-backcommands
are issuedto the same counterwithoutreadingthe
inbf 82C54

count,all but the first are ignored;i.e.,the count

whichwill be readis the countat the timethe first THISACTION: CAUSES:
read-back command wasissued. A. Writeto the control
r, Nullcount: 1
wordr€glst€r:(
Theread-back command mayalsobe usedto latch - Writeto the count
B.
by setting Nullcount:1
statusinformationol selectedcounter(s) r"g,.t"itc^rr'r
ffirre bit D4:0. statusmustbe latchedto be C. Newcountis loaclei
Nullcount=o
by a readtrom
read;statusof a counteris accessed inrocE (cR + cE;
thatcounter. Itl Qnly the counterspecifiedby the controlword will
hav€ its null count set to 1. Null counl bits of othet
Thecounterstatusformatis shownin Figure11.Bits countersare unatfected.
D5 throughD0 containthe counter'sprogrammed t2l I the counter is programmsdlor two-byte counts
Modeexactlyas writtenin the last ModeControl (least significantbyte then most significantbyle) null
Word.OUTPUT bit D7 containsthe currentstateof count goes to 1 when the secondbyte is writt€n.
the OUT pin.This allowsthe userto monitorthe
counter'soutputvia software,possiblyeliminating Flgure12.NullCountOperatlon
somehardwarefroma system.
lf multiplestatuslatchoperations of the counter(s)
are performedwithoutreadingthe status,all but the
firstare ignored;i.e.,the statusthat will be readis
the statusof the counterat the timethe firststatus
read-back command wasissued.
D 71 = O u l P i n i s l Both countand statusof the selectedcounter(s)
0 = OutPinis0 may be latchedsimultaneously by settingboth
D 6 1 = N u l lc o u n t mTfriT and SfA-iliS bits D5,D4=0.This is func-
0 = Countavailablefor reading
Ds-Do CounterProgrammedMode (See Figure7)
tionallythe sameas issuingtwo separate read-back
commands at once,andthe abovediscussions ap-
ply herealso.Specifically, if multiplecountand/or
Flgure 11.Status Byte statusread-backcommands are issuedto the same
counter(s) withoutanyintervening reads,all butthe
NULL COUNTbit D6 indicateswhen the last count firstareignored. Thisis illustrated in Figure13.
writtento the counterregister(CR)has been loaded
into the countingelement(CE).The exact time this lf bothcountandstatusof a counterarelatched,the
happensdependson the Modeof the counterand is firstreadoperationof thatcounterwillreturnlatched
describedin the ModeDefinitions, but untilthecount status,regardlessof whichwas latchedfirst. The
is loadedinto the countingelement(CE),it can't be next one or two reads(dependingon whetherthe
read from the counter.lf the count is latchedor read counteris programmed for one or two type counts)
belore this time, the count value will not reflectthe returnlatchedcount.Subsequent readsreturnun-
new count just written.The operationof Null Count latchedcount.
is shown in Figure12.

Command
Descrlptlon Results
D7 D5 D5 Da D3 D2 D1 De
'l a
0 0 0 0 1 0 Read back count and statusof Countand statuslatched
Gounter0 for Counter0
1 1 1 0 0 1 0 0 Readbackstatusof Gounter1 Statuslatchedfor Counter1
1 1 1 0 1 1 0 0 Read back statusof Counters2, 1 Statuslatchsdfor Counter
2, but not Counter1
1 1 0 1 1 0 0 0 Read back count of Counter2 Countlatchedfor Counter2
.t
1 0 0 0 1 0 0 Readbackcountand statusof Countlatchedfor Counter1,
Counter1 but not status
1 1 1 0 0 0 1 0 Readbackstatusof Counter1 Command ignor€d,status
alreadylatchedfor Counter1

Figure 13.Read-BackCommandExample
3-90
 inbr 82C54

es FD WR A r Ao This allowsthe countingsequenceto be synchroniz-

ed by sottware.Again,OUT does not go high until N
0 1 0 0 0 WriteintoCounter0 + 1 CLK pulsesafter the new count of N is written.
0 1 0 0 1 WriteintoCounter1
lf an initialcount is writtenwhile GATE : 0, it will
0 I 0 1 0 WriteintoCounter2 still be loadedon the next CLK pulse.When GATE
0 1 0 1 1 WriteControlWord goes high,OUT will go high N CLK pulseslater;no
0 CLK pulseis neededto loadthe Counteras this has
0 1 0 0 ReadfromCounter 0 alreadybeen done.
0 0 1 0 1 Readfrom Counter1
0 0 1 1 0 Readfrom Counter2
0 0 1 1 1 (3-State)
No-Operation
1 X X X X (3-State)
No-Operation
0 1 1 X X No-Operation(3-State)
Flgure14.Read/WrlteOperationsSummary

| -l * l* l' I I I 3I I I i I s lF|::l
ModeDefinitions
Cw- l0 Lll rt
The followingare definedfor use in describingthe
operationof the 82C54.
CLK PULSE:a risingedge,then a fallingedge, in
that order,of a Counter,sCLK input.
TRIGGER:a risingedge of a Counter'sGATE in-
put.
COUNTERLOADING:thetransferof a countfrom
the CR to the CE (refer to l"l"l - l" l3 | : I I | : i ? l3 lt:l
the "Functional Descrip-
tion") Cwr l0 Ltl rt

MODE 0: INTERRUPTON TERMTNALCOUNT

Mode0 is typicallyusedfor eventcounting.Afterthe
ControlWord is written,OUT is initiallylow, and will
remainlow untilthe Counterreacheszero.OUTthen
goes high and remainshigh until a new count or a
new Mode 0 Control Word is written into the Goun- l- l" l- l'13lt lt ll lt ls liil
ter. 231244-8

GATE : 1 enablescounting;GATE : O disables
counting.GATE has no etfect on OUT.
Afterthe GontrolWordand initialcountare writtento
a Counter,the initialcountwill be loadedon the next
CLK pulse.This CLK pulsedoes not decrementthe
count,so for an initialcount of N, OUT does not go
high until N + 1 CLK pulsesatter the initiatcount is
wriften.
lf a new count is writlen to the Counter,it will be
loadedon the next GLK pulseand countingwill con-
tinuefrom the new count.lf a two-bytecount is writ-
ten, the lollowinghappens:
1) Writingthe firstbyte disablescounting.OUT is set
low immediately(no clock pulse required).
2) Writingthe secondbyte allowsthe new count to
be loadedon the next CLK pulse.
3-91
NOTE:
The FollowingConventions ApplyTo All Mode Timing
Diagrams:
1. Counters are programmedfor binary (not BCD)
gollting and lor Reading/Writingt€ast significantbyte
(LSB)only.
2. The counleris alwaysselected(dS ahays low).
3. CW standsfor "ControlWord"; CW = 10 meansa
controlword of 10, hex is writtento the counter.
4. LSB standslor "Least SignilicantByte', of count.
5. Numbersbelowdiagramsare countvalues.
The lowernumberis the leastsignilicantbyte.
The uppernumberis the most significantbyte. Since
the counteris programmedto Read/WriteLSB only,
the mostsignificantbytecannotbe read.
N standslor an undelinedcount.
Verticallinesshowtransitions betweencountvalues.
Figure15.Mode0
inbf 82C54

iIODE 1: HARDWABERETRIGGERABLE MODE2: RATE GENERATOR

ONE.SHOT
OUTwill be initiallyhigh.OUT will go low on the CLK
pulsefollowinga triggerto beginthe one-shotpulse'
and will remainlow until the Counterreacheszero'
OUT will then go high and remainhigh untilthe CLK
pulse after the next trigger.
After writingthe ControlWord and initialcount, the
Counter is armed. A trigger results in loadingthe
Counterand settingOUT low on the next CLK pulse'
thus startingthe one-shotpulse.An initialcountof N
will resultin a one-shotpulseN CLK cyclesin dura-
hence OUT will
tion. The one-shotis retriggerable,
remainlow for N CLK pulsesafter any trigger.The
one-shotpulsecan be repeatedwithoutrewritingthe
samecountinto the counter'GATEhas no effecton
OUT.
This Mode functionslike a divide-by'Ncounter'lt is
tvoiciallyused to generatea Real Time Clock inter'
,i,pt. OUr will initiallybe higtr.Whenthe.initialcount
has decrementedto 1, OUT goes low for one CLK
pulse. OUT then goes high again,the Counter re-
ioads the initialcount and the processis repeated'
Mode 2 is periodic;the same sequenceis repeated
indefinitely.For an initialcount of N, the sequence
repeatsevery N CLK cYcles.
: 0 disables
GATE : 1 enablescounting;GATE
counting.It GATE goes low during an outputpulse,
reloadsthe
OUT is-set high immediately. A trigger
Counterwith the initialcount on the next CLK pulse;
OUT goes low N CLK pulsesafter the trigger'Thus
the GATE input can be used to synchronizethe
Counter.

lf a new countis writtento the Counterduringa one-
shot pulse,the currentone-shotis not affectedun-
less the Counter is retriggered.In that case, the
Counter is loaded with the new count and the one-
shot pulse continuesuntilthe new count expires.
After writing a Control Word and initial count, the
Counterwill be loadedon the next CLK pulse.OUT
ooes low N CLK Pulsesafter the initialcount is writ-
ien. This allowsthe Counterto be synchronizedby
softwarealso.

wr
FT

cLt
ctx

o^rE
O TE
oul

out

l - l - | r l * | r I I l t l t | 3 l : t l 3| : I
wt

r[ cLx

clx o^rt

ollE our

oul l',l- l- l-13l:ll l: ll I lli I

l- l.lxlr lr,l: !l ll l: ll li 13l CW. la l8l. a LS! r 3
'0[

CW r t2 Lt! :2 L5! rr
ctx
9t

ollE
ctx
out

GAIE
l.l.l.l" i: l3 i: ll l: l: l3 I
231244-10
our

NOTE:
l-i- ir r,xIIi:lllt:|il: l:I A GATEtransitionshould not occur one clock prior to
231244-9 terminalcount.

Figure16.Mode I Figure17.Mode2
3-92
 inbr 82C54

Writinga new count while countingdoes not atfect OUT will be highfor (N + 1)/2 countsand tow for
the curent counting sequence.lf a trigger is re. (N -1)/2 counts.
ceivedafter writinga new count but beforethe end
of the currentperiod,the Counterwill be loadedwith
the new count on the nsxt CLK pulse and counting
will continuefrom the new count. Othenrvise, th6
itr

new count will be loaded at the end of ths current ctt

countingcycle.ln mode 2, a COUNTof 1 is illegal.
cAt:

ilr
MODE3: SQUAREWAVE MODE

Jvlole _Sis typically used for Baud rate generation.

Mode3 is similarto Mode2 exceptfor the dutycycle
YT
of OUT. OUT witt initiailybe higfr.When hatf ins ini_
tial counthas expired,OUT goes low for the remain- c!r
der of the count. Mode 3 is periodic;the sequence
above is repeatedindefinitely.An initialcount of N oAtt

results in a square wave with a period of N CLK OI

cycles.
l' lr li l" l: lt lt l: lt l: l: ls l: l: I
GATE : 1 enablescounting;GATE : 0 disables
counting.lf GATEgoes low whiteOUTis low,OUT is 9t
set high immediately;no CLK pulse is required.A
triggerreloadsthe Counterwith the initialcount on ctr

the nelrt CLK pulse. Thus the GATE input can be

used to synchronizethe Counter oat:

After writing a Control Word and initial count, the
Counterwill be loadedon the next CLK putse.This
allows the Counter to be synchronizedby software
also.
Writing a new count while counting does not atfect
the current counting sequence.lf a trigger is re-
ceived after writing a new count but before the end
of the current hall-cycle of the square wave, the
Counterwill be loaded with the new count on the
next CLK pulse and countingwill continuefrom the
new count.Othenrise,the new count will be loaded
at the end of the currenthalf-cycle.
Mode 3 is implementedas follows:
Evencounts:OUT is initiailyhigh.The initialcountis
loadedon one CLK pulse and then is decremented
by two on succeedingCLK pulses.When the count
expiresOUT changesvalue and the Counteris re_
loadedwith the initiatcount. The above processis
repeatedindefinitely.
odd counts:oUT is initiallyhigh. The initialcount
minusone (an even number)is loadedon one CLK
pulseand then is decrementedby two on succeed-
ing CLK pulses.One CLK putseafter the count ex-
pires, OUT goes low and the Counteris reloaded
with the initial count minus one. SucceedingCLK
pulsesdecrementthe countby two. Whenthe count
expires,OUT goes high again and the Counteris
reloadedwith the initialcountminusone.The above
processis repeatedindefinitely.So for odd counts,
out
l'l"l"l.lll:ltlil:l|:i 3l
|:l
231214-11
NOTE:
A GATEtransition
shouldnot occurone clockpriorto
terminalcount.
Figure18.Mode3
MODE4: SOFTWARETRtccERED STROBE
OUT will be initiailyhigh.When the initiatcounr ex_
pires,OUT will go low for one CLK pulse and then
go highagain.The countingsequEnceis ,,triggered"
by writingthe initialcount.
GATE : 1 enablescounting;GATE : 0 disables
counting.GATE has no effect on OUT.
After writing a Control Word and initial count, the
Counterwill be loadedon the next CLK pulse.This
CLK pulsedoes not decrementthe couni,so for an
initial count of N, OUT does not strobe low until
N + 1 CLK pulsesafter the initialcount is written.
lf a new count is written duringcounting,it will be
loadedon the next CLK putseand countiig wiil con_
tinue from the new count. lf a two-bytecorint is writ-
ten, the followinghappens:

3-93
intet 82C54

1) Writingthe first byte has no etfect on counting.
2)Writing the secondbyte allowsthe new count to
be loadedon the next GLK Pulse.
This allows the sequenceto be "retriggered"by
software.OUT strobes low N+1 CLK pulses after
the new count of N is written.
wr
After writingthe ControlWord and initialcount' the
counterwill not be loadeduntilthe CLK pulseafler a
trigger. This CLK pulse does not decrementthe
count, so for an initial count of N' OUT does not
strobe low until N + 1 CLK pulses after a trigger.
A triggerresultsin the Counterbeingloadedwiththe
initial count on the next CLK pulse. The counting
sequenceis retriggerable.OUT will not strobe low
for N * 1 CLK pulsesafter any trigger'GATE has
no etfect on OUT.

cLx lf a new count is writtenduringcounting,the current

countingseguencewill not be affected.lf a trigger
oiltE occurs after the new count is written but before the
our current count expires,the Counterwill be loaded
with the new count on the next CLK pulse and
olololFFlFFlFrl
l.l-l.l"l:l zlrlolFFlFElFol countingwill continuefrom there.

w!
EI

ctx
ctx

oat: gAT:

our

l" l"l',l,l3 | 313l:ltlS lfil

Cf,. ta Lil.3 Llt r 2
wt m

cLx ctr

o/lt€ GAIE

out
ouY

l"l,.l"l-l: lololo
lzlrlalr
lo lolFFl
lolrrl
231244-12 ' .',:1.''
rI: IrIr |3r::r
:,'.:':.l,"'
Figure 19.Mode 4 *E

clx
MODE 5: HARDWARETRIGGEREDSTROBE
(RETBIGGERABLE) crlt

OUT will initiallybe high.Countingis triggeredby a out

risingedge ol GATE.When the initialcount has ex-
pired,OUT will go low for one CLK pulse and then l,l. lr lr l* ll I :l I | : l;:l:!l I i : I
go high again. 231244-13

Flgure 20. Mode 5

3-94
intef 82C54

Slgnal Low OperationCommonto All Modes

Statur Or Golng Rlrlng Hlgh
llodcc Low
Programmlng
0 Disables Enables
counting counlinq When a Control Word is written to a Counter,all
1 1) Initiates ControlLogicis immediatelyresetand OUT goes to
counling a knowninitialstate;no CLK pulsesare requiredfor
2) Resetsoutput this.
eft€r next
clock GATE
2 1) Disables
counting lnitiates Enables The GATE input is always sampled on the rising
2) Setsoutput counting counting edgeof CLK.ln Modes0,2,3, and4 the GATEinput
immediately is level sensitive,and the logic level is sampledon
hioh the risingedge of CLK. ln Modes 1, 2, g, and 5 the
GATEinpul is rising-edgesensitive.ln these Modes,
3 1) Disables
a rising edge of GATE (trigger)sets an edge-sensi-
counting lnitiates Enables tiveflip-flopin the Counter.Thisflip-ftopis then sam-
2) Setsoutput counting counting pled on the next risingedge of CLK; the flip-flopis
immedialely
reset immediatelyafter it is sampled. ln this way, a
high
triggerwill be detected no matter when it occurs-a
4 Disables Enables high logic leveldoesnot haveto be maintaineduntil
countino countino the next risingedge of CLK. Note that in Modes 2
5 lnitiates and 3, the GATEinputis both edge-and level-sensi-
countino tive. ln Modes2 and 3, if a GLK sourceother than
the systemclock is used, GATE should be pulsed
Flgure21.GatePlnOperailomSummary immediatelyfollowingWF-of a new count value.

COUNTER
IIODE
MIN mAx
COUNT COUNT New counts are loaded and Counters are decre-
0 1 0 mentedon the fallingedge of CLK.
1 1 0 The largeg!possibleinitial count is O;this is equiva-
2 2 0 lent to 216 tor binary counting and 104 for'BCD
counting.
3 2 0
4 1 0 The Gounterdo€s not stop when it reacheszero. ln
Modes0, 1, 4, and 5 the Counter"wrapsaround"to
NOTE: the highestcount,eitherFFFFhex for binarycount-
0 is equivalentto 216 lor binary countingand 10a for ing or 9999 for BCD counting,and continuescount-
BCDcounting ing. Modes2 and 3 are periodic;the Counterreloads
itself with the initial count and continues counting
Figure22.ilinlmumandilarlmum InlUalCounts from there.

3-95
inbf 82C54

'Notice: Slressesabove those listed under "Abso-

ABSOLUTEMAXIMUMRATINGS* lute MaximumRatings"maycauseparmanentdam'
AmbientTemperatureUnderBias... . ' ' '0'C to 70"C age to the device. Thisis a stressrating only and
StorageTemperature .....-65'to *150'C functionaloperationof the deviceat these or any
SuppliVoltage ......-0.5to +8.0V otherconditionsabovethoseindicatedin the opera'
OperatingVoltage ..... +4Vto+7V tionalsectionsof thisspecificationis not implied'Ex'
VoltageonanyInput.. . ' GND- 2Vto + 6.5V posure to absotutemaximumrating conditionsfor
VoltageonanyOutput. .GND-0.5Vto V6s + 0.5V extandedperiodsmayaffect deice reliability.
PowerDissipation . . .1 Watt

D.C.CHARACTERISTICS -40oC to *85'C for ExtendedTemperature)

:
ffR=0'C to 70'C,V66:5Vt 10%,GND:0V) CIn
Symbol Parameter Mln Max Unlts TeetCondltlona
V11 Input Low Voltage -0.5 0.8 V
Vru InputHighVoltage 2.0 Vcc + 0.5 V
Vor OutoutLowVoltage 0.4 v lnr : 2.5 mA
vox OutputHighVoltage 3.0 V lox : -2.5mA
Vcc - 0.4 V Inr.r: -100 rrA
lu lnputLoadCunent x2.0 pA Vrru:Vecto 0V
lopr OutputFloatLeakageCurrenl r10 pA Vnrm: Vcc to 0.0V
lsc V66 SupplyCunent 20 mA $MHz82C54
Cfk Freq: 10MHz g2CS4-2
't0 pA GLKFreq : 96
lccsa V66 SupplyCurrent-StandbY
dS: Vcc.
All lnputs/DataBusV66
AllOutputsFloatinq
lccser V66 SupplyCurrent-StandbY 150 pA CLKFreq: 96
eS : Vcc.AllOther
InPuts,
l/O Pins = VGND,OutputsOpen
Qru Input Capacitance 10 PF fs: 1MHz
Cvo l/O Capacitance 20 PF Unmeasured pins
20 pF returnedto GND(s)
cour OutputCapacitance

A.C.CHARACTERISTICS -40'C to * 85'Cfor ExtendedTemperature)

: 5V t10o/o,GND :0V) CIn :
fln : 0'C to 7o'C, Vcc
BUS PARAMETERS(NOIE1)
READCYCLE
82C54 82C54-2 Unlts
Symbol Parameter
Mln Max Mln Mar
tnR AddressStableBeforeFi5 J 45 30 ns
tsR 6 stauteBetoreR-DI 0 0 ns
tRl AddressHold Time Atter FE 1 0 0 ns
tnn m PulseWidth 150 95 ns
tRo DataElelaytromF-DJ 120 85 ns
tno Data Delayfrom Address 220 185 ns
tor FD 1 to DataFloating a 90 5 65 ns
tRv CommandRecoveryTime 200 165 ns
NOTE:
'1. AG timingsmeasuredat Vq1 : 2.0V'V91 : 0.8V'

3-96
 inbf 82C54

A.C. CHARACTERISTICS
(continued)
WRITECYCLE
Symbol Parameter 82C54 82C54-2
Unlts
Min ilax Min Max
tew AddressStableBeforeWFij 0 0 ns
tsw 6 StauleBeforeWFIJ 0 0 ns
twR AddressHoldTimeAfterWFII 0 0 ns
tww WR PulseWidth 150 95 ns
tow DataSetupTimeBeforeWFIf 120 95 ns
two DataHoldTimeAfterWFf 0 0 ns
tnv ComqandRecovery Time 200 165 ns

CLOCK AND GATE

Symbol Parameter 82C54 82Cs4-2
Units
Mln Max Min Max
tcr-x ClockPeriod 't25 DC 100 DC ns
tpwx HighPulseWidth 60(3) 30(3) ns
tpwl Low PulseWidth 60(3) 50(3) ns
Ts ClockRiseTime 25 25 ns
tp ClockFallTime 25 25 ns
tow Garewidrh High 50 50. ns
tcl Gate Width Low 50 50 ns
tes GateSetupTimeto CLKT 50 40 ns
teH Gate HoldTimeAfterCLKT 50(2) 50(2) ns
Too OutputDelayfromCLKJ 150 100 ns
!coo OutputDelayfromGateJ 120 100 ns
twc CLI( Delayfor Loading(a) 0 55 0 55 ns
two Gate Delayfor Sampling(a) -5 50 -5 40 ns
two OUT Delayfrom Mode Write 260 240 ns
tcl CLK Set Up for CountLatch -40 45 -40 40 NS
NOTES:
2' ln Modes 1.and 5 triggersare sampledon each risingclock edge.A secondtriggerwithin 120 ns (70
ns lor the s2os4-2)
of the risingclock edge may not be detected.
3. Low-goingglitchesthat violatetpwx, tpult cause_enors requiringcounterreprogramming.
4. Exceptlor Extendedremp., see Extendedlay remp. A.c. characteristiisbelow.
5. Samplednot 100o/otested.Trq= 25 C.
6' ll CLK Present9! Twc min then CountequalsN+2 CLK pulses,T619max equalsCountN+1 CLK pulse.
Ty76m€u,countwill be eitherN+ 1 or N+2 CLKpulses. Twc min to
7. In Modes 1 and 5, if GATE is presentwhen writinga new Countvalue,at Twq min Counterwill not
be triggered,at Try6
max Counterwill be triggered.
8' lf cLK presentwhen writinga CounterLatch or ReadBackCommand,at T6g min CLK will be reflected
in count value
latched'at Tg1 max CLK will not be reflectedin the counl value latched.Writirij a Countert-atctroi
ReaOgacfCom;nJ
betweenT6g min and Tyygmax will resultin a latch€dcount valluewhich is t one leastsignificantbit.

EXTENDED O : -40oC to +85'C for ExtendedT

TEiiIPERATURE

CLK Delayfor Loading

3-97
intet 82C54

WAVEFORMS

231244-14

READ

2312U-15

231244-16

3-98
inbf 82C54

CLOCKAND GATE

23121/-17
' Lrst byto ot counl belngwiten

A.C.TESTINGINPUT,OUTPUTWAVEFORIII A.C.TESTINGLOADCIRCUIT

INPUT/OUTPUT

I orvrcr I
| '*17
I I i cI r . t l r r
J
23124-10
A.C.Tecring:InputBar€ drivonat 2.4V tot I togic"1" and 0..f5V 23121,4.-19
for a logic "0." Timingmee8ur€mentE
aro msd€!t 2.0Vtor s bglc Cl - 150pF
'1" ud 0.8Vlor a logic C1 includer fig cepedtanca
"0."

3-99
 APPENDIX D

FOR SIGNAL*MATH
CONFIGURING THE AD2OOO
D-2
Jumper Settings
WhenrunningSIGNAL*MATH, you haveto changesomeof the AD2000'son-boardjumpen from their
facory-set positions.Before using SIGNAL*MATH on the AD2000 board,checkthe following jumpers:
.F2- Baseaddress
. P3 - 8254 timer/counterI/O configuration
. P4,P5 &YI - Intemrpts
. P6 - End-of-ConvertMonitor
Theboardlayoutis shownin FigureD-1.

IHH_lililqrulmftffi
f"'
Uu
ffi_=_LrUli[: ? |
P8

Oreffi
Ifgf t- .--. l-l

Fig. D-1 - AD2000 Board Layout

P2 - BaseAddress
SIGNAL*MATH assumesthat the baseaddressof your AD2000 is the factory settingof 300 hex (768 deci-
mal).If you changethis setting,you must run the ADAINST programandresetthebaseaddress.
NOTE: When using the ADAINST program,you can enterthe baseaddressin decimalor hexadecimal
notation.Whenenteringa hex value,you mustprecedethenumberby a dollar sign(for example,$300).

D-3
P3 - t254 Timer/Counter VO Configuration
The 8254 mustbe configuredwith the six jumpersplacedbetweenthe pins as shownin Figure D-2. After
setling drejumpers,verify that eachis in theproperlocation.Any remainingjumpersmust be rcmovedfrom the P3
headerconnector.

XTAL
ls

Els
ECo
+5V
E@ l-q
coo
coo
cK1
XTAL
ECr ls

Elr le
+5V
EG1
co1
6T
cJ<2
XTAL
l*

Els
rcz
+5V
ECi2 l"s
cg2
co2

Fig. D-2 -8254 Timer/CounterJumpers,P3

P4, PS & P7 - Interrupts

To selectIRQ channelsand intemrpt sourcesfor SIGNAL*MATH, you must install two jumperson P5 and one
jumper on P7. First install a jumper on P5-OUT2,and a secondjumper acrossthe pair of P5 pins for the IRQ
channelyou select.Then,install a jumper on the end-of+onvertintemrpt header,P7, acrossthe pins of your desired
IRQ channel.TheIRQ selectedon P7 must be different from the IRQ seton P5! FigureD-3 showsOUT2
jumperedto IRQ3 andEOC jumperedto IRQ4. Make surethat no jumpersareinstalledon P4.

P5 7 P7
6
5 7
4 6
3 o s-
2 o
]U 40
ol 3
r lO
:t5 2

Fig.D-3- Timer/Counter lntem;ptJumpers,P5 & P7

Out& End-of-Convert

P6- End-of-Convert
Monitor
placeajumperbetween
WhenrunningSIGNAL*MATH, EOCandPA7,asshownin FigureD4.

Fig.D-4- End-of-Convert
MonitorJumper,P6

D4
RunningADAINST
After thejumpersare setand the AD2000 boardis installedin the computer,you arereadyto configure
SIGNAL*MATH so that it is compatiblewith you board'ssetings. This is doneby running the ADAINST driver
installationprogram.After running theprogram,openAD2000.EXEfrom the Opena File menu.You will seea
screensimilar to the screenshownin Figure D-5 below. The factory default serings are shownin the illustration.
Your seuingsmay or may not matchthe default settings,dependingon whetheryou havemadechangesto these
seuingsbefore.
BaseAddress. The board'sbaseaddresssettingis enteredin the upperright block, as shownin the diagram.
The factory settingfor all Real Time Devicesboardsis 3CI hex (768 decimat).The baseaddresscanbe enteredasa
decimalor hexadecimalvalue (hex valuesmust be precededby a dollar sign (for example,$3m). Refer to your
board'smanualif you needhelp in determiningthe correctvalue0oenter.
EOC IT (End-of-Convert Interrupt). In this block, enterthe IRQ channelnumberwhich correspondsto your
jurnperse$ingon P7.
Timer IT (Timer/Counter Interrupt). In this block, enterthe IRQ channelnumberwhich correspondsto your
jurnpersettingon P5.
LabTech SW IT (LABTECH NOTEBOOK SoftwareInterrupt). This setsthe softwareintemrptaddress
whereLABTECH NOTEBOOK's labLINX driver is installed.The facory seningis $60. This settingcanbe
ignoredwhenrunning SIGNAL*MATH.
A./DParameters. Six A/D boardparameters
arelisted:resolution,numberof channels,activeDMA channel,
gain, loss,and input voltagepolarity.

Endof-Convert Timer/Counter
Interrupt
Channel lnterrupt
Ghannel BaseAddress

Software
lnterrupt
Address

A/D DMA D/A DMA

Channel Channel
Select; Select;
ExternalGain ExternalGain
& Loss & Loss

A/D Unipolar/
Bipolar
Select D/AUnipolar/
Bipolar
Select
Fig.D-5- ADAINST.EXE
Screen

D-5
 Resolutionand numberof channelsarefixed by theprogramfor your board.
The DMA channelnumberblock is not valid on the AD2000,andshouldbe left blank.
The next two blocks, gain and loss,are providedso that you can makeadjustmentsfor external gain or loss,
other than the programmablegain settingsavailableon the board.If your input signalis externallyattenuated,then
you canadjustfor this by settinga valueother than I for loss.Ifyou havean externalgain facbr, thenyou can
adjustfor this condition.Numbersmustbe enteredaswhole decimalvalues.The factory default sesingfor gain and
lossis 1.
For a bipolar input range,an X shouldbe placedbeforeBipolar on the screen(default setting).For unipolar
ope.ration,removethe X.
D/A Parameters. Thesesix blocksarenot usedon the AD2000,and shouldbe left blank.

D-6
 APPENDIX E

FOR ATLANTIS
CONFIGURING THE AD2OOO
Jumper Settings
WhenrunningATLANTIS, you haveo changesomeof theAD2000'son-boardjumpersfrom their facory-set
positions.Before using ATLANTIS on the AD2000 board,checkttrefollowing jumpen:
. F2 - Baseaddress
. P3 - 8254 timer/counterVO configuration
. P4,P5 &Yl - Intemrpts
. P6 - End-of-ConvertMonitor
Theboardlayoutis shownin FigureE-1.

R€l Tima Devi6s, Inq

ffiu*"rnu."n.

ECI
i5V
EGI
col
cor
ga
(TA
EC2
i6V
EG2

Fig. E-1 - AD2000 Board Layout

P2 - BaseAddress
ATLANTIS assumesthat the baseaddressof your AD2000 is the factory settingof 300 hex (seeChapter1). If
you changedthis setting,you must run tlte ATINST progxamandresetthe baseaddress.
NOTE: The ATINST programrequiresthebaseaddressto be enteredin decimalnotation.

E-3
P3 - 8254Timer/Counter UO Configuration
T1ne8254mustbe configuredwith the six jumpersplacedbetweenthe pins as shownin Figure E-2. Aftnr
settingthejumpers,verify that eachis in ttreproperlocation.Any remainingjumpersmust be removedfrom the P3
headerconnector.

XTAL
ECo
+5V
l*
EC{ 1.9
c@
coo
cK1 ls
XTAL
ECl ls

EIr I-e
+5V
EG1
co1
6T
cte.
XTAL
l*
Els
EC2
+5V
EG2 ls
c@.
ffi

Fig.E-2- 8254Timer/Counter
Jumpers,P3

P4,P5& P/ - Interrupts
To selectanRQ channelandanintemrptsourcefor ATLANTIS,youmustinstalltwojumpersonP5,the
outputintemrptheader.
timer/counter JumpersmustbeinstalledacrosstheOUT2pinsandacrossthepinsof your
desiredIRQchannel. FigureE-3showsOUT2jumperedto IRQ3.lvlakesurettratnojumpersareinstalledacrossthe
IRQpinson headerconnectors P4andP7.

[]i
l-l ;
Ll ilc
-ConvertInlerruptJumper,P7
Fig.E-3- End-of

P6 - End-of-ConvertMonitor
WhenrunningATLANTIS, placea jumperbetweenEOC andPA7, asshownin Figure84.

Fig.E-4- End-of-Convert
MonitorJumper,P6

E4
APPENDIX F

WARRANTY
F-2
 LIMITED WARRANTY

Real Time Devices,Inc. warrantsthe hardwareand softwareproductsit manufacturesandproducesto be free

from defecs in materialsand workmanshipfor oneyearfollowing the dateof shipmentfrom REAL TIME DE-
VICES. This warrantyis limited to the original purchaserof productand is not transferable.
During the oneyear warrantyperiod,REAL TIME DEVICES will repair or replace,at its option, any defective
produc8 orparts at no additionalcharge,providedthat the productis returned,shippingprepaid,to REAL TIME
DEVICES. All replacedpartsandproductsbecomettrepropertyof REAL TIME DEVICES. Before returning any
product for repair, customersare required to contactthe factory for an RMA number.
THIS LIMITED WARRANTY DOESNOT EXTEND TO A}.IY PRODUCTSWHICH HAVE BEEN DAM-
AGED AS A RESULT OF ACCIDENT, MSUSE, ABUSE (suchas:useof incorrectinput voltages,improperor
insufficient ventilation,failure to follow the operatinginstructionsthat areprovidedby REAL TIME DEVICES,
"acts of God" or othercontingenciesbeyondthe control of REAL TIME DEVICES),OR AS A RESULT OF
SERVICEOR MODIFICATION BY AI.IYONE OTIIER THAN REAL TIME DEVICES. EXCEPT AS EX-
PRESSLYSET FORTH ABOVE, NO OTHER WARRANTIES ARE E)GRESSEDOR IMPLIED, INCLUDING,
BUT NOT LIMI'IED TO, AI.IY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESSFOR A
PARTICULAR PURPOSE,AND REAL TIME DEVICESE)PRESSLY DISCLAIMS ALL WARRANTIES NOT
STATED HEREIN. ALL IMPLIED WARRANTIES,INCLUDING IMPLTEDWARRANTIES FOR
MECHANTABILITY AND FITNESSFOR A PARTICULAR PURPOSE,ARE LIMITED TO TTIE DURATION
OF THIS WARRANTY. IN TIIE EVENT THE PRODUCTIS NOT FREEFROM DEFECTSAS WARRAN]ED
ABOVE, TI{E PURCHASER'SSOLEREMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED
ABOVE. UNDER NO CIRCUMSTANCESWILL REAL TIME DEVICES BE LIABLE TO TTIE PTIRCHASER
OR AI.IY USER FOR AI.IY DAMAGES,INCLUDING AIIY INCIDENTAL OR CONSEQUENTIAL DAM-
AGES,E)GENSES,LOST PROFITS,LOST SAVINGS,OR OTI{ER DAMAGES ARISING OUT OF TIIE USE
OR INABILITYTOUSE TIIE PRODUCT.
SOME STATESDO NOT ALLOW TI{E EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE-
QUENTIAL DAMAGES FOR CONSUMERPRODUCTS,AND SOME STATESDO NOT ALLOW LIMITA-
TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS, SO T}M ABOVE LIMITATIONS OR EXCLU-
SIONS MAY NOT APPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFICLEGAL RIG}ITS, AND YOU MAY ALSO HAVE OTHER
RIGIITS WHICH VARY FROM STATE TO STATE.

F-3
 AD2000 User-SelectedOptions

Base I/O Address:

(hex) (decimal)

IRQ Channel Selection:

A/DEOC IRQ CHANNEL:

PITOUTO IRQ CHANNEL:

PITOUTI IRQ CHANNEL:

PITOUT2 IRQCI{ANNEL:

PPrrNTRA(PC3) IRQ CHANNEL:

EXTINT IRQ CHANNEL:

A/D EOC/PPI Bit Assignment:

A/D EOC PA?:

PC7: