energies

Article
A Novel Concept for Three-Phase Cascaded
Multilevel Inverter Topologies
Md Mubashwar Hasan * ID
, A. Abu-Siada, Syed M. Islam and S. M. Muyeen
Department of Electrical and Computer Engineering, Curtin University, Perth, WA 6102, Australia;
a.abusiada@curtin.edu.au (A.A.-S.); S.Islam@curtin.edu.au (S.M.I.); Sm.Muyeen@curtin.edu.au (S.M.M.)
* Correspondence: m.hasan12@postgrad.curtin.edu.au; Tel.: +61-8-9266-7287

Received: 16 November 2017; Accepted: 15 January 2018; Published: 23 January 2018

Abstract: One of the key challenges in multilevel inverters (MLIs) design is to reduce the number
of components used in the implementation while maximising the number of output voltage levels.
This paper proposes a new concept that facilitates a device count reduction technique of existing
cascaded MLIs. Moreover, the proposed concept can be utilised to extend existing single phase
cascaded MLI topologies to three-phase structure without tripling the number of semiconductor
components and input dc-supplies as per the current practice. The new generalized concept involves
two stages; namely, cascaded stage and phase generator stage. The phase generator stage is a
combination of a conventional three-phase two level inverter and three bi-directional switches while
the cascaded stage can employ any existing cascaded topology. A laboratory prototype model is
built and extensive experimental analyses are conducted to validate the feasibility of the proposed
cascaded MLI concept.

Keywords: multilevel inverters; device counts reduction; cascaded inverter; conventional three-phase
inverter

1. Introduction
Multilevel inverters (MLIs) have drawn much attention in renewable, vehicular and industrial
applications [1–6]. Also, MLIs have been utilized in flexible AC transmission, heating and air
conditions [7]. Conventional MLIs include diode clamped or neutral point clamped (NPC), flying
capacitor (FC) and cascaded H-bridge (CHB) MLI. Among these types, CHB MLI has been found very
reliable in high voltage/high power applications (6.6–13.8 kV, 500 MVA) [8,9]. Several research efforts
have been conducted to reduce the number and complexity of DC voltage supplies management [10,11].
Extensive research can be found in the literature to reduce the device count of cascaded MLI
(CMLI). Several cascaded MLI topologies comprise two main parts; level generator and polarity
generator as shown in Figure 1a can be found in the literature [12–15]. The level generator is a cascaded
connection of a number of inverter cells that generates multilevel unipolar voltage while the polarity
generator converts this unipolar voltage into bipolar voltage waveform [13]. While level generator
structure varies for different topologies, the structure of polarity generator has been always an H-bridge
connection involving four semiconductor switches. The number of cascaded cells in the level generator
may be increased and/or asymmetric input voltage sources can be used to enhance the number of
levels in the output voltage waveform without any change to the polarity generator [12]. The level
generator switches may work with high frequency, but the polarity generator switches always function
at line voltage frequency [13].
Other CMLI topologies which are able to generate bipolar voltage without using polarity generator
as shown in Figure 1b were proposed in the literature [16]. CMLI topologies such as cross-switched
and modified H-bridge topologies were also recently proposed in the literature [17–23]. Among the

Energies 2018, 11, 268; doi:10.3390/en11020268 www.mdpi.com/journal/energies

Energies 2018,
Energies 2018, 11,
11, xFOR
268 PEER 22 of
of 16
16

literature [17–23]. Among the above mentioned CMLI topologies, some were mainly developed for
above mentioned
three-phase CMLI topologies,
multilevel some wereand
voltage generation mainly developed
cannot for three-phase
be directly utilized multilevel
for singlevoltage
phase
generation and cannot be directly utilized
applications e.g., Figure 1c [24,25]. for single phase applications e.g., Figure 1c [24,25].

Figure 1. Block diagrams: (a) level and polarity generators-based cascaded multilevel inverter (CMLI)
Figure 1. Block diagrams: (a) level and polarity generators-based cascaded multilevel inverter (CMLI)
topology; (b)
topology; CMLI topology
(b) CMLI topology with
with no
no polarity
polarity generator;
generator; (c)
(c) 3-phase
3-phase CMLI
CMLI topology;
topology; (d)
(d) proposed
proposed
3-phase CMLI; (e) Circuital model of the PG-stage. Reprint with permission [4261051118814];
3-phase CMLI; (e) Circuital model of the PG-stage. Reprint with permission [4261051118814]; 2018,
IEEE. IEEE.
2018,

Three-phase CMLI has been widely used in large-scale renewable energy applications to comply
Three-phase CMLI has been widely used in large-scale renewable energy applications to comply
with the high-power conversion requirement [1–4]. In order to improve the quality of the output
with the high-power conversion requirement [1–4]. In order to improve the quality of the output
voltage waveform, the number of components required to implement the three-phase CMLI should
voltage waveform, the number of components required to implement the three-phase CMLI should be
be significantly increased which increases the implementation cost, inverter physical size and
significantly increased which increases the implementation cost, inverter physical size and complicates
complicates the control system. Although several topologies have been proposed in the literature in
the control system. Although several topologies have been proposed in the literature in order to reduce
order to reduce the device count and increase the number of levels in the output voltage of single
the device count and increase the number of levels in the output voltage of single phase CMLIs, the
phase CMLIs, the majority of these topologies have not been extended to three-phase structure yet.
majority of these topologies have not been extended to three-phase structure yet. It is a common
It is a common trend that the number of components of single phase topologies is tripled when they
trend that the number of components of single phase topologies is tripled when they are extended to
are extended to three-phase structures [13,14,26–28].
three-phase structures [13,14,26–28].
Both high frequency and low frequency modulation techniques have been reported as reliable
Both high frequency and low frequency modulation techniques have been reported as reliable
control strategies for CHB MLI [29,30]. The most common high frequency modulation strategy is
control strategies for CHB MLI [29,30]. The most common high frequency modulation strategy is
carrier-based sine pulse width modulation (SPWM) strategy and a wide range of carrier frequency
carrier-based sine pulse width modulation (SPWM) strategy and a wide range of carrier frequency
(1–12 kHz) is employed to get the switching pulses [27,28,31,32]. The main problem of SPWM strategy
(1–12 kHz) is employed to get the switching pulses [27,28,31,32]. The main problem of SPWM
is that it has severe consequences on switching losses [33]. On the other hand, low frequency
strategy is that it has severe consequences on switching losses [33]. On the other hand, low frequency
modulation strategies provide better output voltage waveform with low total harmonic distortions
modulation strategies provide better output voltage waveform with low total harmonic distortions
(THD) [25,34].
(THD) [25,34].
The main goal of this paper is to introduce a new generalized CMLI topology that could be
The main goal of this paper is to introduce a new generalized CMLI topology that could be
employed to extend any existing single-phase CMLI topology to a three-phase structure without
employed to extend any existing single-phase CMLI topology to a three-phase structure without
tripling the devices used within the single-phase structure. The proposed topology can also be
tripling the devices used within the single-phase structure. The proposed topology can also be
employed by existing three-phase CMLI topologies to reduce its device count without compromising
employed by existing three-phase CMLI topologies to reduce its device count without compromising
its performance. Besides, a low frequency space vector modulation (SVM) technique is applied to
its performance. Besides, a low frequency space vector modulation (SVM) technique is applied to
generate switching pulses. The proposed topology provides an optimized design solution to CMLI
generate switching pulses. The proposed topology provides an optimized design solution to CMLI
in terms of reducing the implementation cost and physical size while maintaining the quality of the
in terms of reducing the implementation cost and physical size while maintaining the quality of the
output voltage waveform.
output voltage waveform.
 Energies 2018, 11, 268 3 of 16
Energies 2018, 11, xFOR PEER 3 of 16

2.2.Proposed
ProposedConcept
Conceptofof3-Phase
3-PhaseCMLI CMLI
Figure1d
Figure 1dshows
showsthe theblock
blockdiagram
diagramofofthe theproposed
proposedthree-phase
three-phaseCMLI, CMLI,ininwhichwhicha acascaded
cascadedstage stage
is connected with the polarity generator (PG) stage at junction point
is connected with the polarity generator (PG) stage at junction point ‘J’. The structure of the cascaded ‘J’. The structure of the cascaded
stageisisnot
stage notfixed
fixedasasititcan
canbe bereplaced
replacedby byany
anyexisting
existingcascaded
cascadedMLI MLItopology.
topology.The Thegreengreenshadedshaded
portions of existing CMLI topologies in Figure 1a–c can be employed
portions of existing CMLI topologies in Figure 1a–c can be employed as a cascaded stage in the new as a cascaded stage in the new
proposed topology. The PG stage is developed by utilizing three Bi-directional (BD) switches andand
proposed topology. The PG stage is developed by utilizing three Bi-directional (BD) switches a
a conventional
conventional three-phase
three-phase twotwo levellevel inverter
inverter (CTPTLI).
(CTPTLI). EachEach BD switch
BD switch consistsconsists
of twoofinsulated
two insulated gate
gate bipolar
bipolar transistors
transistors (IGBT)(IGBT)
and two anddiodes.
two diodes. Both IGBT
Both IGBT switches switches
work work simultaneously
simultaneously to turn to the
turnBDthe
on or off. Three-phase arms A, B, and C exist in the PG stage. A BD switch and two switches in thein
BD on or off. Three-phase arms A, B, and C exist in the PG stage. A BD switch and two switches
the CTPTLI canconsidered
be considered ◦ phase difference among the
CTPTLI can be as aas PGa PGcellcell in each
in each phase
phase arm arm withwith 120phase
120° difference among the
switchingdevices
switching devicesofofthe thethree
threecells.
cells.TheTheCTPTLI
CTPTLIisisfed fedby byaadc-voltage
dc-voltagesupply supply‘V ‘VC’Cof
’ ofaamagnitude
magnitude
greaterthan
greater thanthe
thesummation
summationofofthe theinput
inputvoltage
voltagesupplies
suppliesininthe thecascaded
cascadedstage. stage.
Each pair of the switches, (Sa3 , Sa4 ), or (S b3 , S b4 ), or (S c3
Each pair of the switches, (Sa3, Sa4), or (Sb3, Sb4), or (Sc3, Sc4) within the CTPTLI , S c4 ) within the CTPTLI at different
at different PG cells PG
cells are responsible for generating
are responsible for generating VC and zero V C voltage levels in the output voltage waveform at the outputat
and zero voltage levels in the output voltage waveform
the output
nodes A, B, C.nodes A, B,
For any PGC.cell,
For the
anyPD-switch
PG cell, the is PD-switch
turned off while is turned the off
twowhile the two
switches withinswitches
the CTPTLI within
the CTPTLI operate to generate
operate to generate VC and zero voltage V C and zero voltage level. The pair switches
level. The pair switches in the CTPTLI and the BD switch in the CTPTLI and the
BD switch always function in a toggle mode. As mentioned above,
always function in a toggle mode. As mentioned above, any existing CMLI topology can be utilized any existing CMLI topology can
asbea utilized
cascadedasstagea cascaded stageno
and, hence, and, hence, no
significant significant
change changeinisthe
is required required
switching in the
logicswitching
for existinglogic
for existing CMLI topology when used as a cascaded stage to
CMLI topology when used as a cascaded stage to generate different voltage levels in the proposedgenerate different voltage levels in the
proposed topology.
topology.
InInany
anyPG PGcell,
cell,the
thePD-switch
PD-switchisisonly onlyturned
turnedon onfor forconducting
conductingthe thevoltage
voltagelevels,
levels,whichwhichare are
generated by the cascaded stage to the output points A, B, C. Three
generated by the cascaded stage to the output points A, B, C. Three BD-switches, which are connected BD-switches, which are connected
withthe
with thecascaded
cascadedstage stageatatthe
thejunction
junctionpoint point‘J’‘J’asasshown
shownininFigure Figure1e1eare areoperated
operatedwith withaa120° 120◦phase
phase
difference. Figure 2a shows the simplified structure of the PG stage
difference. Figure 2a shows the simplified structure of the PG stage for generating the voltage levels for generating the voltage levels
VVCC
and
and 0 in0 in
thethe
polepole
voltage VAg V
voltage Ag which
which are achieved
are achieved by toggle by toggle
operation operation Sa3 and SSa3
of switches
of switches and Sa4 .
a4. Figure
Figure 2b shows the conduction path of the inverter when it generates
2b shows the conduction path of the inverter when it generates intermediate levels between VC and intermediate levels between VC
and 0 in the pole voltage. Figure 2c shows
0 in the pole voltage. Figure 2c shows the final pole voltage. the final pole voltage.

b A
a
Levels
between 0
Cascaded stage

Vc Sa3 and Vc
BD-switch-A

A J which shown
Sa4 by dotted
line
g g

Sa3 ON
c
Vc
Sa4 ON
VAg
0
120°
240°
Figure 2. Simplified structure of the proposed CMLI, (a) generation of maximum and zero voltage
Figure 2. Simplified structure of the proposed CMLI, (a) generation of maximum and zero voltage
levels; (b) intermediate level generation; (c) pole voltage waveform. Reprint with permission
levels; (b) intermediate level generation; (c) pole voltage waveform. Reprint with permission
[4261051118814]; 2018, IEEE.
[4261051118814]; 2018, IEEE.

If VAg, VBg, VCg are the pole voltages, then the line voltage, VAB, VBC, VCA can be derived as below,
Energies 2018, 11, 268 4 of 16

Energies 2018, 11, xFOR PEER 4 of 16

If V Ag , V Bg , V Cg are the pole voltages, then the line voltage, V AB , V BC , V CA can be derived
as below,
11 −−11 00
    
VAB VAg
=
 VBC  =  00 11 −−1
  
1  VBg
  (1)
(1)
−1 0 1

VCA −1 0 1 VCg

3. Proposed
3. Proposed CMLI
CMLI Using
Using H-Bridge
H-Bridge Topology
Topology as Cascaded Stage
Cascaded H-Bridge
Cascaded H-Bridge (CHB)
(CHB)MLI MLItopology
topology is is
a well-established
a well-established structure for single
structure and three-phase
for single and three-
applications
phase [35]. The
applications [35].cascaded stagestage
The cascaded in theinproposed generalized
the proposed CMLI
generalized is facilitated
CMLI to utilize
is facilitated any
to utilize
single-
any or three-phase
single- or three-phasestructure as shown
structure in Figure
as shown 1. 1.
in Figure
The conventional
The conventional CHB CHB MLIMLI topology
topology shown
shown inin Figure
Figure 33 for
for n-number
n-number of of CHB
CHB cells
cells is
is chosen
chosen to to
validate the
validate theproposed
proposed three-phase
three-phase inverter concept.
inverter The proposed
concept. three-phase
The proposed MLI structure
three-phase MLI involving
structure
three CHBthree
involving cells CHB
in thecells
cascaded
in the stage is shown
cascaded stageinis Figure
shown4a.in Figure 4a.

Figure 3. Conventional three-phase CHB-MLI. Reprint with permission [4261051118814]; 2018, IEEE.
Figure 3. Conventional three-phase CHB-MLI. Reprint with permission [4261051118814]; 2018, IEEE.

The number of CHB cells in the cascaded stage can be increased in order to achieve more levels
in theThe number
output of CHB
voltage cells in the
waveform. cascaded
Each H-bridgestage cellcan (k)becomprises
increased in order
four to achieve
switches (Gk1,more
Gk2, Glevels in
k3, Gk4)
the output voltage waveform. Each H-bridge cell (k) comprises
and a dc-power supply (Vk) as depicted in Figure 4b. Any CHB cell is able to produce four switches (G k1 , G , G
k2 three, G ) and
k3 different
k4 a
dc-power
voltage supply
levels (Vk,(V ) as
0, k−V depicted in Figure 4b. Any CHB cell is able to produce three different voltage
k) in the output voltage, Vout. Table A1 in the Appendix A shows the switching
levels (V , 0,
logic to achieve
k − V )
the in the threeVoutput
output voltage,
k aforementioned out . Table A1 in the Appendix A shows the switching logic
voltages.
to achieve
Symmetricthe aforementioned
and asymmetric three output voltages.
structures are proposed for conventional CHB MLI topology in
[35,36], respectively. Asymmetric methodsare
Symmetric and asymmetric structures areproposed
found superior for conventional
than theCHB MLI topology
symmetric in terms in [35,36],
of the
respectively. Asymmetric methods are found superior than the
number of levels in the output voltage as presented in [35]. In [37], an asymmetric CHB MLI is symmetric in terms of the number of
levels in thewhere
presented, output thevoltage as presented
dc voltage in kept
ratios are [35]. Inin [37],
binary an formasymmetric
(1:2 … CHB MLITrinary
2n). The is presented, where
ratio format
the dc voltage ratios are kept in binary form (1:2 . . . 2 n ). The Trinary ratio format (1:3: . . . :3n ) has
(1:3: … :3 ) has been also proposed for CHB MLI asymmetric structure [38]. The new proposed three-
n

been also
phase CMLI proposed
conceptfor CHBpaper
in this MLI asymmetric
can adopt both structure
symmetric [38]. and The asymmetric
new proposed three-phase
structure of theCMLI
CHB
concept in this paper
MLI in the cascaded stage. can adopt both symmetric and asymmetric structure of the CHB MLI in the
cascaded stage.
As mentioned above, the magnitude of the VC should be greater than the summation of the
As mentioned
connected above, in
voltage supplies thethe
magnitude of the IfVV
cascaded stage. C1,should
V2, …, V be3 are
greater than voltages
the input the summation of the
for n-number
connected voltage supplies in the cascaded stage. If V 1 , V 2 , . . . , V 3 are
of cells in the cascaded stage, then the following respective equations for symmetric, binary-related the input voltages for n-number
and trinary-related input supplies can be written,
= ; = ;…; = (2)

= ; = 2 ;…; =2 (3)
Energies 2018, 11, 268 5 of 16

of cells in the cascaded stage, then the following respective equations for symmetric, binary-related
and trinary-related input supplies can be written,

V1 = v; V2 = v; . . . ; Vn = v (2)
Energies 2018, 11, xFOR PEER 5 of 16
V1 = v; V2 = 21 v; . . . ; Vn = 2n−1 v (3)

V1 ==v; ;V2 ==313v; .;.…

. ;; Vn =
=33n −1 v (4)
(4)
where ‘v’
where ‘v’ is
is the
the per
per unit
unit voltage
voltage value.

N
Gk1 Gk4

load

load

load
Vk Vout

Gk2 Gk3

CHB-cell Vc Sa3 Sb3 Sc3

(b) A B C

CHB Sa4 Sb4 Sc4

V3 cell-3

CHB
V2 cell-2
BD-switch-C
BD-switch-B
BD-switch-A

J
G11 G14

V1
G12 G13
Bi-directional switches
CHB stage g (a)

Figure 4. Proposed three-phase CMLI (a) CHB cells are considered as cascaded stage; (b) a standard
Figure 4. Proposed three-phase CMLI (a) CHB cells are considered as cascaded stage; (b) a standard
CHB cell. Reprint with permission [4261051118814]; 2018, IEEE.
CHB cell. Reprint with permission [4261051118814]; 2018, IEEE.

The input voltage-supply of the CTPTLI, VC can be calculated from,

The input voltage-supply of the CTPTLI, V C can be calculated from,
=n + = + + ⋯+ + (5)
VC = ∑ Vx + V1 = (V1 + V2 + . . . + Vn ) + v (5)
0
Figure 5 shows the conduction path for generating the pole voltage. In Figure 5, the magnitudes
Figure 5 shows the conduction path for generating the pole voltage. In Figure 5, the magnitudes
of the CHB cells input voltage supplies are considered symmetric i.e., V1 = V2 = V3 = v; VC = 4v. With
of the CHB cells input voltage supplies are considered symmetric i.e., V 1 = V 2 = V 3 = v; V C = 4v.
the contribution of CTPTLI and CHB cells along with the BD-switches, pole voltages, VAg, VBg, VCg are
With the contribution of CTPTLI and CHB cells along with the BD-switches, pole voltages, V Ag , V Bg ,
produced. Only the CTPTLI switches operate to generate the voltage levels, VC and 0 as shown in
V Cg are produced. Only the CTPTLI switches operate to generate the voltage levels, V C and 0 as shown
Figure 5a,e, respectively. The other voltage levels, (V1 + V2 + V3), (V1 + V2), V1 between 0 and VC levels
in Figure 5a,e, respectively. The other voltage levels, (V 1 + V 2 + V 3 ), (V 1 + V 2 ), V 1 between 0 and
are produced using different switching logics among the CHB cells, when the BD-switches are turned
V levels are produced using different switching logics among the CHB cells, when the BD-switches
on.C Figure 5e shows the pole voltage output, VAg, which can be obtained by the above mentioned
are turned on. Figure 5e shows the pole voltage output, V Ag , which can be obtained by the above
switching operation.
mentioned switching operation.
While Figure 5 explains the generation of one arm pole voltage, VAg; the other two pole voltages
While Figure 5 explains the generation of one arm pole voltage, V Ag ; the other two pole voltages
follow the same switching logics with 120° phase shift among the PG-cells. The switching function
follow the same switching logics with 120◦ phase shift among the PG-cells. The switching function for
for each phase arm lasts for 120° phase angle.
each phase arm lasts for 120◦ phase angle.
Energies 2018, 11, 268 6 of 16
Energies 2018, 11, xFOR PEER 6 of 16

Figure 5.
Figure Differentswitching
5. Different switchinglogics
logicsforfor generating
generating four
four levels
levels in in
thethe pole
pole voltages:
voltages: (a) level
(a) level 3v;
3v; (b)
(b) Level 2v; (c) Level v; (d) Level 0; (e) Complete cycle of the pole voltage. Reprint with permission
Level 2v; (c) Level v; (d) Level 0; (e) Complete cycle of the pole voltage. Reprint with permission
[4261051118814]; 2018,
[4261051118814]; 2018, IEEE.
IEEE.

4. Implementation
4. Implementation of
of the
the Proposed
Proposed MLI
MLI
The proposed
The proposed MLI topology
topology inin Figure
Figure 44 is
is controlled
controlled with
with aa low
low frequency
frequency staircase
staircase modulation
modulation
strategy [39,40]. The switching states follow a specific
strategy [39,40]. The switching states follow a specific sequence in sequence in the d-q plane. The number of
The number of
switching states, S in the
switching the d-q
d-q plane
plane isis an
an essential
essential factor
factor to
to generate
generate the
the output
output voltage
voltage levels
levels and
and can
can
be expressed
be expressed as,
S = 6( NP − 1); NP > 1 (6)
S = 6 ( N P − 1 ) ; NP > 1 (6)
where NP is the number of levels in the pole voltages.
where The NPnumber
is the number of levels
of switching in the
states formspole voltages.
different hexagons as shown in Figure 6 to achieve different
The number of switching states
number of levels in the pole voltage waveforms. forms different hexagons as shown in Figure 6 to achieve
different number
In Figure of levels
6, the in the
smallest pole voltage
hexagon waveforms.
represents the switching states for NP = 2 and the following
In Figure
is for6,Nthe smallest hexagon represents the switching states for NP = 2 and the following
hexagons P = 3, NP = 4, and NP = 5; respectively. According to Figure 5, the proposed topology
hexagons
generates is Nfor NP = 3, NP = 4, and NP = 5; respectively. According to Figure 5, the proposed topology
P = 5 in the pole voltages. Hence, the most upper hexagon in Figure 6 is appropriate for
generates N P = 5 in the pole voltages. Hence, the most upper hexagon in Figure 6 is appropriate for
getting 24 switching states to generate five voltage levels, 4v, 3v, 2v, v, 0 in the pole voltages.
getting 24 switching states to generate five voltage levels, 4v, 3v, 2v, v, 0 in the pole voltages.
The 24 switching states are, 044, 043, 042, 041, 040, 140, 240, 340, 400, 430, 420, 410, 400, 401, 402,
The 24 switching states are, 044, 043, 042, 041, 040, 140, 240, 340, 400, 430, 420, 410, 400, 401, 402,
403, 404, 304, 204, 104, 004, 014, 024, 034. Each of the switching states has three switching vectors,
403, 404, 304, 204, 104, 004, 014, 024, 034. Each of the switching states has three switching vectors, Sa,
Sa , Sb , Sc for three-phase voltage generation. The pole voltages, V Ag , V Bg , V Cg are taken as reference
Sb, Sc for three-phase voltage generation. The pole voltages, VAg, VBg, VCg are taken as reference to
achieve the three switching vectors in each switching state at any instant of time [39]. In general, the
switching angles, φ for each of the switching states are equal and can be calculated from,
Energies 2018, 11, 268 7 of 16

Energies 2018, 11, xFOR PEER 7 of 16

to achieve the three switching vectors in each switching state at any instant of time [39]. In general,
the switching angles, ϕ for each of the switching states are equal and can be calculated from,
φ = 360°/S (7)
◦
Hence, the switching angle of each of theϕ24 = 360 /S
switching state is 15°. This means, a new switching (7)
state will come into operation every 15°. In the switching sequence of 24 switching states, the
Hence, the switching ◦ . This means, a new switching
switching vectors 4, 3, 2, 1,angle
0 areofcombined
each of the in 24
answitching
organisedstate is 15to
manner generate three pole voltages
state will come into operation every 15 ◦ . In the switching sequence of 24 switching states, voltage
the switching
and the switching vectors always abide by Table A2 in the Appendix A for different level
vectors 4,
generation. 3, 2, 1, 0 are combined in an organised manner to generate three pole voltages and the
switching vectors always abide by Table A2 in the Appendix A for different voltage level generation.

q
140 240 340

130 230

120

400
100
044

022

011
033

300
200 d

102

103 203

104 204 304

Figure
Figure 6.
6. Generalized
Generalized switching
switchingstates
statesfor
forgenerating
generatingdifferent
differentnumber
numberof
oflevels
levelsin
inthe
thepole
polevoltage.
voltage.
Reprint
Reprint with
with permission
permission [4261051118814];
[4261051118814]; 2018,
2018, IEEE.
IEEE.

The real time switching signals are obtained using digital signal processor, TMS320F2812 (Texas
The real time switching signals are obtained using digital signal processor, TMS320F2812 (Texas
Instruments, Dallas, TX, USA). The implementation requires 12 IGBTs for three CHB cells in the
Instruments, Dallas, TX, USA). The implementation requires 12 IGBTs for three CHB cells in the
cascaded stage and 12 IGBTs in the PG cells. A laboratory prototype is developed to validate the
cascaded stage and 12 IGBTs in the PG cells. A laboratory prototype is developed to validate the
feasibility of the proposed inverter.
feasibility of the proposed inverter.
Figure 7 shows the developed hardware prototype model. A total of 21 general-purpose
Figure 7 shows the developed hardware prototype model. A total of 21 general-purpose
input/output (GPIO) pins are required in the DSP, TMS320F2812 for achieving all real-time switching
input/output (GPIO) pins are required in the DSP, TMS320F2812 for achieving all real-time switching
signals. Sixteen (GPIOA0-GPIOA15) pins are chosen from GPIO-A while the remaining one pin is
signals. Sixteen (GPIOA0-GPIOA15) pins are chosen from GPIO-A while the remaining one pin is
chosen from GPIO-B (GPIO B0) pin array. The gate signals of phase B and C within the three PG-cells
chosen from GPIO-B (GPIO B0) pin array. The gate signals of phase B and C within the three PG-cells
have similar pattern as in phase-A with a phase shift of 120°◦ and 240°, respectively.
have similar pattern as in phase-A with a phase shift of 120 and 240◦ , respectively.
Six IGBTs, IRG4BC40W, 600 V/20 A along with six diodes, RHRP1540, 400 V/15 A are used for
Six IGBTs, IRG4BC40W, 600 V/20 A along with six diodes, RHRP1540, 400 V/15 A are used
the three BD-switches in the PG-stage while 18 IGBTs, HGTG20N60B3D, 600 V/40 A are used to build
for the three BD-switches in the PG-stage while 18 IGBTs, HGTG20N60B3D, 600 V/40 A are used to
the CHB cells in the cascaded stage and CTPTLI. A four channel digital storage oscilloscope,
build the CHB cells in the cascaded stage and CTPTLI. A four channel digital storage oscilloscope,
Tektronix TPS 2014 (Tektronix Inc., Beaverton, OR, USA) is utilized to capture the experimental
Tektronix TPS 2014 (Tektronix Inc., Beaverton, OR, USA) is utilized to capture the experimental output
output waveforms and analyse total harmonic distortion (THD).
waveforms and analyse total harmonic distortion (THD).
Energies 2018, 11, xFOR PEER 8 of 16
Energies 2018, 11, 268 8 of 16
Energies 2018, 11, xFOR PEER 8 of 16

Figure 7. Experimental prototype hardware model. Reprint with permission [4261051118814]; 2018,
IEEE.
Figure 7. Experimental
Experimentalprototype hardware
prototype model.
hardware Reprint
model. with with
Reprint permission [4261051118814];
permission 2018,
[4261051118814];
5. Results and Discussions
IEEE.IEEE.
2018,

Table A3 in the Appendix A shows system specification of the implemented inverter. To validate
5. Results and Discussions
the feasibility of the proposed topology, its performance in terms of output voltage/current
Table A3
Table
waveforms A3 in the
in
along Appendix
with the THD A showshas been system specification
compared with of thetheperformance
implemented ofinverter.
the MLITotopology
validate
feasibility
presented
the feasibility of of
in [5,40]. the
theAs proposed
will
proposed be elaborated
topology,topology,below,
its itswhile
performance performance
the terms in
inproposed terms
topology
of output of in output voltage/current
this paper
voltage/current can reduce
waveforms
waveforms
the MLI
along device
with along
the THD with
count has the THD
significantly,
been compared has been
with compared
it almost provides
the withsame
the
performance the
of theperformance
MLI topology of the MLI topology
MLI
presented topology
in [5,40].
presented
presented
As will bein in [5,40]. Results
elaborated As below,
will be elaborated
in while
various thetestbelow,
cases are
proposed while the proposed
demonstrated
topology in thisin topology
paper can in
the following thissub-sections.
reduce paper
the MLIcan reduce
device
the MLI
count device count
significantly, significantly,
it almost providesitthe almost
sameprovides
performance the same
of theperformance
MLI topology of presented
the MLI topology
in [5,40].
A. H-bridge cells symmetric input supplies
presented
Results in [5,40].test
in various Results
casesin arevarious test cases
demonstrated inare
thedemonstrated in the following sub-sections.
following sub-sections.
The input dc-voltage sources are connected such as V1 = V2 = V3 = v = 70 V and VC = 4v = 280 V.
A. H-bridge cells symmetric input supplies
Inductive 3-phase load (Z = 55 + j 37.68 Ω/phase) is considered for testing the inverter performance.
Figure input
The input dc-voltage
8a shows sourcesvoltage,
the junction
dc-voltage sources areconnected
are connected
VJg andsuch such asVV1 1==VV22V==AgV
poleasvoltages, V, 33V==
Bgv,vV==Cg70 V
V and VCC ==4v
, respectively.
70 4v==shown
As 280
280V.V.
in the figure,
Inductive the pole
3-phase (Z = 55 comprise
loadvoltages ++ jj 37.68 Ω/phase)
37.68 Ω/phase)
five levels isis(280
considered
V, 210 V,
considered for
for testing
140 V, 70the
testing V, inverter
the 0) while performance.
inverter Vperformance.
Jg comprises

Figure
threeFigure
levels 8a8ashows
(210 shows
V, 140 theV,
the junction voltage,
70 V). voltage,
junction Figure VV
8b,c andpole
show
JgJgand pole voltages,
thevoltages, VV
load voltages, AgAg, ,V VBg , V, Cg
VBgAN V,BN
Cg ,respectively.
, VCN, and their
respectively. As shown
THD,
respectively.
in the figure,The the relation between
pole voltages the pole
comprise five levels (280
voltages VAg, VV,Bg210 V,
, VCgV, 140load
, and
140 V,70
V, 70voltages
V,V,0)0)while
while
canVVbeJg
Jg comprises
expressed
comprises
three levels (210
by, (210 V, V, 140
140 V, V, 70
70V).
V).Figure
Figure8b,c 8b,cshow showthe theload
load voltages,
voltages, VAN V,ANVBN , ,VVBN
CN,, V
and
CN ,their
and THD,
their
respectively.
THD, The relation
respectively. between
The relation the pole
between thevoltages VAg, VBgV
pole voltages ,VAgCg,, V
and
Bg , load
V Cg , voltages
and loadcan be expressed
voltages can be
by,
expressed by, 1 2 −1 −1
= −1 2 −1  (8)
3 2 −1 −1
  
VAN −1 −1 2 VAg
1 2 −1 −1
 VBN  = =1−−1 1 2 2 −−1 1  VBg  (8)
    
3 (8)
On the other hand, the line VCN voltages, V 3
AB, VBC, VCA shown in Figure 9a comprise nine levels
−−11 −−1 1 22 VCg
(280 V, 210 V, 140 V, 70 V, 0 V, −70 V, −140 V, −210 V, −280 V).
On the other hand, the line voltages, VAB, VBC, VCA shown in Figure 9a comprise nine levels
(280 V, 210 V, 140 V, 70 V, 0 V, −70 V, −140 V, −210 V, −280 V).
VJg VAN VCN
250V VBN
VAg
VJg VAN VCN
250V VBN Load voltage harmonics
VBg VAg
(c) harmonics
2.5ms 2.5ms

100V Load voltage

(b)
VCg
2.5ms 2.5ms

VBg
(a) (c)
100V
(b)
VCg
Figure
Figure 8. (a)
8. Experimental
Experimental results of
results of (a)
(a) Junction
Junctionvoltage,
voltage,andandPole
Polevoltages
voltageswhen
when the
the CHB-cells
CHB-cells areare
fedfed
by
by symmetric
symmetric dc-power
dc-power supplies;
supplies; (b)(b)
load load voltage;
voltage; (c) (c)
loadload voltage
voltage harmonics.
harmonics.
Figure 8. Experimental results of (a) Junction voltage, and Pole voltages when the CHB-cells are fed
by symmetric dc-power supplies; (b) load voltage; (c) load voltage harmonics.
Energies 2018, 11, 268 9 of 16

On the other hand, the line voltages, V AB , V BC , V CA shown in Figure 9a comprise nine levels
(280 V, 210 V, 140 V, 70 V, 0 V, −70 V, −140 V, −210 V, −280 V).
Energies 2018, 11, xFOR PEER 9 of 16

VAB
2A
250V IAN IBN ICN
VBC

VCA

2.5ms
(a) (b)
5ms

Line voltage THD Line current THD

(c) (d)

Figure 9. Experimental results, (a) line voltages; (b) line currents; (c) THD of the line voltage; (d) THD
Figure 9. Experimental results, (a) line voltages; (b) line currents; (c) THD of the line voltage; (d) THD
of the line current, when CHB cells are fed by Symmetric dc power supplies.
of the line current, when CHB cells are fed by Symmetric dc power supplies.
Figure 9b shows the three-phase line currents, IAN, IBN, ICN. It is worth mentioning that no
harmonic
Figure 9bfilter
showswasthe
used in the implemented
three-phase hardware
line currents, IANsetup.
, IBN ,The
ICNtotal
. It harmonic
is worth distortion
mentioning(THD)
that no
of the unfiltered line voltage and line current are 9.27% and 2.09%; respectively as shown
harmonic filter was used in the implemented hardware setup. The total harmonic distortion (THD) of in Figure
9c,d, respectively. The THD of the line current and voltage must be less than 5%, to comply with the
the unfiltered line voltage and line current are 9.27% and 2.09%; respectively as shown in Figure 9c,d,
IEEE standard [41]. While the current THD complies with the mentioned standard, voltage THD is
respectively. The THD of the line current and voltage must be less than 5%, to comply with the IEEE
more than 5% in the implemented 9-level CMLI topology. Voltage THD can be reduced by increasing
standard [41]. While
the number theincurrent
of levels THD
the output complies with the mentioned standard, voltage THD is more
voltage.
than 5% in the implemented 9-level CMLI topology. Voltage THD can be reduced by increasing the
B. H-bridge cells Trinary-related input supplies
number of levels in the output voltage.
In the proposed topology, the number of levels in the output voltages can be increased by
B. H-bridge cells Trinary-related input supplies
considering asymmetric trinary ratio for the input dc supplies. According to (3) the magnitudes of
V1, the
In V2, Vproposed
3 are set to 20 V, 60 V, 180 V; respectively and hence the magnitude of VC is 280 V.
topology, the number of levels in the output voltages can be increased by
This configuration
considering asymmetric trinary is ableratio
to generate
for the 15-levels
input dc(N P = 15) in the pole voltage and 29-levels in the
supplies. According to (3) the magnitudes of V 1 ,
line voltage. Hence, it needs 84-switching states to generate three-phase output voltages according
V 2 , V 3 are set to 20 V, 60 V, 180 V; respectively and hence the magnitude of V C is 280 V.
to (5). Table A4 in the Appendix A shows the switching logics for generating 15 levels in the pole
This configuration is able to generate 15-levels (NP = 15) in the pole voltage and 29-levels in the
voltage. The junction voltage, and line voltage, VAB are shown in Figure 10a. Figure 10b shows 29-
line voltage. Hence, itline
level three-phase needs 84-switching
voltages on the samestates
plot. to
Thegenerate
THD of thethree-phase
unfiltered output
29-levelvoltages according
line voltages is
to (5).nearly
Table5%A4 in the Appendix
as shown in Figure 10c. A shows the switching logics for generating 15 levels in the pole
voltage. The junction voltage, and line voltage, V AB are shown in Figure 10a. Figure 10b shows 29-level
C. Three-phase conversion of existing single-phase inverter topologies
three-phase line voltages on the same plot. The THD of the unfiltered 29-level line voltages is nearly
5% as shown A number of single
in Figure 10c. phase MLI topologies along with different input voltage algorithms have
been recently published [12–15,17–23]. The proposed three-phase inverter concept in this paper
C. Three-phase
permits easyconversion
conversionofofexisting single-phase
the existing inverter
single phase MLI topologies
into three-phase structures without tripling
the number of semiconductor switches and dc-supplies as per the current conventional practice. To
A number of single phase MLI topologies along with different input voltage algorithms have been
do so, only the PG stage in the proposed topology is required to be connected with any existing single
recently published [12–15,17–23]. The proposed three-phase inverter concept in this paper permits easy
phase topology.
conversion of the existing single phase MLI into three-phase structures without tripling the number of
Energies 2018, 11, 268 10 of 16

semiconductor switches and dc-supplies as per the current conventional practice. To do so, only the
PG stage in the proposed topology is required to be connected with any existing single phase
Energies 2018, 11, xFOR PEER
topology.
10 of 16
ToEnergies
extend 2018,any existing
11, xFOR PEER single-phase inverter to three-phase structure using the proposed 10 ofconcept,
16
To extend
switching logics of theany existing
single phasesingle-phase inverter can
cascaded inverter to three-phase
be retained. structure using
Figure 11a the proposed
shows a single phase
topology To extend
concept, switching
published any
in [12]existing
logics of thesingle-phase
while single phase
Figure inverter
cascaded
11b shows toinverter
the three-phase
extended bestructure
retained.using
canthree-phase Figurethe
11aproposed
structure shows
of thisasingle
concept,
single switching
phase topologylogics of the single
published in [12]phase
while cascaded
Figure inverter
11b shows can
the be retained.
extended Figure 11astructure
three-phase shows a
phase inverter using the proposed concept in this paper. As shown in Figure 11b, the single phase
single
of this phase
single topology published
phase inverter usinginthe
[12]proposed
while Figure
concept11bin
shows the extended
this paper. three-phase
As shown in Figurestructure
11b, the
topology acts as a cascaded stage and generates all possible voltage levels by following the same
of thisphase
single singletopology
phase inverter
acts asusing the proposed
a cascaded stage and concept in this
generates paper. As
all possible shownlevels
voltage in Figure 11b, the
by following
switching
single
the
logic
same phase proposed
topology
switching
in [12].
acts
logic as a cascaded
proposed in [12].stage and generates all possible voltage levels by following
the same switching logic proposed in [12].

VJg
VJg

VAg
100 V VAg VBg 100 V
100 V

2.5ms
VBg 100 V

2.5ms
(b)
VAB (b)
(a) VAB
2.5ms

(a)
2.5ms

Line voltage THD

Line voltage THD
(c)
(c)

Figure 10. Experimental results, (a) Junction voltage, pole voltages (VAg, VBg), line voltage (VAB); (b)
10. Experimental
Figure29-level
Figure 10. Experimental
3-phase results,
line voltages; (a)(a)
results,
(c) Junction
THDJunction voltage,
of the voltage,
line pole
pole
voltage, voltages
voltages
when CHB (V are
(Vcells
Ag, VAg
V Bgby
, fed
Bg), line
), line
voltage voltage
(Vrelated
trinary AB); (b)
(V AB );
(b) 29-level 3-phase
29-level
dc power 3-phaseline
line
supplies. voltages;
voltages;
Reprint with(c)permission
THDof
THD ofthe
the linevoltage,
line voltage,
[4261051118814]; when
when CHB
2018, CHB
cellscells
IEEE. areby
are fed fedtrinary
by trinary
relatedrelated
dc power supplies.
dc power Reprint
supplies. with
Reprint permission
with permission[4261051118814]; 2018,
[4261051118814]; 2018, IEEE.
IEEE.
N
N
loadload

loadload

loadload

Sʹ1 V1,1
Sʹ1 V1,1
V1,1 Sʹ1 V1,1
Sʹ1 V1,1 Sʹ2
V1,1
S1,1
Sʹ2 V1,1 S1,1
Sʹ2
Vc Sa3 Sb3 Sc3
V1,1
Sʹ2 V2,1 S1,1
S4,1 Vc SAa3 Sb3
B SCc3
V2,1 S1,1
S4,1 A Sa4 B Sb4 C Sc4
Generator

S2,1
V2,1
S2,1 S4,1
S5,1
V2,1 S4,1 T3 V3,1
T1
Generator

V3,1
S2,1
S5,1 S2,1
S5,1
Sa4 Sb4 Sc4
S3,1
LoadLoad

T1 T3 V3,1
S5,1
Generator

S3,1
V3,1
Polarity

S3,1
T2
Generator

Generator

S3,1 T4 V1,2
Polarity

V1,2 T2
Generator

T4 S1,2
BD-switch-C
BD-switch-B

V1,2
BD-switch-A

S1,2
J
Level

V1,2
V2,2 S1,2
BD-switch-C
BD-switch-B
BD-switch-A

S1,2 S4,2
J
Level

Level

V2,2 S4,2 S2,2

V2,2
S2,2 S4,2
Level

V2,2 S5,2
S4,2
S5,2 V3,2
S2,2
V3,2
S2,2 S5,2
S3,2
V3,2 (a)
S3,2 S5,2
V3,2 (a) Bi-directional switches
S3,2 (a)
S3,2 (a) Cascaded stage Bi-directional
g switches
Cascaded stage g
(b)
(b)
Figure 11. Three-phase conversion of a single phase topology (a) existing single phase topology
Figure
Figureproposed 11.inThree-phase
11. Three-phase conversion
[12]; (b) three-phase
conversion ofofaasingle
single
conversion phase topology
of existing
phase topology(a)
topology existing
according
(a) tosingle
existing phase
thesingle
concept topology
proposed
phase topology
proposed
in in [12]; (b) three-phase conversion of existing topology according to the concept proposed
this paper.
proposed in [12]; (b) three-phase conversion of existing topology according to the concept proposed in
in this paper.
this paper.
 Structure Phase Conversion Concept

Line Voltage Levels

Line Voltage Levels

Line Voltage Levels

DC-Supplies

DC-Supplies

DC-Supplies
Switches

Switches

Switches
Topology
Energies 2018, 11, 268 11 of 16

The bidirectional and CTPTLI switches operate as shown in Figure 2. In [12], the single phase
structure produces 15-levels in the line voltage, when Figure 12a is set with V 11 = V 21 = V 31 = V 21 =
Non-isolated inverter topology [9] 15 12 7 15 36 21 17 24 8
V 22 = V 23 = V’
DC-link 0 = 40 V and
half-bridge V C = 280 V. The cascaded stage in Figure 11b is arranged in a similar pattern
cascaded
by imitatinginverter
the single-phase
[21] structure 13 12 6 conversion.
for three-phase 13 36 18 15 24 7

VJg
VAB VBC VCA

100 V
VAg 100 V (b)

2.5ms
VBg

VAB
2.5ms

(a)

Figure 12.
Figure 12. Experimental
Experimental results,
results, (a)
(a) Junction
Junction voltage,
voltage, pole
polevoltages
voltages(V , V, Bg
(VAgAg V),Bgline voltages
), line (VAB
voltages (V);AB
(b)
);
17-level three-phase line voltages.
(b) 17-level three-phase line voltages.

Figure 11b, the single phase topology acts as a cascaded stage and generates all possible voltage
levels by following the same switching logic proposed in [12]. The bidirectional and CTPTLI switches
operate as shown in Figure 2. In [12], the single phase structure produces 15-levels in the line
voltage, when Figure 12a is set with V 11 = V 21 = V 31 = V 21 = V 22 = V 23 = V’0 = 40 V and V C = 280 V.
The cascaded stage in Figure 11b is arranged in a similar pattern by imitating the single-phase structure
for three-phase conversion.
Table 1 provides a comparison of using the concept proposed in this paper and conventional
methods to transfer single-phase to three-phase structure.

Table 1. Comparison between three-phase conversion of a single-phase structure using conventional

methods and proposed concept in this paper.

Conventional 3 Phase This Paper Proposed

Single Phase Structure
Conversion Concept
Line Voltage Levels

Line Voltage Levels

Line Voltage Levels

DC-Supplies

DC-Supplies

DC-Supplies
Switches

Switches

Switches

Topology

Non-isolated inverter topology [9] 15 12 7 15 36 21 17 24 8

DC-link half-bridge cascaded
13 12 6 13 36 18 15 24 7
inverter [21]

The table reveals the superior advantages of the proposed concept over existing conventional
methods in terms of reducing the number of switches and dc-supplies while increasing the levels in
the output voltages when a single phase structure is extended to three-phase one.
The three-phase inverter in Figure 11b produces nine levels in the pole voltages and 17-levels
in the line voltage. It requires 48-switching states to produce these voltage levels according to (5).
Table A5 in the Appendix A shows the switching logic for this inverter. Figure 12a shows the junction
Energies 2018, 11, 268 12 of 16

voltage, V Jg , pole voltages and line voltage, V AB of the extended three-phase inverter. Figure 12b
shows the three-phase 17-level line voltages on the same plot.

6. Semiconductor Losses and Inverter Efficiency

Semiconductor losses are considered as a crucial design factor for any converter circuit, which
influences and defines the required thermal management and contributes to the estimation of overall
cost, volume and weight of the inverter. There are two dominant losses in the semiconductor devices;
the static and the dynamic losses. The on-state resistance and the forward voltage drop of the
semiconductor device are responsible for the static (conduction) losses, while the dynamic losses are
produced during the ON-OFF actions dictated by the switching frequency of the device [39].
The overall semiconductor losses of the proposed CMLI can be estimated by the total conduction
and switching losses of all used semiconductors as below:

Ptotal_loss = Pc (t) + Psw (9)

If the output power is Pout , the inverter efficiency (η) can be calculated from:
 
Pout
η% = × 100% (10)
Ptotal_loss + Pout

The output power is calculated from:

√ V Iline
Pout = 3 × √C × √ × PF (11)
2 2

where V C and Iline are the input voltage to the CTPTLI and output line current, respectively.
The proposed topology (Figure 4b) in this paper utilizes IGBT with anti-parallel diode
(HGTG20N60B3D) in the cascaded structure and IGBT (IRG4BC40W) along with diode (RHRP1540)
in the PG structure. The following parameters are used to calculate the switching losses; VT = 1.8 V,
RT = 0.10, VD = 1.2 V, RD = 0.1, β = 1, ton = toff = 1 µs. where, the on-state voltage drop of the transistor
and diode are expressed by VT and VD , respectively. The on-state resistances of the transistor and
diode, are given by RT and RD , respectively. The transistor amplification factor and ON-OFF time is
expressed by ‘β’, ton and toff , respectively.
Total switching loss is found to be Ptotal_loss = 2.9067 watt with 1.3076 watt losses associated in the
cascaded stage and 1.5991 watt in the PG stage. For a connected load of 0.82 lagging power factor (PF)
and by using (15), the output power is 98.64 watt which gives an overall efficiency of about 97%.

7. Comparison with Other Topologies

As shown in the results section, the proposed three-phase MLI concept can be adopted to extend
any existing single-phase topology to three-phase without tripling the used components as per the
current conventional methods. Furthermore, the proposed concept is able to reduce the size of the
existing three-phase cascaded MLI topologies in terms of device count without degrading the quality
of the output voltage. A comparison is performed in order to show the effectiveness of the proposed
three-phase cascaded MLI concept over various existing topologies. Different factors such as number
of power semiconductor components, number of gate driver circuits and number of dc-supplies are
considered in the comparison.
Table 2 shows a comparison among existing three-phase CHB MLI topologies and the three-phase
MLI concept proposed in this paper. The CHB inverter proposed in [35], has two CHB cells and binary
relation is maintained between the input dc-supplies in each phase arm.
Energies 2018, 11, 268 13 of 16

Table 2. Comparison among conventional three-phase CHB topologies and the proposed three-phase
cascaded MLI for different asymmetric input voltage arrangements.

Binary Related Two CHB Trinary Related Three CHB Trinary Related Four CHB
Cell Topology [35] Cell Topology [42] Cell Topology [38]

Proposed New Concept

Proposed New Concept

Proposed New Concept

Existing 3-Phase

Existing 3-Phase

Existing 3-Phase
Category

No of levels in line voltage 7 9 27 29 81 83

No of switches 24 20 36 24 48 28
No of diodes 24 20 36 24 48 28
No of gate driver 24 20 36 24 48 28
No of dc supplies 6 3 9 4 12 5

On the other hand, trinary related three and four CHB cells in each phase arm is considered
in [38,42], respectively. A significant reduction in the device count can be realized when the new
three-phase cascaded MLI concept is applied to these existing topologies as can be seen in Table 2.
The percentage of reduction of device count and the input dc supplies is increasing when the number
of CHB cells in each phase arm is increasing. For example, 17% reduced power electronic components
is achieved in the proposed three-phase cascaded MLI concept for two CHB cell, while 33% and 42%
reduction will be achieved when the proposed concept is applied for three and four CHB cells in each
phase arm of the existing topologies, respectively.

8. Conclusions
This paper presents a new design for a three-phase CHB MLI. Experimental results validate the
practical feasibility of the proposed three-phase MLI concept. Comparison with published three-phase
MLI topologies shows the superiority of the proposed concept over existing topologies in terms of
reduced device count without compromising the quality of the output voltage. Moreover, the proposed
concept can be adopted to extend any single phase MLI to three-phase structures without tripling its
components as per the current practice. The new technique can be adopted by existing three-phase
topologies to reduce its device count without degrading the overall performance. Since the number of
components is directly related to the cost, complexity and the installation area, the new three-phase
concept is a cost-effective technique that is expected to have a great potential for renewable power
generation systems and smart grid applications.

Acknowledgments: The authors would like to acknowledge the contribution of an Australian Government
Research Training Program Scholarship in supporting this research.
Author Contributions: Md Mubashwar Hasan conceived, designed the laboratory prototype and conducted the
experiments; A. Abu-Siada and Syed M. Islam contributed in analyzing data and results; S. M. Muyeen took part
while writing the paper.
Conflicts of Interest: The authors declare no conflict of interest.

Appendix A
Table A1. Generalized switching logic for a cascaded cell.

V out Turn on Switches

Vk Gk1 , Gk3
0 Gk1 , Gk4
−V k Gk2 , Gk4
Energies 2018, 11, 268 14 of 16

Table A2. Switching logic for different switching vector.

Switching Vector, Sa /Sb /Sc Switching Logic

4 Figure 5a
3 Figure 5b
2 Figure 5c
1 Figure 5d
0 Figure 5e

Table A3. System specifications of the implemented inverter.

Input DC Source Voltage in CHB Stage (V 1 , V 2 , V 3 ) 70 V Each

Input DC source voltage in PGS (V C ) 280 V
Switching frequency 50 Hz
Magnitude of line voltages 280 V (Peak)
Load power factor 0.82
Tested power of the prototype 523 Watt
Number of levels in the peak–peak line voltages 9

Table A4. Switching logic for generating 15 levels in the pole voltage.

Switching Vector, Sa Pole Voltage Switching Logic

14 VC 280 V Figure 5a
13 v + 3v + 9v 260 V V1 + V2 + V3
12 0 + 3v + 9v 240 V 0 + V2 + V3
11 −v + 3v + 9v 220 V −V 1 + V 2 + V 3
10 v + 0 + 9v 200 V V1 + 0 + V3
9 0 + 0 + 9v 180 V 0 + 0 + V3
8 −v + 0 + 9v 160 V −V 1 + 0 + V 3
7 v − 3v + 9v 140 V V1 − V2 + V3 BD-Switch-A ON
6 0 − 3v + 9v 120 V 0 − V2 + V3
5 −v − 3v + 9v 100 V −V 1 − V 2 + V 3
4 v + 3v + 0 80 V V1 + V2 + 0
3 0 + 3v + 0 60 V 0 + V2 + 0
2 −v + 3v + 0 40 V −V 1 + V 2 + 0
1 v+0+0 20 V V1 + 0 + 0
0 0 0 Figure 5e

Table A5. Switching logic in the cascaded stage and PG-stage for generating 9 levels in the pole voltage, V Ag .

Switching Vector Pole Voltage (V) Switching Logic

0 0
1 20
2 40
3 60
4 80
5 100
6 120
7 140
8 160
Figure 5a
S0 1 , S51 , S52
S0 2 , S11 , S31 , S41 , S52
S0 1 , S11 , S31 , S41 , S52
S0 1 , S11 , S21 , S31 , S52 BD-Switch-A Turn ON
S0 2 , S11 , S21 , S31 , S12 , S32 , S42
S0 2 , S11 , S21 , S31 , S12 , S22 , S32
S0 1 , S11 , S21 , S31 , S12 , S22 , S32
Figure 5e

References
1. Kawamura, W.; Hagiwara, M.; Akagi, H.; Tsukakoshi, M.; Nakamura, R.; Kodama, S. AC-Inductors Design
for a Modular Multilevel TSBC Converter, and Performance of a Low-Speed High-Torque Motor Drive Using
the Converter. IEEE Trans. Ind. Appl. 2017, 53, 4718–4729. [CrossRef]
Energies 2018, 11, 268 15 of 16

2. Hasan, M.M.; Mekhilef, S.; Ahmed, M.; Messikh, T. Three-phase multilevel inverter with high value of
resolution per switch employing a space vector modulation control scheme. Turk. J. Electr. Eng. Comput. Sci.
2016, 24, 1993–2009. [CrossRef]
3. Hasan, M.M.; Ahmed, M.; Mekhilef, S. Analyses and simulation of three-phase MLI with high value of
resolution per switch employing SVM control scheme. In Proceedings of the 2012 IEEE International
Conference on Power and Energy (PECon), Kota Kinabalu, Malaysia, 2–5 December 2012; pp. 7–12.
4. Hasan, M.M.; Abu-Siada, A. A high frequency linked modular cascaded multilevel inverter. In Proceedings
of the 2016 IEEE Industrial Electronics and Applications Conference (IEACon), Kota Kinabalu, Malaysia,
20–22 November 2016; pp. 47–51.
5. Hasan, M.M.; Abu-Siada, A. A novel three-phase cascaded multilevel inverter topology. In Proceedings
of the 2016 IEEE Industrial Electronics and Applications Conference (IEACon), Kota Kinabalu, Malaysia,
20–22 November 2016; pp. 31–35.
6. Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Wu, B.; Rodriguez, J.; Perez, M.A.;
Leon, J.I. Recent advances and industrial applications of multilevel converters. IEEE Trans. Ind. Electron.
2010, 57, 2553–2580. [CrossRef]
7. Franquelo, L.G.; Rodriguez, J.; Leon, J.I.; Kouro, S.; Portillo, R.; Prats, M.A. The age of multilevel converters
arrives. IEEE Ind. Electron. Mag. 2008, 2. [CrossRef]
8. Kawakami, N.; Ota, S.; Kon, H.; Konno, S.; Akagi, H.; Kobayashi, H.; Okada, N. Development of a 500-kW
modular multilevel cascade converter for battery energy storage systems. IEEE Trans. Ind. Appl. 2014, 50,
3902–3910. [CrossRef]
9. Hasan, M.M.; Abu-Siada, A.; Islam, M.R. Investigation of low switching frequency control of a three-phase
cascaded H-bridge multilevel inverter. In Proceedings of the 2016 International Conference on Electrical,
Computer & Telecommunication Engineering (ICECTE), Rajshahi, Bangladesh, 8–10 December 2016; pp. 1–5.
10. Inoue, S.; Akagi, H. A bidirectional isolated DC–DC converter as a core circuit of the next-generation
medium-voltage power conversion system. IEEE Trans. Power Electron. 2007, 22, 535–542. [CrossRef]
11. Dixon, J.; Pereda, J.; Castillo, C.; Bosch, S. Asymmetrical multilevel inverter for traction drives using only
one DC supply. IEEE Trans. Veh. Technol. 2010, 59, 3736–3743. [CrossRef]
12. Babaei, E.; Laali, S.; Bayat, Z. A single-phase cascaded multilevel inverter based on a new basic unit with
reduced number of power switches. IEEE Trans. Ind. Electron. 2015, 62, 922–929. [CrossRef]
13. Hasan, M.M.; Abu-Siada, A.; Dahidah, M.S.A. A Three-Phase Symmetrical DC-Link Multilevel Inverter with
Reduced Number of DC Sources. IEEE Trans. Power Electron. 2017. [CrossRef]
14. Kangarlu, M.F.; Babaei, E.; Laali, S. Symmetric multilevel inverter with reduced components based on
non-insulated dc voltage sources. IET Power Electron. 2012, 5, 571–581. [CrossRef]
15. Khosroshahi, M.T. Crisscross cascade multilevel inverter with reduction in number of components. IET Power
Electron. 2014, 7, 2914–2924. [CrossRef]
16. Hasan, M.M.; Abu-Siada, A.; Islam, S.M.; Muyeen, S.M. A three-phase half-bridge cascaded inverter with
reduced number of input DC supply. In Proceedings of the 2017 Australasian Universities Power Engineering
Conference (AUPEC), Melbourne, Australia, 19–22 November 2017.
17. Alishah, R.S.; Hosseini, S.H.; Babaei, E.; Sabahi, M. Optimization Assessment of a New Extended Multilevel
Converter Topology. IEEE Trans. Ind. Electron. 2017, 64, 4530–4538. [CrossRef]
18. Alishah, R.S.; Hosseini, S.H.; Babaei, E.; Sabahi, M. Optimal Design of New Cascaded Switch-Ladder
Multilevel Inverter Structure. IEEE Trans. Ind. Electron. 2017, 64, 2072–2080. [CrossRef]
19. Thamizharasan, S.; Baskaran, J.; Ramkumar, S.; Jeevananthan, S. Cross-switched multilevel inverter using
auxiliary reverse-connected voltage sources. IET Power Electron. 2014, 7, 1519–1526. [CrossRef]
20. Kangarlu, M.F.; Babaei, E. Cross-switched multilevel inverter: An innovative topology. IET Power Electron.
2013, 6, 642–651. [CrossRef]
21. Kangarlu, M.F.; Babaei, E.; Sabahi, M. Cascaded cross-switched multilevel inverter in symmetric and
asymmetric conditions. IET Power Electron. 2013, 6, 1041–1050. [CrossRef]
22. Gupta, K.K.; Jain, S. Multilevel inverter topology based on series connected switched sources. IET Power
Electron. 2013, 6, 164–174. [CrossRef]
23. Gupta, K.K.; Jain, S. A novel multilevel inverter based on switched DC sources. IEEE Trans. Ind. Electron.
2014, 61, 3269–3278. [CrossRef]
Energies 2018, 11, 268 16 of 16

24. Karasani, R.R.; Borghate, V.B.; Meshram, P.M.; Suryawanshi, H.M.; Sabyasachi, S. A Three-Phase Hybrid
Cascaded Modular Multilevel Inverter for Renewable Energy Environment. IEEE Trans. Power. Electron.
2017, 32, 1070–1087. [CrossRef]
25. Hasan, M.; Mekhilef, S.; Ahmed, M. Three-phase hybrid multilevel inverter with less power electronic
components using space vector modulation. IET Power Electron. 2014, 7, 1256–1265. [CrossRef]
26. Su, G.-J. Multilevel dc-link inverter. IEEE Trans. Ind. Appl. 2005, 41, 848–854. [CrossRef]
27. Ruiz-Caballero, D.A.; Ramos-Astudillo, R.M.; Mussa, S.A.; Heldwein, M.L. Symmetrical hybrid multilevel
DC–AC converters with reduced number of insulated DC supplies. IEEE Trans. Ind. Electron. 2010, 57,
2307–2314. [CrossRef]
28. Waltrich, G.; Barbi, I. Three-phase cascaded multilevel inverter using power cells with two inverter legs in
series. IEEE Trans. Ind. Electron. 2010, 57, 2605–2612. [CrossRef]
29. Elias, M.F.M.; Rahim, N.A.; Ping, H.W.; Uddin, M.N. Asymmetrical cascaded multilevel inverter based on
transistor-clamped H-bridge power cell. IEEE Trans. Ind. Appl. 2014, 50, 4281–4288. [CrossRef]
30. Colak, I.; Kabalci, E.; Bayindir, R. Review of multilevel voltage source inverter topologies and control
schemes. Energy Convers. Manag. 2011, 52, 1114–1128. [CrossRef]
31. Mortezaei, A.; Simões, M.G.; Bubshait, A.S.; Busarello, T.D.C.; Marafão, F.P.; Al-Durra, A. Multifunctional
control strategy for asymmetrical cascaded H-bridge inverter in microgrid applications. IEEE Trans. Ind. Appl.
2017, 53, 1538–1551. [CrossRef]
32. Prabaharan, N.; Palanisamy, K. A comprehensive review on reduced switch multilevel inverter topologies,
modulation techniques and applications. Renew. Sustain. Energy Rev. 2017, 76, 1248–1282. [CrossRef]
33. Tolbert, L.M.; Zheng, P.F.; Habetler, T.G. Multilevel PWM methods at low modulation indices. IEEE Trans.
Power. Electron. 2000, 15, 719–725. [CrossRef]
34. Islam, S.M.; Nayar, C.V.; Abu-Siada, A.; Hasan, M.M. Power Electronics for Renewable Energy Sources.
In Power Electronics Handbook, 4th ed.; Elsevier: Amsterdam, The Netherlands, 2018; pp. 783–827.
35. Khoucha, F.; Lagoun, S.M.; Marouani, K.; Kheloui, A.; El Hachemi Benbouzid, M. Hybrid cascaded H-bridge
multilevel-inverter induction-motor-drive direct torque control for automotive applications. IEEE Trans.
Ind. Electron. 2010, 57, 892–899. [CrossRef]
36. Beig, A.R.; Dekka, A. Experimental verification of multilevel inverter-based standalone power supply for
low-voltage and low-power applications. IET Power Electron. 2012, 5, 635–643. [CrossRef]
37. Lee, C.K.; Hui, S.Y.R.; Shu-Hung, C.H. A 31-level cascade inverter for power applications. IEEE Trans.
Ind. Electron. 2002, 49, 613–617. [CrossRef]
38. Liu, Y.; Luo, F.L. Trinary hybrid 81-level multilevel inverter for motor drive with zero common-mode voltage.
IEEE Trans. Ind. Electron. 2008, 55, 1014–1021. [CrossRef]
39. Hasan, M.M.; Abu-Siada, A.; Islam, M.R. Design and implementation of a novel three-phase cascaded
half-bridge inverter. IET Power Electron. 2016, 9, 1741–1752. [CrossRef]
40. Hasan, M.M.; Abu-Siada, A.; Islam, S.M.; Muyeen, S.M. A Novel Generalized Concept for Three-phase
Cascaded Multilevel Inverter Topologies. In Proceedings of the 2017 Ninth Annual IEEE Green Technologies
Conference (GreenTech), Denver, CO, USA, 29–31 March 2017; pp. 110–117.
41. IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems; IEEE Std. 1547-2003;
Institute of Electrical and Electronics Engineers: Piscataway, NJ, USA, 2003; pp. 1–28. [CrossRef]
42. Pereda, J.; Dixon, J. High-frequency link: A solution for using only one dc source in asymmetric cascaded
multilevel inverters. IEEE Trans. Ind. Electron. 2011, 58, 3884–3892. [CrossRef]

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access
article distributed under the terms and conditions of the Creative Commons Attribution
(CC BY) license (http://creativecommons.org/licenses/by/4.0/).