COMPUTER
CIRCUITRY 339
to provide a framework foractivitiesin computer
chess and to encourage advances in the field. There
are currently about 500 members. It published the
ICCA Journal, the leading publication in the field.
Information on the ICCA can be obtained by writing
to Don F. Beal, Secretary, ICCA, Department of
Computer Science, Queen Mary and Westfield
College, Mile EndRoad,London El 4NS, England
(http://www.dcs.qmw.ac.uk/-icca; email: icca
@dcs.qmw.ac.uk).
Bibliography
1950. Shannon, C. “Programming a Computer for Playing
Chess,” Philosophy Magazine, 41, 256-275.
1953. Turing, A. M. “Digital Computers Applied to Games,” in
Faster than Thought (ed. B. V. Bowden), 286-295. London:
Pitman.
1975. Newborn, M. Computer Chess. New York: Academic
Press.
1977. Frey,P. (ed.) Chess Skill in Man and Machine.New York:
Springer-Verlag.
1990. Levy, D. N. L., and Newborn, M. How Computers Play
Chess. New York: W. H. Freeman.
1991. Hsu, F.-H., Anantharaman, T., and Nowatzyk, A.
“A Grandmaster Chess Machine,” Scientific American, 263, 4
(October), 44-50.
1997. Newborn, M. Kasparov Versus Deep Blue: Computer
Chess Comes of Age. New York: Springer-Verlag.
Monty Newborn
COMPUTERCIRCUITRY
Although the development of digital computers can be
traced back to Charles Babbage, who conceived a
mechanical machine with toothed wheels to perform
arithmetic processes, electrical principles first found
application in digitalcomputers in the form of electro-
mechanical relays. The most prominent examples of
this type of computer are theBell Labs relay machines
( 4 . v . )and the Harvard Mark I (4.v.) and Mark 11. Even
while these machines were under construction in the
early and middle 1940s, it was recognized that an elec-
tronic computer would offer great advantages in terms
of computational speed. Electronic computers use
electronic circuits that interconnect electronic compo-
nents called gates. Gates implement basic operations
called Boolean or logic functions. This article starts
with a brief overview of Boolean algebra, the theory
that underlies such circuits.
The physical realization of electronic gates has under-
gone major changes since the 194Os, when they were
built with electric relays and then with vacuum tubes
as the first electronic components. The evolution in
electronic component technology has been motivated
primarily by the desire to have faster and smaller
computers that consume very little energy. Electronic
computers built since the late 1960s have used metal-
oxide semiconductor (MOS) transistors. Prior to that,
bipolar junction transistors (BJT) gates were used;
we discuss these transistor types later. Theearliest
semiconductor computer circuits consisted of gates
mounted on printed circuit boards connected by cop-
per wires. This technology has also undergone major
changes and today gates and interconnect wires are
integrated into a singlesilicon wafer in VLSI (Very
LargeScale Integration) technology (see MICROCOM-
PUTER CHIP).
This article is restricted to discussing the structure of
MOS and BJT gates. It describes a systematic method
to design two classes of electronic circuits: combina-
tional circuits, which implement arithmetic functions,
for example; and sequential circuits, which implement
memory. Finally,it describes the use of “program-
mable logic” devices, which facilitate the often tedious
process of designing computer circuits.
Boolean Algebra
Boolean algebra forms the theoretical cornerstone on
which modern digital computers are built. Boolean
algebra deals with functions and variables that take on
only two values, commonly denoted by either T and F
or 1 and 0. Using the axioms of Boolean algebra, it can
be shown that any Boolean function (a function over
Boolean variables), no matter how complex, can be
composed from at most three primitive operations:
and, or, and not. This set of logic operations is therefore
said to be functionally complete. In fact, there are two
primitive operations, widelyusedin the design of
computer circuitry, that are functionally complete in
themselves. These are nand (equivalent to a not fol-
lowing an a n d ) and nor (equivalent to a not following
an O Y ) . The implicationis that one needs only to design
circuits for a functionally complete set of Boolean
operations in order to have the basic building blocks
for a digital computer.
Theassociation that isusually made between an
abstract Boolean operation and circuitry that imple-
ments that operation is through voltage levels. Thatis,
digital circuitry is designed to respond to two voltage
levels, designated high and low (e.g. +5 volts and 0
volts). The conventional method uses the high voltage
(or V d d ) to represent a 1 and the low voltage (or Gnd
(Ground)) to represent a 0. Other associations of
Boolean values and circuit quantities are possible.
340 COMPUTER CIRCUITRY
nand and not
D- or nor
Figure 1. Symbols for logic gates.
MOS Logic Gates
Circuits that implement the most primitive Boolean
functions are called gates. The symbols that are used
to implement the commonly used gates are shown in
Fig. 1. A small circle used in conjunction with any gate
denotes negation of that gate’s function.
Variations of metal-oxide semiconductor (MOS) tech-
nologies are currently used to design computers.
In such technologies logic gates are buildusing
controlled switches. As shown in Fig. 2, such switches
consist of three terminals and can be either “n-type”
or “p-type” (‘n’for negative and ‘p’ for positive). In an
n-type switch, if G equals 1, terminal S is connected to
terminal D. If G equals 0, then terminal S is dis-
connected from terminal D. In a p-type switch, if G
equals 1, terminal S is disconnected from terminal D.
If G equals 0, then terminal S is connected to termi-
nal D. Physically, the “n-type” switch is an n-type field
effect transistor (nFET) and the “p-type” switch is a
p-type field effect transistor (pFET). For the purpose of
this discussion, we will not be concerned with the
physics of these devices (see INTEGRATED CIRCUITRY).
As shown in Fig. 3, such switches may be intercon-
nected to form a network having two distinct terminals,
X and Y.The connection pattern of Fig. 3a is a series
Yl
(a) Series
connection (b) Parallel connection
Figure 3. Series-parallelconnections.
Figure 2. Symbols for FETs.
connection, and the pattern ofFig. 3b is a parallel
connection. These elementary connection patterns can
be used to build larger networks, as shown in Fig. 3c.
We say that anetwork N of switches is activated if and
only if the two terminals X, Y of N are connected
through a set of switches. For example, in Fig. 3a, if
A = B = 1, both switches are closed and X is con-
nected to Y. Therefore the network of Fig.3a is
activated by the assignment A = B = 1. One can verify
that, if A = B = 0, the network of Fig. 3c is activated.
MOS logic gates are constructed by using networks of
switches. As shown in Fig. 4, there are two distinct
models of logic gates. The type-a gate uses two net-
works of switches-pullup and pulldown networks.
The pullup network consists only ofpFETs and the
pulldown network consists only of nFETs. These gates
are designed so that, for any assignment of values
to the input variables, only one of the two networks
is activated. If the pullup (pulldown) network is
activated, the output of the gate is set to the logic
valu‘e 1 (0).Fig.5ais an example of a type-a gate.
If A = B = 1, the pulldown network is activated and
the output is set to 0. If A = B = 0, then the pullup
network is activated and the outputis set to 1. One can
verify that the gate of Fig. 5a implements the nand
function.
A C
0 0
B
0
- D E
-
Y
(c) Series-Parallel graph
 COMPUTER CIRCUITRY 341

vdd vdd
4
t
Input Pullup
network variables
-1 output

I Pulldown
Output Input
variables
Pulldown
network
network

Figure 4. Structure of MOS gates.

For any assignment of values to the input of type-b
gates, the output is set to 0 if and only if the assign-
ments activate the pulldown network. One can verify
that Fig.5bis a type-b nand gate, and Fig.5cis a
type b nor gate.
Type-a gates in which the p d u p network consists only
of pFETs and the pulldown network consists only of
nFETs are known as CMOS (complementary metal-
oxidesemiconductor) gates. Circuitsconsisting
CMOS gates are known as CMOS circuits. Type-b
gates in which the pulldown network consists only of
nFETs are known as nMOS gates. Circuits consisting
of nMOS gates are known as nMOS circuits.
Historically, nMOS circuits preceded CMOS circuits
because nMOS circuits, unlike CMOS circuits, require
only one type of switch. Therefore, it was easier to
perfect the nMOS technology. However, technologi-
cal innovation has made CMOS an equallyfeasible
technology, and today almost all circuits are CMOS
circuits.
One of the major reasons fordeveloping the more
complicated CMOS technology can be understood by
re-examining the structure of the nMOS and CMOS
of
logic gates. Consider the nand gates of Fig.5a, b.
If A = B = 1, the pulldown network of Fig. 5a is acti-
vated but thepullup network of Fig. 5a isnot activated.
Therefore, in Fig. 5a, there is no conducting path from
V d d (both 'd's refer to the transistor drain terminal) to
Gnd. In fact, in the gate of Fig.5a, there is no
assignment of values to the input of the gate that will

I vdd

B
C 0
A

output
A
- ? output

-l

A - L
B I-
B---l
I - -
A B
L I
Gnd Gnd I
Gnd
(a) CMOS nand gate (b) nMOS nand gate (c) nMOS nor gate

Figure 5. Examples of MOS gates.

342 COMPUTER CIRCUITRY
result in a conducting path from V d d to Gnd. On the
other hand, inFig.Sb, when A = B = 1, there is a
conducting path from vd/dd to Gnd. Therefore, current
flows through the pullup resistor R, thereby dissipating
power, something that does not occur with CMOS cir-
cuits. This, in turn, hinders the integration of a large
number of nMOS gates on a single chip. This is one of
the many reasons for using CMOS circuits for denser
chips.
Other Logic Families
Although MOS, more specificallyCMOS,isnow the
dominant technology, a number of technologies have
been used for manufacturing computers. These tech-
nologies differ inthe type of switching devices used, as
well as how the devices are used in the design of logic
gates. The earliest computer circuits used vacuum
tubes, but since they are no longer in use, we will
not discuss the implementation of logic gates using
vacuum tubes.
The logic familiesthat we will discuss here use bipolar
junctiontransistors (BJTs)as the switching device.
LikeFETs,BJTs are also three-dimensional devices.
l u x
(c) Diode
I
(b) RTL nor gate
v+. I
( e ) TTL nand gate
Figure 6 . Implementation of some universal gates using BJT-basedlogic families.
We use the symbol of Fig. 6a to represent a BJT where
G is the base, E is the emitter, and Cis the collector. If
the voltage at C is “sufficiently higher” than the
voltage at E, terminal C is electrically connected to
terminal E (the switch is ON); otherwise, terminal Cis
disconnected from terminal E (the switch is OFF).
Logic gates using BJTs are similar (if not identical) to
type-b gates. In resistor-transistor logic (RTL),only
nor gates are available for designing circuits. It is for
this reason that RTL is said to be “nor logic.” A two-
input RTL nor gate is shown in Fig. 6b. It is similar to
the nMOS nor gate of Fig. 5c.
In diode-transistor Iogic (DTL), unlikeRTL, only nand
gates are availablefordesigning the circuits. These
nand gates use both diodes and transistors as active
devices. The symbol for a diode is shown in Fig. 6c.
A diode is a unidirectional two-terminal device. If the
voltage at X is higher than the voltage at Y, terminal X
is electrically connected to terminal otherwise, X is
disconnected from Y. A DTL nand gate is shown in
Fig. 6d. To understand the operation of this gate, note
that if A(B) has the logic level 0 (Le. voltage 0), diode
d l (d2) conducts. This implies that the voltage at P
is 0. V - is a negative voltage. Therefore, diodes d3,
dl c-
d2
V-
(d) DTL nand gate
v+ I
VS
5
S
R3 V -
(0ECL nand gate

d4 conduct and Q is at a negative voltage (by adjust-
ing the resistance value R3). This cuts T, the driver
transistor, OFF and the output F is at logic level 1.
If A = B = 1, diodes d l , d2 do not conduct. Diodes d3,
d4 conduct and Q is at a positive voltage (adjusted by
resistances R1, R3). The driver Tis ON and the output
F is pulled down to logic level 0.
In transistor-transistorlogic (TTL), the only gates
available are nand gates. A TTL nand gate is shown in
Fig. 6e. It is very similar to a DTL nand gate, but is
faster than either RTL or DTL.If either A or B is at
logic level 0, there is enough base-to-emitter voltage
difference at either T1 or T2 to turn one or both of
them ON. This brings down the voltage of P to a
sufficiently low value to cut T OFF. The output F is
therefore at logic level 1. When both A, B are 1, then
both T1 and T2 are cut OFF and P returns to a high
voltage. This turns TON and the output F is pulled to
logic level 0.
In DTL and TTL, there is a driver BJT and circuitry is
added to the base of this BJT to implement the nand
function. In emitter-coupled logic (ECL), the base of
the driver BJT is grounded and circuitry is added to
its emitter to implement the nor function. ECL circuits
are potentially faster than RTL, DTL, or TTL because,
unlike those logicfamilies, the driver BJTis never
driven into saturation and can therefore switch much
faster from one state to another. If either A or B in
Fig.6fis at logiclevel1, either T1 or T2 conducts.
Therefore there is current through R1. This brings Q
to logic level 0. The emitter of T4 is now at either 0 or
a small positive voltage(depending on the values of R1
and R3) and this cuts T4 OFF. S is therefore at logic
level 1. When both A, B are 0 , neither T1 nor T2 con-
ducts. Q is at logic level 1. The emitter ofT4is at a
negative voltage (close to 0). T4 conducts and S is set
to logic level 0. Note that Q and S are complements.
One advantage of using logic gates implemented using
BJTsis that they have faster switching speeds than
gatesusing MOS devices. However, the low power
dissipation of MOS gates, among other reasons, made
it easier to integrate MOS devices. Nevertheless, many
BJT devices are still in use for special-purpose circuits
or where higher driving capabilities are required.
r-l 1 n
Clock
Intervals 1 I3
I I
-b
I
Time
(4
Figure 7. Global clock.
COMPUTER CIRCUITRY 343
Classes of Computer Circuits
Depending onthe functions they implement, com-
puter circuits are divided into two classes: combina-
tional circuits and sequential circuits. Combinational
circuits are the simpler of the two classes and, along
with other circuit elements, are used in the design of
sequential circuits.
To understand the difference between combinational
and sequential circuits, refer to Fig. 7a. The time
interval is divided into subintervals 11, 12, . . . of equal
size. The intervals are marked by a periodiclogic
signal known as clock. The peviod of clock is equal to
the length of the interval. Every interval is divided into
two parts. During the first part, clock is 1, and during
the second part, clock is 0. We will refer to them as the
one and zero periods of the interval.
Every such circuit can be represented as shown in
Fig. 7b. Computation proceeds as follows. During the
one period, the values of the inputs change. During
zero period, the logic valuesat the outputschange and
settle down to their steady state value. This is known
as single-phase clocking.
Combinationalcircuits are circuits whose output,
during any time interval, depends only on the values
of the inputs during the current time interval and is
independent of the values of the inputs during the
preceding time intervals. The output of sequential
circuits, during any time interval, on the other hand,
depends on both the values of the inputs during the
current interval, as well as the values of the inputs
during the preceding time intervals. Having noted this
difference, we will next look at some combinational
and sequential circuits and try to understand some
simple design procedures for these classes of circuits.
Combinational Circuits
Boolean functions are functions overBooleanvari-
ables whose result can be only one of the two Boolean
values 0, 1. Combinational circuits implement Boolean
functions. An example of such a function is the odd
parity function P, of n variables. P, equals 1 if and
n -
only if an odd number of the n input variables equal 1.
'
I4
I
1 Clock
(b)
344 COMPUTER
CIRCUITRY

Table 1 get the following sum of products expression P3: P3 =

R1’~~T;x3+xl’X2’x3+f~’~~7i~3$X~’
X1 x2 x3 From such an expression, weget the gatelevel de-
..................................................... .........,....................
p3

scription shown in Fig. 8. Note that, for each term,we

0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Boolean functions are defined using truth tables. Such
a table definesthe value of the function for each combi-
nation of values of the input. The truth table of the
parity function of three variables is shown in Table 1.
Circuitswithmultiple outputs can alsobespecified
using truth tables.
Fig. 8 is a description of a circuit for the parity
function. Such a pictorial representation is a gate level
description of the circuit. A simple, but not necessarily
efficient, way to derive a gate level description from a
truth table is as follows. An input variable Xi or its
complement (Le. negation) X i is known as an input
literal. A conjunction of literals is known as a term.
Corresponding to each row of a truth table, we have a
term. For example, for row 1 of Table 1, we have the
term X I . X 2 . X3 (“.” denotes the “and” operation).
The term correspondingto a row of a truth table for a
Boolean function f is a one-term for f if and only if the
value of f for that input combination is 1. A zero-term
issimilarlydefined.FromTable 1, . x2 X3 is a
zero-term and X1 . x2 . X3 is a one-term for P3.
Let a l , . . . , at be the one-terms of a function f. Then,
+ + +
al a2 . . at (“+” denotes the or operation) is a
sum-of-products expressionfor f. FromTable 1 we
0 0
1 1
0 1
1 0
0 1
1 0
0 0
1 1
have an and gate and thereis one or gate that is driven
by all the and gates.
Programmable Circuits
The gate leveldescription is a description of the circuit
that isusedfor fabricating it. Prior to fabrication,
the physical location on a silicon wafer of the devices
(like FETs, resistors, etc.) has to be determined (place-
ment). Thisisfollowedby determining how the
devices are tobe interconnected (routing). For circuits
using a small number of devices, placement and rout-
ing canbedone manually.For larger circuits, the
entire process has to be automated. Many of the steps
of placement and routing can easily be automated if
the circuit topology is regular. Moreover, the integra-
tion process becomes simpler and more cost effective
if a variety of circuits can be physically implemented
by minor variations (or programming) of a “master
piece.” These factors have led to the evolution of a
number of design styles like programmable logic arrays
(PLAs), Weinburger arrays, gate matrix arrays, etc.
Such design styles are being used extensively. To gain
insight into these styles, we will have a brief look at
nMOS PLAs.
Let X I , X Z , X3 be input variables.The nor expres-
+ +
sion (X1 x2 X,) can be implemented logically as
shown in Fig. 9a. To implement this expression
physically, if there are n input variables, we have a
physical row of 2 n nFETs. For everyinput variable Xi,
there exist two nFETs, one driven by Xi and the other
driven by xi. An example is shown in Fig. 9b. For this
row of nFETs, some of the “links” are “broken.” This

x2
-

x3

T
Figure 8. Example of sum-of-product circuits.
 COMPUTER
CIRCUITRY 345

Links to be broken

I-l-l

Figure 9. Programmable NOR gate.

effectively removes some of the FETs from the circuit,
resulting in the desired gate shown in Fig. 9c. This is
the basic idea used in a PLA.
A PLA is shown in Fig. 10. It consists of two parts, an
AND-PLANE and an OR-PLANE. Each of these two
parts is a two-dimensional array of FETs. Every rowof
The inputs of the FETs in a row of the OR-PLANE are
driven by the output of the same nor gate of the AND-
PLANE. Given such an array of FETs, a set of sum of
products expressions is implemented by “selectively
disconnecting” some of the FETs from the circuit. For
example, to implement the followingBoolean func-
tions, the FETs to be disconnected are shown by x ” I‘

the AND-PLANEis arranged to form a potential nor in Fig. 10.

gate. AU FETs in a column of the AND-PLANE are
driven by the same input literal. Every column of the fl = XIX2 +m
OR-PLANE is arranged to form a potential nor gate. + XlX2

+
f2 = XlX2

OR
AND-PLANE

PLANE %

- - -

><

1._1-1?+-
: I

- -
x1 xi x2 x2 fi f2

Figure 10. Example of a programmable logic array.

346 COMPUTER
CIRCUITRY
Figure 11. Example of a state diagram.
Sequential Circuits
We will use a simple example to illustrate how sequen-
tial circuits are designed. Consider a circuit with one
input X and one output Y, defined as follows.Let ni be
the number of intervals, including and up to I;, during
which Xhad the value 1, At the end of Zj, Yis set to 1if
and only if n; is divisible by 3. We call such a circuit
MOD-3.
In order to compute thevalue of Y during the interval
Ij, MOD-3 must remember some characteristics of the
pattern of Os and 1s during the intervals 1 to Ii-1. It is
enough for the circuit to remember the value of
r;-1 = n;-1 mod 3, which is nothing but the remainder
left after dividing nj-1 by 3. Also note that if X,during
+
I;, equals 1, then r; = (rj-1 1) mod 3; and if r; equals
0, then Y is to be set to 1. Therefore, at the end of any
interval, we need to remember if the remainder was 0,
1, or 2.
ICLOCK
\ n
-.--
Figure 12. Structure of a flip-flop
Another way to express this behavior of MOD-3 is with
the help of the state diagram of Fig. l l b . Since we
need to know if rj is 0, 1, or 2 , we say that the circuit,
at the end of I;, is in state So if rj is 0 , SIif rj is 1, and
Sz if rj is 2. The arrow marked a / b , which starts at Si
and ends at S t , is to be interpreted as follows: if,at the
end of the interval Zj-1, rj-1 is i and during interval 4
the value of X is a, then, at the end of interval Z;, the
value of Y should be b and Y , should be t.
While designinga circuit from a state diagram, we have
to make sure that thecircuit "remembers" the state of
the system. In order to do that, the states are encoded
using two statevariables ao, a1 asfollows: SO =
(a0 = 0 , a1 = 0); SI= (a0 = 0 , a1 = 1); and& = (a0 = 1,
a1 = 0). The circuit now needs to remember thevalues of
the state variables. In other words, the circuit should
be capable of remembering two bits of information.
This leads to the question: how exactly does a circuit
remember two or more bits of information?
1 WR Q
 COMPUTER CIRCUITRY 347

Table 2 JK flip-flops,etc. (see SEQUENTIAL MACHINES).Fig. 12c

depicts a slightvariation of a D flip-flop that uses
si st
nFETs. In this case, in order to modify the values of Q
input
.......................................................... output
X a0 a1 Do Dl Y and Q, both CLOCK and WR have to be 1.
........................................................................................................
0 0 0
To continue our discussion of the design process, we
0 0 1
1 0 0 0 1 0 derive the state table from the state diagram. The state
0 0 1 0 1 0 table for our example is shown in Table 2. For each
1 0 1 1 0 0 edge in the state diagram, we have a row in the state
0 1 0 1 0 0 table. The pair (ao, a l ) defines the state Si of Fig. l l c ;
1 1 0 0 0 1
0 1
(DO,01)defines the state .ST; X defines the value a; and
dc 1 dc dc
1 1 1 dcdc dc Ydefines the value b. Note that DO,Dl will become the
new value of ao, a1 at the start of the next interval. In
dc-don’t care. order for that to happen, the circuit should be of the
form shown inFig. 13a, where C must satisfy the
conditions of the state table (Table 2). Since there is no
As theydidforlogic gates, circuit designers have
state S3, the case a0 = a1 = 1 cannot arise; hence
devised circuit elements called flip-flops. A flip-flop
there are “don’t care”values in these rows. The com-
can store (i.e. remember) one bit of information. The
plete circuit is shown in Fig. 13b. Note that Table 2 is
structure of a flip-flop isshown in Fig. 12aand we will
like a truth table for the combinational block C of
use the symbol of Fig. 12bto represent such a flip-flop.
Fig. 13a. Thisis a simple, but notnecessarily an
Here Q is the output of the flip-flop and Q is another
efficient way to implement sequential circuits.
output, such that the value of Q is always the com-
plement of the value of Q. D is the input to the flip-
flop. When CLOCK is 1 and D is 1, Q is set to 1. When
Conclusion
D is 0 and CLOCKis 1, then Q is set to 0. When This article has provided an overview of the building
CLOCK is 0 , the value of Q or Q cannot change. What blocks of computer circuits. Since the 1960s, these
we have just described is a D flip-flop. There are a circuits havebeenincreasingly compact and dense
number of other classes of flip-flops like SR flip-flop, semiconductor devices,initiallybuilt out of discrete

I ‘
(b)
Figure 13. Implementation of the state diagram of Fig. 11.
348 COMPUTER
CONFERENCINC
transistors, and then as integrated circuits that packed
many transistors, and hence, many gates, on a silicon
chip. They have evolved from small-scale integration
(SSI) to medium and large scale integration (MSI and
LSI) to the current very large scale integration (VLSI)
that can put several million transistors on a silicon
wafer about 1 cm in diameter. Such microcomputer
chips can hold a powerful processor and fast cache
memory (4.v.).
Sometimes computers are characterized by their gen-
eration: the first generation used vacuum tubes; the
second, discrete transistors, and the third, integrated
circuits. These circuits, introduced at the end of the
1960s, have evolved greatly, but more than 30 years
later, they still providethe fundamental material out of
which computers are built.
Bibliography
1980. Mead, C.,and Conway, L. Introduction to VLSI Systems.
Reading, MA: Addison-Wesley.
1993. Weste, N., and Eshraghian, K. Principles of CMOS VLSI
Design, 2nd Ed. Reading, MA: Addison-Wesley.
1998. Unger,S. H. The Essence of Logic Circuits, 2nd Ed. Upper
Saddle River, NJ: Prentice Hall.
1998. Wolf, W. Modern VLSI Design-Systems on Silicon,
2nd Ed. Upper Saddle River, NJ: Prentice Hall.
2000. Wakerly, J. F. Digital Design: Principles and Practice,
3rd Ed. Upper Saddle River, NJ: Prentice Hall.
Sreejit Chakravarty
tems (CS), Computer ConferencingSystems(CCS),
Computer-MediatedCommunication Systems (CMCS),
Computer-Supported Cooperative Work (CSCW), Co-
ordination Systems (CS), Electronic Meeting Systems
(EMS), Group Decision Support Systems (GDSS),
Groupware, Networking, Teamware, and Teleconfer-
encing. All these types of systems have one thing in
common: they are designed with the objective of using
the computer to aid inthe process of facilitating group
communications. The most appropriate inclusive term
is Computer-MediatedCommunications (CMC),a term
that includes all the others and claimeddifferences
among them.
With the emergence of theInternet (4.v.) and the
World Wide Web ( q . v . ) , there are currently hundreds
of group systemscommerciallyavailable: however,
very fewof them reflect the ability of the user or group
to tailor the process. The demonstration of that con-
cept is still largely limited to R&D systems.
Thediscussion or conference part of a CMC sys-
tem may be represented as a specific hypertext (4.v.)
structure. Most current systems can be described as
in Table1, which shows the relationships (links)among
the objects (nodes) that characterize the system.
Objects in CMC systems include both the elements of
discourse and the individuals or members. The individ-
uals are objects which are linked to content objects by
privileges associated with their human roles. There may
be significant additional functionality with respect to
the different roles and associated software powers a
person can have in a given conference. However, the
basic discourse structure is usually some combination
of temporal occurrence, comment/reply hierarchies,
and keyword association of comments.
An example that goesbeyond these basics is the
“Virtual Classroom” (Hiltz, 1994), where a number of
special communication structures exist inaddition to a
basic computer conferencing structure. For exam-
ple, an instructor can ask a discussion question but no
student can see the other discussion answers until he
or she has answered. What this example indicates is
Table 1. Common CMC object and relationship structures.
Comment Reply Person
Comment Laterlearlier In response to Author of/
than temporal editor of/
reader of
Additional/ Author of/
alternative editor of/
reader of
Person Member of
same
conference