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Detailed Routing Techniques:Historical
Prospective and Recent Trends

Abstract— We propose a detailed routing technique in IC
fabrication process. Routing is a physical design step which
provides precise path or set of wires for connecting all the nets in
the netlist and satisfying certain constraints and try to minimize
wire length,routing area and vias. As technology advances, IC
designer start facing problems in routing technique like finding
location of blocks,pins,netlist and timing budget for critical net.So
to solve this routing problem two stage solution was proposed in
[2].First is Global routing in which we divide the space into
sectors/tiles called global routing cell and decide sector to sector
path for each net. Maze and Line routing are two types of global
routing.Second is detailed routing which decides actual layout of
each net in the pre-assigned tiles. Channel routing ,Full chip
routing ,Switchbox and over the cell routing are types of detailed
routing .In this paper we mainly discussed about detailed routing
and its types specially Channel and Full chip routing in detail.
Index Terms—Routing, Detailed Routing, Channel Routing. Full
Chip Routing, Switch box Routing, Over the cell
Routing ,Hierarchical and Multi level Routing framework.
I. INTRODUCTION
n IC(Integrated Circuit) manufacturing process,after placement
Routing comes and it is a process which provides precise path
or set of wires for connecting all the nets in the netlist,pins
which are present on circuit blocks and pads at the chip
boundary by using metals and vias and by maintaining certain
manufacturing design rules which guarantee that design is
manufactured correctly. As Technology advances, IC
manufacturing process reaches at nanometer scale, in which
billions of transistors and millions of nets fabricated on single
chip.As a result designing of IC becomes more complicated and
provide many challenges for IC designer specially in case of
routing.
Problems faced by IC designer in routing technique are location
of blocks and pins,netlist,timing budget for critical net and
making design rules for manufacturing process such as wire or
via width and spacing of each layers,spacing between wires and
vias [1]-[2].The main objective of routing technique is to
minimize the number of vias and metal used in design and
optimize the total wire length,satisfy the timing
constraint,no LVS and DRC error and to complete the routing
inside the routing region.
Therefore two stage approach was proposed to solve this
routing problem,first is Global Routing and second is Detailed
Routing.In global routing we divide the routing space into
sectors/tiles called global routing cell and decide sector to
sector paths for each net and trying to optimize total wire length
and circuit timing.Types of global routing are maze routing and
line routing.Detailed Routing decides the actual layout of each
net in the pre-assigned routing tiles.Router decides actual
physical connections of nets by allocating wires on each metal
layers and by providing vias for switching between different
metal layers. From the given global routing we perform
detailed routing which gives the compaction of the circuit. Both
Global and Detailed routing are shown in figure 1.
Fig.1. (a) A given placement with fixed locations of blocks and
pins. (b) Global routing (c) Detailed routing
In this paper we mainly discussed two types of Detailed routing
techniques,first is Channel Routing which was used in earlier
technologies where only two or three metal layers are present
and most of the wires were routed in the free space between
logic blocks and second is Full Chip routing which is used in
present technologies were six to ten metal layers are present
and routing region is looks like channel free region.
In Channel Routing,all wires are connected inside the routing
channel and to apply routing channel routing region is divided
into many routing channels.The order in which routing regions
are placed is very important for channel routing process as its
significantly affects the routing process.The aim of channel
routing is to minimize the channel height through which
manufacturing cost reduces as It is related to die size.Generally
doglegs are used to connect wires so that wire channel height
decreases.Full chip routing is implemented by many routing
algorithms which follows two ways approach of global routing
and detailed routing.Hierarchical and multilevel frameworks
are used for large scale design and solve scalability problems.
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In hierarchical framework divide and conquer approach is used

which convert bigger routing problems into smaller routing
problems but disadvantage is that there is lack of interaction
between different routing sub regions and in routing decision
which cannot improved in later stages. So to overcome these
difficulties multilevel frameworks are introduced. Other
detailed routing methods like Switchbox routing is used to
minimize the channel length and to make sure that all nets are
routed and in over the cell routing, outside area of channel is
used to minimize the channel length.

Fig.3. Two ways of routing region decomposition: (a) The

II. DESCRIPTION
After global routing ,detailed rounting comes in which we
determines the exact tracks and vias for nets. In this section we
are going to discuss some popular types of detailed routing
techniques.
1. Channel Routing
2. Full-chip Routing
3. Switch box Routing
4. Over the cell Routing
A. Channel Routing
Channel routing is used in earlier technologies in which
maximum number of metal layers was only two or three shown
in figure 2 .In this interconnections are made within a
rectangular regions without any obstructions.To implement this
type of routing, routing region is divided into routing
channels.For example, out of many ways to divide routing
regions, one way is given below in which T-shaped routing
region shown in figure 3 is divided in two ways [9]-[10].The
routing region shown in figure 3a is divided into two horizontal
channel(channel 1) and one vertical channel (channel 2)
whereas that in figure 3b is divided into two horizontal
channels (channel 1 and 2) and vertical channel (channel 3).
routing region is decomposed into two channels. (b) The routing
region is decomposed into three regions
Order in which routing regions are placed affects the channel
routing technique significantly. In figure 2 if routing is of order
channel 2 followed by channel 1 than no conflicts occurs as we
can expend channel 1 if needed but if channel 1 is routed first
than all relatred wiring are fixed in channel 1 and channel 2
cannot expend if this channel can contains all the nets. Finding
feasible channel ordering to avoid conflict is not possible all the
time.So we use L-shaped channel routing to avoid this conflict.
In recent chip routing techniques ,each routing layer has a
specified routing direction, either horizontal or vertical like
three layer HVH routing model in which specified direction for
first, second and third layer are horizontal,vertical and
horizontal respectively.Other three layer model is VHV routing
model in which first,second and third layers are
vertical,horizontal and vertical.Both HVH and VHV routing
models are shown in figure 4.

Fig.4. Channel routing example: Channel routing configuration

with two routing tracks.

Some channel routing terminology which commonly used in

Channel routing are defined below and illustrated in figure 4.
Upper and the Lower boundary are the two channel boundaries
which is the input to the channel routing problem with pin
number which is a unique net ID present on the column of
channel boundaries. Tracks are horizontal rows available for
routing. Trunk are horizontal wire segment on the track.
Fig.2. Channel routing between IC blocks
Branches are vertical wire segment connecting trunks to
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terminal. Via is connection between branch and a trunk. If
routing path of a net contains more than one trunk than this path
is called dogleg. Channel height is the area of routing channel
shown by number of routing tracks . Local density is the total
number of nets crossing the column. Channel density is the
maximum local density inside the channel. The main reason for
doing channel routing is to minimize the channel height which
is directly proportionally to die size and thus manufacturing
cost.
Here two layer channel routing which is used connects three
nets wioth pin no 1,2 and 3 is shown 4.Connection of net 1 is
dogleg and channel height is 2. Simplified form of figure 4 is
figure 5 in which 8 columns are present in channel routing and
its local densities of 1,2,2,2,2,2,2,1 for these columns from left
to right and channel density is 2.
Fig.5. Simplified version for 4.
.Figure 6b shows routing channel with dogleg where channel
height is of 2 tracks whereas figure 6a shows channel routing
without doglegs where channel height is of 4 tracks. So doglegs
are used to connects wire segments for the purpose to minimize
the channel height .
Fig.6. Effect of dogleg channel routing: (a) Channel routing
solurion without dogleg requires four tracks for routing
completion (b) Channel routing solution with dogleg only requires
two tracks.
Constrained left edge channel routing algorithm-
It is a simplest channel routing algorithm. In this only 2
terminal nets are used,no vertical constraints required, HV two
layer model and doglegs are not allowed. This algorithm
produce minimum track solution in the absence of vertical
constraints. Dogleg channel routing algorithm is an extension
of constrained left edge channel routing algorithm. First this
algorithm decomposes multi- pin net into 2 pin net and than
assign trunk of each connection into a feasible track.
Dogleg channel routing algorithm contains 3 steps:
1. Decompose multi- pin net into 2 pin connection
2. Construct 2 constraints graphs, horizontal constraint
graph(HCG) and vertical constraint graph(VCG) to model
routing constraints [4] &[11].
3. Routing each net in the netlist without violating any
constraints modeled in both HCG AND VCG.
Step1: figure 8 shows 3 pin net (represented by interval [2,7]) is
divided into 2 pin connection 1a(interval [2,5]) and 1b(interval
[5,7]).
Fig.7. Channel routing instance
Fig.8. Multi-pin net decomposition
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Step2: HCG (V,E) is an undirected graph in which each node
Vi represents a connection Ni and edge(Vi,Vj) exists if
horizontal constraint exists bwtween connection Ni and Nj and
these cannot share same track else short circuit would occur.
Horizontal constraint in HCG between the nodes 2 & 4.Figure
9 shows HCG from the routing instance of figure 8.
Fig.9. Undirected horizontal constraint graph (HCG)
VCG(V,E) is a directed graph, each node Vi represents
connection Ni and directed edge exist if vertical constraints
exists between Ni & Nj. VCG constructed according to the pin
location in the upper and lower boundaries are 4 & 2, directed
edge (4,2). Figure 10 shows VCG for figure 8.
Fig.10. Directed vertical constraint graph(VCG).
Step3: In this step constrained left edge algorithm is used which
routes net to the routing tracks from top to bottom in both HCG
and VCG.In this algorithm first treats each connection as an
intervals and it sorted the interval according to the left end
x-coordinates. Than connection without vertical constraint are
routed one by one .For each connection ,track in the channel are
scanned from top to bottom and the first track is assigned to the
connection, than connects the left and right end of the trunks to
the corresponding pins of the channel boundaries via branches
and channel routing is completed.
B. Full Chip Routing
In modern technology ,chip contains 6 to 10 metal layers and
this number is expected to increase in upcoming time.As metal
layers increases, routing over the logic block is common,so
routing region becomes channel-less region in [12] &[15].
Full chip routing is a very difficult combinatorial problem. So
to deal with this problem, many algorithms used two stage
approach of global routing and detailed routing. As the design
size increases flat framework does not work.So to overcome
this drawback, hierarchical and multilevel frameworks were
introduced for large scale design.
Hierarchical routing framework uses the divide and conqueror
method in which big and difficult problems are transferred into
series of smaller sub problems and than move in
top-down,bottom-up or hybrid manner.
In top-down hierarchical global routing framework, algorithm
repeatedly breaks routing region into smaller regions called
super cells and nets at each hierarchical level are routed
concurrently. Figure 11 shows above method. This top-down
process performed until super cells are reduced to the global
routing sectors/tiles.
Fig.11. Top-down hierarchical routing approach for for a 3 pin
net.
In bottom-up hierarchical routing framework, region is divided
into array of super cells and routing is restricted in each super
cell at each hierarchical level and when routing at current level
is over, every four super cells are combined to form larger super
cells at higher level and this methods continues until the top
level contains all the chip. Figure 12 shows the bottom-up
hierarchical routing for 7 net. In this each solid rectangle
represents super cell and 2*2 dotted regions are combined
together.
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Fig.12. bottom-up hierarchical routing approach for a 7-pin net.
Limitation of top-down and bottom-up hierarchical methods is
decision taken at one routing level maybe suboptimal for
following levels. To overcome this limitation, hybrid
hierarchical methods are used which combines bounded maze-
routing algorithm with top-down and bottom-up hierarchical
methods into a unified routing framework.
Hierarchical routing approach solves the scalability problem
for larger designs but the major problem in this method is
lacking of interactions between different routing sub regions
and routing decision at one level is irreversible.
So to overcome this drawback, multilevel framework was
introduced to handle the large scale routing problems.
Multilevel framework were introduced for both global and
detailed routing.
Multi level routing framework made the routing resource as a
multi level routing graph. In this, routing region is divided into
array of rectangular sub regions and each of which contains
tens of routing tracks in each dimension shown in figure 13.
These sub regions are called global cells(GCs). Node in the
routing graph represents GC in the chip and edge represents the
boundary between 2 adjacent GCs. According to the physical
area, each edge is assigns a capacity in [14] &[15].
Fig.13. The multilevel routing graph
C. Switchbox Routing and Over the cell Routing
Switch box routing and over the cell routing are two other
types of detailed routing techniques. Switch box routing is
more difficult than channel routing because expanding switch
box to make more room for wires is not possible. Pins are
connected on all the 4 sides and fixing the dimensions of the
box. Main objective for switch box routing is to make sure the
all nets are routed and it is based on Greedy router,rip-up and
reroute routers and BEAVER algorithms.
In over -the -cell channel routing, problem is divided into three
steps.
1. Routing over the cells
2. Choosing net segments
3. Routing within the channel
In first step we the maximum independent set of the circle path
and solved in the quadratic time. In second step, we show the
optimal choice of net segment is NP-hard. Third step is based
on conventional channel router. The basic idea behind this
method is to use area outside the channel to reduce the channel
height. Router over the cell rows is possible due to limited use
of second and third metal layers.
III. CONCLUSION
We proposed detailed routing techniques to overcome the
problems faced by the IC designer in routing process such as
location of blocks, pin,nets timing budget for critical nets and
making design rules for manufacturing process such as wire or
via width ,spacing of each layers and spacing between wires
and vias. Some Detailed routing techniques are Channel routing,
Full chip routing, Switchbox routing and Over the cell routing
techniques. Channel routing is used to minimize the channel
density, total routing area, length of routing nets and number of
vias.
Switchbox routing is used to minimize the channel height and
ensuring that all nets are routed. In over the cell routing, outside
area of channel is used to reduce the channel height and its
possible by the limited use of second and third metal layers.
Full chip routing is used to overcome the scalability problem by
hierarchical and multilevel framework.
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