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  • CP211

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    Victor Hemz
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    This document provides details about an NPN power transistor chip process called CP211. It is an epitaxial planar process with a die size of 80 x 99 mils and thickness of 12.5 mils. The process yields 1450 gross dies per 4 inch wafer and is designed for transistor types including 2N3054A, CJD41C, and TIP41C.

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    This document provides details about an NPN power transistor chip process called CP211. It is an epitaxial planar process with a die size of 80 x 99 mils and thickness of 12.5 mils. The process yields 1450 gross dies per 4 inch wafer and is designed for transistor types including 2N3054A, CJD41C, and TIP41C.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    8 views2 pages

    CP211

    Uploaded by

    Victor Hemz
    This document provides details about an NPN power transistor chip process called CP211. It is an epitaxial planar process with a die size of 80 x 99 mils and thickness of 12.5 mils. The process yields 1450 gross dies per 4 inch wafer and is designed for transistor types including 2N3054A, CJD41C, and TIP41C.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    PROCESS CP211

    Power Transistor
    NPN - Amp/Switch Transistor Chip

    PROCESS DETAILS
    Process EPITAXIAL PLANAR
    Die Size 80 x 99 MILS
    Die Thickness 12.5 MILS
    Base Bonding Pad Area 12 x 32 MILS
    Emitter Bonding Pad Area 13 x 48 MILS
    Top Side Metalization Al - 30,000Å
    Back Side Metalization Cr/Ni/Ag - 16,000Å

    GEOMETRY
    GROSS DIE PER 4 INCH WAFER
    1,450

    PRINCIPAL DEVICE TYPES


    2N3054A
    CJD41C
    TIP41C

    R5 (22-March 2010)
    w w w. c e n t r a l s e m i . c o m
    PROCESS CP211
    Typical Electrical Characteristics

    R5 (22-March 2010)
    w w w. c e n t r a l s e m i . c o m

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