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General Software Model

of Intel Architecture
and
Processor Organization

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3.1 General Software Model of Intel Architecture

 8086 through Core-i series considered program visible.

– registers are used during programming and are specified by the instructions

 Other registers considered to be program invisible.

– not addressable directly during applications programming

 80286 and above contain program-invisible registers to control and operate protected
memory and other features of the microprocessor.

 80386 through Core-i series microprocessors contain full 32-bit internal architectures.

 8086 through the 80286 are fully upward-compatible to the 80386 through Core-i series.

 Figure 1 illustrates the software model of the 8086 through Core-i series microprocessors.
It is including the 64-bit extensions.

Figure 1 Software model of the 8086-Core-i series microprocessors

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 The programming model of the 8086 - 80286 contains 8- and 16-bit registers.
 The programming model of the 80386 and above contains 8-, 16-, and 32-bit extended
registers as well as two additional 16-bit segment registers: FS and GS.

 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL.

16-bit registers are AX, BX, CX, DX, SP, BP, DI, and SI.

32-bit extended registers are EAX, EBX, ECX, EDX, ESP, EBP, EDI, and ESI.

64-bit registers in a Pentium 4 with 64-bit extensions are RAX, RBX, RCX, RDX, RSP,

RBP, RDI, RSI, and R8 - R15.

 R8 - R15 (additional general-purpose registers) found in the Pentium 4 and Core-i series if
64-bit extensions are enabled.

– data are addressed as 64-, 32-, 16-, or 8-bit sizes

Register size Override Bits Accessed Examples
8 bits B (low-order byte) 7-0 MOV R9B, R10B
16 bits W (low-order word) 15 - 0 MOV R10W, AX
32 bits D (low-order double word) 31 - 0 MOV R14D, R15D
64 bits - 63 - 0 MOV R13, R12

 Most applications will not use these registers until 64-bit processors are common.
– the 8-bit portion is the rightmost 8-bit only
– bits 8 to 15 are not directly addressable as a byte
 The segment registers are CS, DS, ES, SS, FS, and GS.

 The FS and GS segments are supplemental segment registers available in the 80386–Core-
i series microprocessors to allow two additional memory segments for access by programs.
Windows uses these segments for internal operations, but no definition of their usage is
available.

 The length of CS and DS are limited to 64K bytes in the 8088–80286, and 4G bytes in the
80386 and above when these microprocessors operate in the protected mode.

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 Instruction Pointer (IP/EIP/RIP) : a 64-bit register (RIP)

a 32-bit register (EIP)

a 16-bit register (IP)

– In the 64-bit mode, RIP contains a 40-bit address at present to address a 1T flat
address space.

 Flag register (FLAGS, EFLAGS, or RFLAGS).

 Eight 80-bit floating-point data registers:

– ST (0), ST (1), . . . ST (7).

– Arranged in a stack.
– Used for all floating-point arithmetic.
 Eight 64-bit MMX registers:

– Used with MMX (Multimedia Extensions) instructions.

 Eight 128-bit XMM registers for Single-Instruction Multiple-Data (SIMD) operations.

– Used with SSE (Streaming SIMD Extensions) instructions.

 All instructions (code) are accessed by the combination of CS (segment address) plus IP or
EIP (offset address).

 Data are normally referenced through a combination of the DS (data segment) and either an
offset address or the contents of a register that contains the offset address. The 8086–Core-i
series use BX, DI, and SI as default offset registers for data if 16-bit registers are selected.

 The 80386 and above can use the 32-bit registers EAX, EBX, ECX, EDX, EDI, and ESI as
default offset registers for data.

 RFLAGS indicate the condition of the microprocessor and control its operation.
 Figure 2 shows the flag registers of all versions of the microprocessor.
 Flags are upward-compatible from the 8086/8088 through Core-i series.
 The rightmost five and the overflow flag are changed by most arithmetic and logic
operations.
 The flags never change for any data transfer or program control operation.
 Some of the flags are also used to control features found in the microprocessor.

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Figure 2 The EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor
family.

 IOPL (Input\Output Privilege Level) used in protected mode operation to select the
privilege level for I/O devices.

 NT (Nested Task) flag indicates the current task is nested within another task in protected
mode operation.

 RF (Resume Flag) used with debugging to control resumption of execution after the next
instruction.

 VM (Virtual Mode) flag bit selects virtual mode operation in a protected mode system.

 AC (Alignment Check) flag bit activates if a word or double word is addressed on a non-
word or non-double word boundary.

 VIF (Virtual Interrupt Flag) is a copy of the interrupt flag bit available to the Pentium 4.

 VIP (Virtual Interrupt Pending) flag provides information about a virtual mode interrupt
for Pentium.

• used in multitasking environments to provide virtual interrupt flags.

 ID (Identification) flag indicates that the Pentium microprocessors support the CPUID
instruction.

• CPUID instruction provides the system with information about the Pentium
microprocessor.

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3.2 Modes of Operation

• Intel processor runs in five modes of operation:

1. Real-mode

Native MS-DOS

1 MB space (20-bit address)

2. Protected mode

Native mode (Windows, Linux).

4 GB addressable RAM (32-bit address).

- (00000000 to FFFFFFFFH).

Each program assigned a memory partition which is protected from other programs.

Designed for multitasking.

3. Virtual-8086 mode

It is used to run 8086 compatible programs concurrently with other protected mode
programs (hybrid of protected).

1 MB space (20-bit address).

4. IA 32e – Extended Memory model for 64-bits

Compatibility mode – execute 32 bit code in 64-bit mode without recompilation. No

access to 64-bit address space.

64-bit mode – 64-bit OS accessing 64-bit address space and 64-bit registers.

5. System Management Mode

Power management, system security, and diagnostics.

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3.3 Instruction Cycle( Fetch-Decode-Execute Cycle)

 The fetch-decode-execute cycle represents the steps that a processor follows to run a
program. Instruction cycle includes the following sub-cycles to execute one instruction:
1. Fetch (F): transfers instruction from main memory to the current instruction register.
2. Decode (D): determines the opcode and fetches any data necessary to carry out the
instruction.
3. Execute (E): performs the operation indicated by the instruction.

Figure 3 Instruction Cycle

Execution of instruction without pipeline

Time T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

F1 D1 E1 F2 D2 E2 F3 D3 E3 F4 D4 E4
Instruction1 Instruction2 Instruction3 Instruction4

Execution of instruction using pipeline

Time T1 T2 T3 T4 T5 T6
Instruction I1 F1 D1 E1
I2 F2 D2 E2
I3 F3 D3 E3
I4 F4 D4 E4

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 Four registers are essential to instruction execution:

1. Program Counter (PC): Contains the address of an instruction to be fetched.
2. Current Instruction Register (CIR): Contains the instruction most recently fetched.
3. Memory Address Register (MAR): Contains the address of a location in memory.
4. Memory Data Register (MDR): Contains a word of data to be written to memory or
the word most recently read.
 In microprocessor, an instruction can be divided into two parts:
– Operation code (opcode)
– Operand
 An instruction contains an opcode and one or more operand.
 Mostly instructions contain only one or two operand.

Instruction Format

Opcode Operand

Instruction Data or Address stores in Register or Memory

(a)

4 Bits 6 Bits 6 Bits

Opcode Operand 1 Operand 2
16 Bits
Instruction Data or Address stores in Register or Memory

(b)

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 Notice that a large part of this cycle is spent copying data from one location to
another. When a program is initially loaded, the address of the first instruction must be
placed in the PC. The steps in this cycle are listed below. Note that Steps 1 and 2 make
up the fetch phase, Step 3 makes up the decode phase, and Step 4 is the execute phase.

1. Copy the contents of the PC to the MAR: MAR PC.

2. Go to main memory and fetch the instruction found at the address in the MAR,
placing this instruction in the CIR; increment PC by 1 (PC now points to the next
instruction in the program):
CIR 





M[MAR]
PC 

PC+1
3. Copy the rightmost bits of the CIR which represent the operand(s) into the MAR;
decode the leftmost bits which represent the opcode to determine the opcode,
MAR CIR, and decode CIR.
4. If necessary, use the address in the MAR to go to memory to get data, placing the
data in the MDR, and then execute the instruction: MDR M[MAR] and execute
the actual instruction.

Figure 4 Fetch-Decode-Execute Cycle

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Step 1 Step 2

Step 3 Step 4

Step 5 Step 6

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Step 7 Step 8

Step 9 Step 10

Step 11 Step 12

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Step 13 Step 14

Step 15 Step 16

Step 17 Step 18
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Step 19 Step 20

Step 21 Step 22

Step 23 Step 24
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Step 25 Step 26

Step 27

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3.4 Types of Operations

 The number of different opcodes varies widely from machine to machine. However, the
same general types of operations are found on all machines. A useful and typical
categorization is the following:
1. Data transfer
 Move, Store, Exchange, Push, Pop, Clear, Set.
2. Arithmetic
 Add, Subtract, Multiply, Divide, Absolute, Negate, Increment, Decrement.
3. Logical
 AND, OR, NOT, XOR, Test, Compare, Shift, Rotate.
4. Conversion
 Translate, Convert (Convert the contents of a word from one form to another).
5. I/O
 Input (read), Output (write).
6. System control
7. Transfer of control
 Jump (unconditional & conditional), Jump to Subroutine (Call), Return, Halt (Stop
program execution), Wait, No operation, Skip (Increment PC to skip next
instruction).

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