CoE 236 DIGITAL ELECTRONICS

Dr. Mohannad H. Al-Ali

Department of Computer Engineering

University of Basrah

Spring 2020

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 Chapter Five

CMOS Logic Circuits

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Chapter Objectives

Study the operation of complementary CMOS logic.

Study the operation of clocked CMOS logic.

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 5.1 Introduction

5.1 Introduction

Combinational logic circuit: The output is related to the current input signals.
- Sequential logic circuit: The output is a function of the current input signals and the past
input values.
Important metrics when implementing a logic function:
 Required area,
 Switching speed,
 Power and energy dissipation,
 Immunity to noise and reliability,

Figure: (a) Combinational logic circuit. (b) Sequential logic circuit.

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 5.2 Complementary CMOS

5.2 Complementary CMOS

Complementary CMOS has a pull-up network (PUN) and pull-down network (PDN).
- PUN provides a connection between VDD and the output to yield logic 1. PUN is con-
structed using PMOS.
- PDN provides a connection between the ground and the output to yield logic 0. PDN is
constructed using NMOS.
- Either PUN or PDN is conducting in the steady state. PUN is the dual or the complement
of PDN.

PUN

PDN

Figure: Complementary CMOS logic as a combination of a PUN and a PDN.

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 5.2 Complementary CMOS

5.2 Complementary CMOS (cont.)

NMOS in series corresponds to AND function. Y = A:B
- NMOS in parallel corresponds to OR function. Y = A + B
PMOS in series corresponds to NOR function. Y = A + B
- PMOS in parallel corresponds to NAND function. Y = A:B
If PDN is implemented using combinations of series and parallel NMOS, PUN is imple-
mented by replacing the series paths in the PDN with parallel paths and the parallel paths
with series paths.
Complementary CMOS produces inverting output: NAND, NOR, XNOR.
- The realization of a non-inverting function requires an additional inverter stage.
An N -input complementary CMOS logic gate requires 2N transistors.

(a) (b) (c) (d)

Figure: NMOS: (a) in series yields AND, and (b) in parallel yields OR. PMOS: (C) in series yields NOR, and (d) in parallel yields
NAND.

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 5.2 Complementary CMOS

Example 5.1
Using complementary CMOS to design
(a) a 2-input OR gate.
(b) a 3-input NAND gate.

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 5.2 Complementary CMOS

Example 5.2

Using complementary CMOS to design the logic function Y = AB + C (D + E ).

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 5.2 Complementary CMOS

5.2.1 Transistor Sizing

Consider transistor sizing based on the switching speed (or propagation delay).
- Switching time in PUN is the same as switching time in PDN.
CMOS inverter, equal switching times happen when Kn = KP .
(W =L)p n
=
(W =L)n p
 2: (1)

- Assume Lp = Ln , then Wn = W and Wp = 2W , where W is a standard (minimum)

width.
Worst case analysis:
- PDN: Pick the input pattern that add as much as NMOS in series. Wn = #W .
- PUN: Pick the input pattern that add as much as PMOS in series. Wp = #2W .

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 5.2 Complementary CMOS

Example 5.3
Determine the transistor sizes of the logic gates in Example 5.1. Symmetrical switching times are
desired and the switching times should correspond to the basic CMOS inverter.

(c)

Figure: (a) CMOS inverter. (b) 2-input NOR. (C) 3-input NAND. 10 / 14
 5.2 Complementary CMOS

Exercise 5.1
(a) Determine the transistor sizes of the implemented logic gates in Example 5.2.
(b) Determine the transistor sizes of an N-input NAND gate. Comment on Fan-in.
(c) Determine the transistor sizes of an N-input NOR gate. Comment on Fan-in.
Assume Symmetrical switching times are desired and the switching times should correspond to
the basic CMOS inverter.

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 5.3 Clocked CMOS Logic

5.3 Clocked CMOS Logic

Clocked CMOS logic reduces the number of transistors required to implement a logic func-
tion.
- It replaces PUN by one PMOS and one NMOS.
- It requires N + 2 transistors to implement an N input logic function.
- It saves silicon area and reduces fan-in capacitance.
When CLK = logic 0, PMOS MP 1 is on and NMOS MN 1 is o. Output node is precharged
to VDD by PMOS.
- When CLK = logic 1, PMOS MP 1 is o and NMOS MN 1 is on. Output nodes is condi-
tionally discharged to GND depending on the input values and PDN.

Figure: Basic concept of a dynamic gate. 12 / 14

Example 5.3
Use clocked CMOS logic to implement (i) 2-input AND function, (ii) 2-input OR function.
AND function
 If CLK = logic 0, MN 1 is o and MP 1 is on, vO 1 = VDD , vO goes low. The gate of MP 2 is precharged.
 If CLK = logic 1, MN 1 is on and MP 1 is o,
- If A = logic 0 or B = logic 0, vo 1 = VDD and vO remains low,
- If A = logic 1 and B = logic 1, v01 discharges and vO goes high,
OR function
 If CLK = logic 0, MN 1 is o and MP 1 is on, vO 1 = VDD , vO goes low. The gate of MP 2 is precharged.
 If CLK = logic 1, MN 1 is on and MP 1 is o,
- If A = logic 0 and B = logic 0, vo 1 = VDD and vO remains low,
- If A = logic 1 or B = logic 1, v01 discharges and vO goes high,

Figure: Clocked CMOS logic: (a) 2-input AND, and (b) 2-input OR. 13 / 14
Exercise 5.2
The clocked circuit shown below is called domino logic in which each clocked dynamic logic
circuit is followed by an inverter. Analyze the operation of the depicted circuit and specify the
logic functions f1 and f2 .

Figure: A domino logic circuit. 14 / 14