XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00 & XC17S00XL Family

Description The Spartan Family consists of 5 volt and

3.3 volt devices. For each 5 volt device
The Spartan Family of Serial Configuration (XC17S00), there is a 3.3 volt counterpart
PROMs provide easy-to-use, cost-effective (XC17S00XL). All devices are one-time
configuration memory for Xilinx Field programmable (OTP) and are organized as
Programmable Gate Arrays. follows:
These devices use a simple serial-access procedure XC17S05 65,536 x 1 bit
to configure one or more LCA devices. The user
can select the polarity of the reset function by XC17S05XL 131,072 x 1 bit
programming a special bit. These devices are fully
XC17S10/XL 131,072 x 1 bit
compatible and can be cascaded with other
members of the XC17S00 family of devices. XC17S20/XL 262,144 x 1 bit
DATA 1 8 Vcc XC17S30/XL 262,144 x 1 bit
CLK 2 7 Vpp
XC17S40/XL 524,288 x 1 bit
RESET/OE 3 6 CEO

4 5
XC17S50XL 1, 048,576 x 1 bit
CE GND

XC17S100XL 1, 048,576 x 1 bit

8 Pin Dip/VOIC Assignments
XC17S150XL 1, 048,576 x 1 bit
All devices are available in the 8 pin DIP and 8
pin VOIC package except the XC17S40,
XC17S40XL, XC17S50XL, XC17S100XL, and
XC17S150XL which comes in the 8 pin DIP
and 20 pin SOIC package (See below).

DATA 1 20 Vcc
nc 2 19 nc
CLK 3 18 Vpp
nc 4 17 nc
nc 5 16 nc
nc 6 15 nc
nc 7 14 nc
RESET/OE 8 13 CEO
nc 9 12 nc
CE 10 11 GND

20-Pin SOIC Assignment (17S40/XL, 50XL,

100XL, 150XL Only)

03/00 Rev. 2.1 1

This datasheet has been downloaded from http://www.digchip.com at this page

 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00 & XC17S00XL Family

Programming Overview Table I Clock To ID (decimal)

NIDCLK NRSTCLK
All the Spartan SPROMs are internally
organized in rows, each row containing eight S05 2,056 2,048
(8) words. The S05 device has 32 bit words S05XL 4,600 4,104
and the S05XL, S10/XL, S20/XL, S30/XL and S10/XL 4,600 4,104
S40/XL has 64 bit words. Additional non-data S20/XL 4,600 4,104
rows are used to read the
S30/XL 4,600 4,104
Manufacturer’s/Device ID and set the Reset
S40/XL 19,791 16,384
Polarity and cannot be used to store
configuration data. The device programmer S50XL 19,791 16,384
should prompt the user for the desired Reset S100XL 19,791 16,384
Polarity. S150XL 19,791 16,384
Figure 1 shows the flow of how the SPROMs Then bring High and Low* . The first bit
are programmed. See Figure 2 for the of the identification word is present when
programming cycle overview and Figure 4 for goes Low and does not require a clock. Apply
the details of the programming cycle.
15 additional clock signals to the CLK pin to
Enter Programming Mode read the complete device ID.

The Manufacturer’s/Device ID
The programming mode is entered by holding
and High with VPP at VPP1 for two rising Consisting of 2 bytes of data. The first byte
clock edges, then lowering VPP to VPPNOM for contains the JEDEC assigned Manufacturer’s
one more rising clock edge (See Figure 3).
Once in the programming mode, the following ID code for Xilinx (C9). The first four bits of the
functions are available. second byte define the density of the PROM
(See Table ll), while the last four bits of the
Read Manufacturer’s/Device ID second byte contain specific programming
algorithm code (See Table lll). The data is read
All of the SPROMs contain a Manufacturer’s
out MSB first.
and Device identification code. Prior to
attempting to program or verify the device, the Table ll Density Codes
device programmer should read this code and
Device Density Codes
verify that it is the correct code for the device
selected by the user. If not, display message S05 F (1111)
“Manufacturer or Device ID Error.” S10/S10XL/S05XL 8 (1000)
S20/S20XL/S30/S30XL A (1010)
To read the Manufacturer’s/Device
identification code, first enter the programming S40/S40XL 9 (1001)
mode. While holding High and Low, S50XL 9 (1101)
apply NIDCLK (See Table 1) clock signals to the S100XL 9 (1101)
clock pin to access the ID row. S150XL 9 (1101)

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00 & XC17S00XL Family

Table lll Programming Algo Codes Increment the Address (Word) Counter
Device Algorithm Code
After successfully programming a data word, the
S10XL/S20XL/S40XL 9 (1001) address counter must be incremented. This is
S05/S10/S20/S40 8 (1000) done on the rising edge of the clock while is
S30XL/S05XL 7 (0111) High and is Low.*
S30 6 (0110)
S50XL 6 (0110) Set RESET Polarity
S100XL 7 (0111)
The polarity of the Reset/ pin may be made
S150XL 9 (1001) active Low by writing zeros into a dedicated
row.(See Figure 5).
Loading and Programming a Data Word
The data word is shifted into the SPROM, one bit Reset/ is located outside of the user data
at a time, on the rising edge of the clock, while array. Enter the programming mode, then
and are High. The data word counter is lower Reset/ , hold the Data pin Low, strobe
temporarily held in internal latches until the the clock NRSTCLK times (See Table l), raise the
address is advanced to the next address, and is
Reset/ pin, load the data latches with all
programmed into the memory as an entire word
upon strobing the device with VPP at VPP1 for zeros (see Load a Data Word above), and
100µs. strobe VPP at VPP1 for 5 ms.

The contents of the data word must now be

The reset polarity has to be verified (sensed) at
verified at VPP2. The data word is read while
VPP2 while in programming mode. To sense the
lowering and capturing the data while clocking
polarity bit, after strobing VPP for 5ms, set
the device 31 or 63 times (See Programming
low and sense the pin. If is high, reset
Overview). The first bit of the word (LSB) is
is active low (successfully programmed). If
present when goes low. After all bits were
is low, reset is active high (failed to program).
read, bring high and compare the data to the
original file data. If the data does not compare, Writing ones or not writing anything maintains
stroke VPP at VPP1 for 500µs. (Note, the original RESET active High.
data is still contained in internal latches and does
Note:
not have to be loaded into the device again.)
Read the data word again (as described above) The Reset Polarity is actually only the MSB of
and compare it to the original data. If it still does the data word.
not compare, pulse VPP at VPP1 for another 500µs.
Now read the data word again. If it still does not
compare, power the device down and issue * Be careful not to have and Low at the
message: “Device Failed to Program”. See Figure same time, as this causes the device to exit
4. If the word compares, increment the word programming mode.
counter as described below.

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00 & XC17S00XL Family

Sensing RESET Polarity If the data fails to verify, display message

“Failed Margin Verify”. If the data verifies,
To sense or read the polarity of the Reset/ display message “Device Passed”.
pin, enter the programming mode, then lower
Reset/ , hold the Data pin High, then strobe
the clock NRSTCLK times (See Table l). Set
Reset/ High, set Low and sense the
pin. If is High, Reset is active Low. If is
Low, Reset is active High. The reset polarity bit
is defaulted (unprogrammed) to active high.
When the reset bit is programmed, the “reset”
polarity is active low.

Exit Programming Mode

To exit the programming mode, remove power
from the device, per Figure 6.

Stand Alone Verify Of Data Bits

(Normal Mode)
The verify operation should be performed after
programming. Power up the device and read
the data bits out serially in normal readout
mode (see Figure 7). A margin voltage
(difference between VPP and VCC) is applied to
the device to ensure charge retention on each
programmed bit. Set VCC to VCCVFY and VPP to
VPPVFY. When in normal mode, the Reset/
signal should be driven active high if the reset
polarity bit was unprogrammed (logic “1”). It
should be driven active low if the reset polarity
bit was programmed (logic “0”).
At the end of the verify operation the
programmer must confirm that the pin has
gone Low one clock after the last bit is read
out.

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

Programming Mode Pin Assignments

DIP8 VOIC8 SOIC20 Name I/O Description
Pin Pin Pin
1 1 1 Data I/O The rising edge of the clock shifts a data word in or out of
the SPROM one bit at a time.
2 2 3 CLK I Clock input. Used to increment the internal address/word
counter for reading and programming.
3 3 8 RESET/ I The rising edge of CLK shifts a data word into the PROM
when and are High; it shifts a data word out of the
PROM when is Low and is High. The
address/word counter is incremented on the rising edge
of CLK while is held High and is held Low. Note:
Any modified polarity of the RESET/ pin is ignored in
the programming mode.
4 4 10 I The rising edge of CLK shifts a data word into the PROM
when and are High; it shifts a data word out of the
PROM when is Low and is High. The
address/word counter is incremented on the rising edge
of CLK while is held High and is held Low.
5 5 11 GND Ground pin
6 6 13 O The polarity of the RESET/ pin can be read by sensing
the pin. Note: The polarity of the RESET/ pin is
ignored while in the programming mode. In final
verification, this pin must be monitored to go Low one
clock cycle after the last data bit has been read.
7 7 18 VPP Programming Voltage Supply. Programming mode is
entered by holding and High and VPP at VPP1 for
two rising clock edges and then lowering VPP to VPPNOM
for one more rising clock edge. A word is programmed by
strobing the device with VPP for the duration TPGM. VPP
must be held at VCC for normal operation.
8 8 20 VCC VCC power supply input.

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

DC Programming Specifications

Symbol Description Min Recommended Max Units

VCCP* Supply voltage during programming 5.0 V

VIL Low-level input voltage 0.0 0.0 0.5 V

VIH High-level input voltage 2.4 VCC VCC V

VOL Low-level output voltage 0.4 V

VOH High-level output voltage 2.5 V

VPP1** Programming voltage 12.0 12.25 12.5 V

VPP2*** Margin verify voltage during programming 5.4 V

IPPP Supply current on programming pin 60 mA

VCCNOM/VPPNOM Nominal Voltage 5.0 V

VCCVFY (S00 Only) Supply voltage during stand alone margin 5.0 V
verify (5 volt devices)
VCCVFY (S00XL Only) Supply voltage during stand alone margin 3.3 V
verify (3.3 volt devices)
VPPVFY (S00 Only) Margin voltage during stand alone margin 5.4 V
verify (5 volt devices)
VPPVFY (S00XL Only) Margin voltage during stand alone margin 3.7 V
verify (3.3 volt devices)

* Noise and voltage deviation allowed: 5.0V ± 50 mV.

** No overshoot is permitted on signal. VPP must not be allowed to exceed VPP1 max.
*** Noise and voltage deviation allowed: 5.4V ± 250 mV.

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

AC Programming Specifications

Symbol Description Min Rec Max Units

1 TRPP* 10% to 90% rise time of VPP 5 µs
2 TFPP* 90% to 10% fall time VPP 5 µs
3 TPGM VPP programming pulse width 90 100 (500 Retry) µs
4 TSVC VPP setup to CLK for entering programming 100 ns
5 THVC VPP hold from CLK for entering programming 300 ns
6 TSDP Data setup to CLK for programming 50 ns
7 THDP Data hold from CLK for programming 0 ns
8 TSCC setup from programming/verifying 100 ns
9 TON Reset Pulse Width 5 ms
10 TSCV hold from CLK for programming/verifying 100 ns
11 THCV hold from VPP for programming 50 ns
12 TSIC setup to CLK for incrementing address 100 ns
13 THIC hold from CLK for incrementing address 0 ns
14 TCAC CLK to data valid 400 ns
15 TOH Data hold from CLK 0 ns
16 TCE low to data valid 250 ns

* Use the fastest rise and fall time (permitting no overshoot or undershoot) your hardware can
support.

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

Start

Enter PGM Mode

Incorrect
Read Mfg Code Issue Error Message "A"

Correct

Incorrect
Read Device ID Issue Error Message "A"

Correct

Power Down

Power Up In Read Mode

(Normal Mode)

No Device Data
Issue Message "B"
Array Blank
Yes

Power Down
Code Message
A Manufacturer Or Device ID Error
Enter PGM Mode
B Device Not Blank
C Device Not Blank, Reset Polarity Low
Sense Reset Polarity State
D Device Failed To Program
E Reset Failed To Program
F Failed Margin Verify
No Reset Active
Issue Message "C" G Device Passed
High

Yes

Power Down

Figure 1. Programming Flow

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

Enter PGM Mode

Yes Data Word Blank

(FFFFFFFFFFFFF
FFFH)
No

Load Data Word To Device

Pulse VPP to VPP1 for 100us

Read Device Word

Compare Device Fail

Word To Data
Word
Pulse VPP to VPP1 for 500us
Pass
Read Device Word

Increment Address
Counter Compare
Pass
Device Word To
Data Word
Fail

Pulse VPP to VPP1 For 500us

Read Device Word

Pass
Compare
Device Word To
Data Word
Fail

No Last Data Power Down

Word?
Issue Msg "D"
Yes

Power Down

II

*32 or 64 bits, See Programming Overview

Figure 1. Programming Flow (Continued)

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL Family

II

Program Reset No
Polarity

Yes

Enter Programming Mode

Clock To Reset Row

Load Data Latches With O's

Pulse VPP With VPP1 For 5ms

Fail

No/Fail
Issue Message "E" Sense CEO Reset
Active Low?

Device Power Off Yes/Pass

Exit Programming Mode

Stop Device Power Off

Power Up In Read Mode

VCC = VCCVFY
VPP = VPPVFY

Fail Margin Verify

Issue Message "F"
All Data Bits

Device Power Off Pass

Device Power Off

Stop

Issue Message "G"

Figure 1. Programming Flow (Continued)

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

VCC =VCCP

VCC VPP1

VPP2
Enter 100 µs 500 µs 500 µs 100 µs
VPP Programming Programming Over Programming
Programming Programming
Mode Pulse Pulse Pulse Pulse
(Retry) (Retry)

CLK
Load Data Verify Data Verify Data Verify Data Load Data Verify Data
Word Word Word Word Word Word
Clock Increments
Address Counter

CE

RESET/OE

CEO

Figure 2. Programming Cycle Overview

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

VCCP

VCC
VPP1

VPPNOM VPPNOM

1 TFPP 2
VPP TRPP
5
TSVC 4 THVC TSVC
4

CLK

DATA

CE

RESET/OE

Figure 3. Enter Programming Mode

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

V PP1

V PP
VPP2

13
CLK 14
6
12
7 15

DATA
1 2 Last Bit 1 2 3 Last Bit

8 16

CE

RESET/OE
Load Prom Internal Program Increment
Data Latches Pulse Read Current Device Word Word
Counter

Figure 4. Details Of The Programming Cycle

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

VCCP

VCC VPP1

VPP2
VPPNOM
5 ms
VPP Enter Programming
Programming Reset Polarity
Mode

CLK
Load
Zeros **
Clock Increments
Address Counter *

CE

RESET/OE
(Reset active low)

CEO
(Reset active high-failed)

* Number of Clocks for the Device Reset Polarity Location

** Number of Clocks for the Device Word

Figure 5. Programming Reset Polarity

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

VPP2
VPP
GND

VCCP
VCC
GND

1 ms
CE
GND

RESET/OE

GND

CLK
GND

If your programming hardware does not allow VPP and VCC to power up and
down simultaneously, make sure to first power up VPP during power up and
power down VPP after VCC during power down.

Figure 6. Exit Programming Mode

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 XILINX PROGRAMMER QUALIFICATION SPECIFICATION

XC17S00, & XC17S00XL

VPPVFY

Read All Device Data Bits

VPP
VCCVFY

VCC VIH (VCCVFY level)

1
CLK 4
1
5
VIH (VCCVFY level)

1 2 3 Last Bit
DATA 1
6
9

CE
(With Reset Polarity Bit programmed, '0')

RESET/OE (With Reset Polarity Bit unprogrammed, '1')

Verify CEO low one

CEO clock after last bit
(output)

Figure 7. Details Of Verify Cycle

03/00 Rev. 2.1 16