A B C D E

1 1

VBLE4 / VBLE5
2
Eureka 2

LA-8868P REV 1.0 Schematic

3
AMD Brazos 2.0 / Zacate APU / Hudson-M3L FCH 3

2012-07-12 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/05/18 2013/10/05 Title
Issued Date Deciphered Date SCHEMATIC, MB A8868
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 1 of 47
A B C D E
 A B C D E

Two DIMM/One Channel

CRT
page 20
1.5V DDRIII 800MHZ
200pin DDRIII-SO-DIMM X2
LVDS Conn. BANK 0, 1, 2, 3 page9,10
1
page 19 AMD Zacate APU 1

Memory BUS(DDRIII)
HDMI Conn. FT1 1.5V DDRIII 1066
page 21 BGA 413-Ball USB PORT 2.0 x2(Right)
USB port 0,1 page 27 Daughter board
19mm x 19mm
PCIE-Express 4X 5GHz USB PORT 2.0 x2(Left)
page 5,6,7,8
USB port 10, 11 page 28

x4 UMI Gen. 1
2.5GT/s per lane 2IN1 RTS5129 Daughter board
USB port 7 page 32

USB2.0x6
VGA (DDR3) 5V 480MHz Int. Camera
USB port 5 page 19
ATI Seymour XTX S3 64bit with 1GB
page 11~18
Hudson M3L
2
(A38M) 2

PCIeMini Card
BGA 656-Ball WiMax
23mm x 23mm USB port 8
page 29

HDMI Conn. LCD Conn. CRT PCIe 1x PCIeMini Card

page 19 page 20
1.5V 2.5GHz(250MB/s) WLAN
page 21
RTL8105E-VB 10/100M PCIe port 1
PCIe 1x page 29
RJ45 RTL811F Giga page 36
page 36 1.5V 2.5GHz(250MB/s)
PCIe port 0
SATA port 0 SATA HDD
USB3.0x2 5V 3GHz(300MB/s) page 27
USB PORT 3.0 x2(Left)
USB3.0 port 0,1 page 28
SATA port 1 SATA ODD
page 22~26
5V 3GHz(300MB/s) page 27

3.3V 33 MHz
LPC BUS
HD Audio 3.3V/1.5V 24MHz
3 3

HDA Codec
TPM Debug Port ENE KB9012 ALC259-GR
page 31
page 32 page 34 page 33

RTC CKT. SPK Conn JCRIO

JTP page 31
Int.KBD (HP &page
MIC)
RUSB+Power/B (Touch Pad) page 34 32
page 35
LS-8865P page 27
Power On/Off CKT.
Audio+CR/B
LS-8864P page 32

DC/DC Interface CKT. ODD/B

4 4

LS-8862P page 27 Daughter board

Power Circuit DC/DC TP/B

LS-8863P page 35 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 2 of 47
A B C D E
 A B C D E

DESIGN CURRENT 0.1A +3VL

B+ DESIGN CURRENT 0.1A +5VL
DESIGN CURRENT 4A +5VALW

1 SUSP 1

N-CHANNEL DESIGN CURRENT 6.5A +5VS

SI4800BDY
ODD_PWR
DESIGN CURRENT 1.5A +5VS_ODD
A03413-SOT23
SUSP#

DESIGN CURRENT 2.6A +1.8VS

Y8032ABC

RT8205LZQW
FCH_PWR_EN

DESIGN CURRENT 1.2A +1.1VALW

SY8036LDBC SUSP

N-CHANNEL DESIGN CURRENT 3.8A +1.1VS

FDS6676AS-SO8

SUSP#

DESIGN CURRENT 2.5A +1.05VS

2 APL5916KAI-TRL 2

DESIGN CURRENT 1.7A +3VALW

SUSP

N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800BDY
LCD_ENVDD

P-CHANNEL DESIGN CURRENT 2.0A +LCD_VDD

AO-3413

WLAN_PWR#
DESIGN CURRENT 500mA +3V_LAN
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 11A +APU_CORE
RT8870AZQW DESIGN CURRENT 10A +APU_CORE_NB
3 3

SYSON
DESIGN CURRENT 7A +1.5V
RT8207MZQW SUSP

N-CHANNEL DESIGN CURRENT 5A +1.5VS

SI4800BDY

SUSP#

DESIGN CURRENT 3A +1.0VS

APL5930KAI-TRG

DESIGN CURRENT 1.5A +0.75VS

SUSP#
DESIGN CURRENT 21.6A +VGA_CORE
TPS51518RUK
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/05/18 2013/10/05 Title
Issued Date Deciphered Date SCHEMATIC, MB A8868

A B
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Size Document Number
Custom

Date:
4019K4
Saturday, September 07, 2013
E
Sheet 3 of 47
Rev
B
 A B C D E

Symbol Note :
O MEANS ON X MEANS OFF
Voltage Rails
: means Digital Ground : means Analog Ground

@ : means just reserve , no build

+5VS K625R3@ : means just for 1.5G CPU
K125R3@ : means just for 1.7G CPU
1 1
+3VS
power
plane +2.5VS K325R3@ : means just for 1.3G CPU
+1.8VS K625R1@ : means just for 1.5G CPU
+1.5VS K125R1@ : means just for 1.7G CPU
B+ +5VALW +1.5V
+1.1VS K325R1@ : means just for 1.3G CPU
+3VL +3VALW
+0.9VS M@ : means just reserve for
+5VL +1.1VALW
+0.75VS
+NB_CORE 13.3: control
S@ means just reserve for 11.6 control
State
+RTCVCC +VDDNB GSENSOR@ : means just reserve for G sensor
+CPU_CORE_0 part 1ST@ : means just reserve 1st G sensor
IC
1STGSENSOR@ : means just reserve 1st G sensor
IC 2ND@ : means just reserve 2nd G sensor IC
2NDGSENSOR@ : means just reserve 2nd G sensor
IC NOSIDE@ : means just reserve NOSIDE
S0
O O O O SIDE@ : means just reserve SIDE
port : means just for
RS880MR1@
S1
O O O O RS880MR1 : means just for
RS880MR3@
RS880MR3 : means just for SB820MR1
SB820MR1@
2 2

S3
O O O X SB820MR3@ : means just for SB820MR3

S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

SB SM Bus1 Address SB SM Bus2 Address

Power Device HEX Address Power Device HEX Address

3 3
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b +3VALW WLAN/WIMAX
SMBUS Control Table
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
+3VS Clock Generator D2 H 1101 0010 b CPU
SOURCE BATT SODIMM 0 CLK WLAN LCD HDMI
THERMAL GEN DDC DDC APU
WWAN
SENSOR ROM ROM
EC_SMB_CK1
KB926
EC_SMB_DA1 V
EC_SMB_CK2
KB926 V
EC_SMB_DA2
LCD_EDID_CLK
APU FT1
EC SM Bus1 Address EC SM Bus2 Address LCD_EDID_DATA V
HDMICLK
APU FT1
Power Device HEX Address Power Device HEX Address HDMIDAT V
SMB_CK_CLK0
+3VL Smart Battery 16 H 0001 011X b +3VS CPU_ADM1032-1 98 H 1001 100X b FCH M1
SMB_CK_DAT0 V
+3VS G-Sensor SMB_CK_CLK1
FCH M1
4
SMB_CK_DAT1 V 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 4 of 47
A B C D E
 A B C D E

PCIE_CTX_GRX_P[3..0]
<11> PCIE_CTX_GRX_P[3..0]
PCIE_CTX_GRX_N[3..0]
<11> PCIE_CTX_GRX_N[3..0]

PCIE_CRX_GTX_P[3..0]
<11> PCIE_CRX_GTX_P[3..0]
PCIE_CRX_GTX_N[3..0]
<11> PCIE_CRX_GTX_N[3..0]

1 1

U1A E1R1@
PCIE_CRX_GTX_P0 AA6 AB6 PCIE_CTX_C_GRX_P0 C518 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 Y6 P_GPP_RXP0 P_GPP_TXP0 AC6 PCIE_CTX_C_GRX_N0 C519 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_N0
P_GPP_RXN0 P_GPP_TXN0
PCIE_CRX_GTX_P1 AB4 AB3 PCIE_CTX_C_GRX_P1 C520 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_P1

PCIE I/F
PCIE_CRX_GTX_N1 AC4 P_GPP_RXP1 P_GPP_TXP1 AC3 PCIE_CTX_C_GRX_N1 C521 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_N1
P_GPP_RXN1 P_GPP_TXN1
PCIE_CRX_GTX_P2 AA1 Y1 PCIE_CTX_C_GRX_P2 C522 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AA2 P_GPP_RXP2 P_GPP_TXP2 Y2 PCIE_CTX_C_GRX_N2 C523 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_N2
P_GPP_RXN2 P_GPP_TXN2
PCIE_CRX_GTX_P3 Y4 V3 PCIE_CTX_C_GRX_P3 C524 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 Y3 P_GPP_RXP3 P_GPP_TXP3 V4 PCIE_CTX_C_GRX_N3 C525 1 2 DIS@ 0.1U_0402_16V7K PCIE_CTX_GRX_N3
P_GPP_RXN3 P_GPP_TXN3
+1.05VS 1 R1 2 DIS@ P_ZVDD_10 Y14 AA14 P_ZVSS DIS@ 1 R2 2
2K_0402_1% P_ZVDD_10 P_ZVSS 1.27K_0402_1%

<22> UMI_RX0P AA12 AB12 UMI_TX0P_C C2 1 2 0.1U_0402_16V7K

P_UMI_RXP0 P_UMI_TXP0 UMI_TX0P <22>
<22> UMI_RX0N Y12 AC12 UMI_TX0N_C C1 1 2 0.1U_0402_16V7K
P_UMI_RXN0 P_UMI_TXN0 UMI_TX0N <22>

<22> UMI_RX1P AA10 AC11 UMI_TX1P_C C4 1 2 0.1U_0402_16V7K

P_UMI_RXP1 P_UMI_TXP1 UMI_TX1P <22>
Y10 AB11 UMI_TX1N_C C3 1 2 0.1U_0402_16V7K

UMI I/F
<22> UMI_RX1N P_UMI_RXN1 P_UMI_TXN1 UMI_TX1N <22>
From FCH <22> UMI_RX2P AB10 AA8 UMI_TX2P_C C5 1 2 0.1U_0402_16V7K
To FCH
P_UMI_RXP2 P_UMI_TXP2 UMI_TX2P <22>
<22> UMI_RX2N AC10 Y8 UMI_TX2N_C C6 1 2 0.1U_0402_16V7K
P_UMI_RXN2 P_UMI_TXN2 UMI_TX2N <22>
<22> UMI_RX3P AC7 AB8 UMI_TX3P_C C8 1 2 0.1U_0402_16V7K
P_UMI_RXP3 P_UMI_TXP3 UMI_TX3P <22>
<22> UMI_RX3N AB7 AC8 UMI_TX3N_C C7 1 2 0.1U_0402_16V7K
P_UMI_RXN3 P_UMI_TXN3 UMI_TX3N <22>
S IC E SERIES EME450GBB22GVA 1.65G BGA
2 2

FAN Control Circuit

+5VS JFAN @
1A +FAN 1
2 1
3 2
2 2 3
3 C18 C20 3
10U_0805_10V6K 1000P_0402_50V7K 4
@ 5 GND
U3 1 1 GND
1 8 ACES_85204-0300N
2 EN GND 7
+FAN 3 VIN GND 6 R63 10K_0402_5%
4 VOUT GND 5 2 1
<33> EN_DFAN1 VSET GND +3VS
10mil 1
APL5607KI-TRG_SO8
FAN_SPEED1 <33>
C36 1
10U_0805_10V6K C19
2 0.01U_0402_25V7K
@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 5 of 47
A B C D E
 1 2 3 4 5

A A

U1E E1R1@
DDR_A_MA0 R17 B14 DDR_A_D0
<9,10> DDR_A_MA0 M_ADD0 M_DATA0 DDR_A_D0 <9,10>
DDR_A_MA1 H19 A15 DDR_A_D1
<9,10> DDR_A_MA1 M_ADD1 M_DATA1 DDR_A_D1 <9,10>
DDR_A_MA2 J17 A17 DDR_A_D2
<9,10> DDR_A_MA2 M_ADD2 M_DATA2 DDR_A_D2 <9,10>
DDR_A_MA3 H18 D18 DDR_A_D3
<9,10> DDR_A_MA3 M_ADD3 M_DATA3 DDR_A_D3 <9,10>
DDR_A_MA4 H17 A14 DDR_A_D4
<9,10> DDR_A_MA4 M_ADD4 M_DATA4 DDR_A_D4 <9,10>
DDR_A_MA5 G17 C14 DDR_A_D5
<9,10> DDR_A_MA5 M_ADD5 M_DATA5 DDR_A_D5 <9,10>
DDR_A_MA6 H15 C16 DDR_A_D6
<9,10> DDR_A_MA6 M_ADD6 M_DATA6 DDR_A_D6 <9,10>
DDR_A_MA7 G18 D16 DDR_A_D7
<9,10> DDR_A_MA7 M_ADD7 M_DATA7 DDR_A_D7 <9,10>
DDR_A_MA8 F19
<9,10> DDR_A_MA8 M_ADD8
DDR_A_MA9 E19 C18 DDR_A_D8
<9,10> DDR_A_MA9 M_ADD9 M_DATA8 DDR_A_D8 <9,10>
DDR_A_MA10 T19 A19 DDR_A_D9
<9,10> DDR_A_MA10 M_ADD10 M_DATA9 DDR_A_D9 <9,10>
DDR_A_MA11 F17 B21 DDR_A_D10
<9,10> DDR_A_MA11 M_ADD11 M_DATA10 DDR_A_D10 <9,10>
DDR_A_MA12 E18 D20 DDR_A_D11
<9,10> DDR_A_MA12 M_ADD12 M_DATA11 DDR_A_D11 <9,10>
DDR_A_MA13 W17 A18 DDR_A_D12
<9,10> DDR_A_MA13 M_ADD13 M_DATA12 DDR_A_D12 <9,10>
DDR_A_MA14 E16 B18 DDR_A_D13
<9,10> DDR_A_MA14 M_ADD14 M_DATA13 DDR_A_D13 <9,10>
DDR_A_MA15 G15 A21 DDR_A_D14
<9,10> DDR_A_MA15 M_ADD15 M_DATA14 DDR_A_D14 <9,10>

DDR SYSTEM MEMORY

C20 DDR_A_D15
M_DATA15 DDR_A_D15 <9,10>
DDR_A_BS#0 R18
<9,10> DDR_A_BS#0 M_BANK0
DDR_A_BS#1 T18 C23 DDR_A_D16
<9,10> DDR_A_BS#1 M_BANK1 M_DATA16 DDR_A_D16 <9,10>
DDR_A_BS#2 F16 D23 DDR_A_D17
<9,10> DDR_A_BS#2 M_BANK2 M_DATA17 DDR_A_D17 <9,10>
F23 DDR_A_D18
M_DATA18 DDR_A_D18 <9,10>
DDR_A_DM0 D15 F22 DDR_A_D19
<9,10> DDR_A_DM0 M_DM0 M_DATA19 DDR_A_D19 <9,10>
DDR_A_DM1 B19 C22 DDR_A_D20
<9,10> DDR_A_DM1 M_DM1 M_DATA20 DDR_A_D20 <9,10>
DDR_A_DM2 D21 D22 DDR_A_D21
<9,10> DDR_A_DM2 M_DM2 M_DATA21 DDR_A_D21 <9,10>
DDR_A_DM3 H22 F20 DDR_A_D22
<9,10> DDR_A_DM3 M_DM3 M_DATA22 DDR_A_D22 <9,10>
DDR_A_DM4 P23 F21 DDR_A_D23
<9,10> DDR_A_DM4 M_DM4 M_DATA23 DDR_A_D23 <9,10>
DDR_A_DM5 V23
<9,10> DDR_A_DM5 M_DM5
DDR_A_DM6 AB20 H21 DDR_A_D24
<9,10> DDR_A_DM6 M_DM6 M_DATA24 DDR_A_D24 <9,10>
DDR_A_DM7 AA16 H23 DDR_A_D25
<9,10> DDR_A_DM7 M_DM7 M_DATA25 DDR_A_D25 <9,10>
K22 DDR_A_D26
B M_DATA26 DDR_A_D26 <9,10> B
DDR_A_DQS0 A16 K21 DDR_A_D27
<9,10> DDR_A_DQS0 M_DQS_H0 M_DATA27 DDR_A_D27 <9,10>
DDR_A_DQS#0 B16 G23 DDR_A_D28
<9,10> DDR_A_DQS#0 M_DQS_L0 M_DATA28 DDR_A_D28 <9,10>
DDR_A_DQS1 B20 H20 DDR_A_D29
<9,10> DDR_A_DQS1 M_DQS_H1 M_DATA29 DDR_A_D29 <9,10>
DDR_A_DQS#1 A20 K20 DDR_A_D30
<9,10> DDR_A_DQS#1 M_DQS_L1 M_DATA30 DDR_A_D30 <9,10>
DDR_A_DQS2 E23 K23 DDR_A_D31
<9,10> DDR_A_DQS2 M_DQS_H2 M_DATA31 DDR_A_D31 <9,10>
DDR_A_DQS#2 E22
<9,10> DDR_A_DQS#2 M_DQS_L2
DDR_A_DQS3 J22 N23 DDR_A_D32
<9,10> DDR_A_DQS3 M_DQS_H3 M_DATA32 DDR_A_D32 <9,10>
DDR_A_DQS#3 J23 P21 DDR_A_D33
<9,10> DDR_A_DQS#3 M_DQS_L3 M_DATA33 DDR_A_D33 <9,10>
DDR_A_DQS4 R22 T20 DDR_A_D34
<9,10> DDR_A_DQS4 M_DQS_H4 M_DATA34 DDR_A_D34 <9,10>
DDR_A_DQS#4 P22 T23 DDR_A_D35
<9,10> DDR_A_DQS#4 M_DQS_L4 M_DATA35 DDR_A_D35 <9,10>
DDR_A_DQS5 W22 M20 DDR_A_D36
<9,10> DDR_A_DQS5 M_DQS_H5 M_DATA36 DDR_A_D36 <9,10>
DDR_A_DQS#5 V22 P20 DDR_A_D37
<9,10> DDR_A_DQS#5 M_DQS_L5 M_DATA37 DDR_A_D37 <9,10>
DDR_A_DQS6 AC20 R23 DDR_A_D38
<9,10> DDR_A_DQS6 M_DQS_H6 M_DATA38 DDR_A_D38 <9,10>
DDR_A_DQS#6 AC21 T22 DDR_A_D39
<9,10> DDR_A_DQS#6 M_DQS_L6 M_DATA39 DDR_A_D39 <9,10>
DDR_A_DQS7 AB16
<9,10> DDR_A_DQS7 M_DQS_H7
DDR_A_DQS#7 AC16 V20 DDR_A_D40
<9,10> DDR_A_DQS#7 M_DQS_L7 M_DATA40 DDR_A_D40 <9,10>
V21 DDR_A_D41
M_DATA41 DDR_A_D41 <9,10>
DDR_A_CLK0 M17 Y23 DDR_A_D42
<9> DDR_A_CLK0 M_CLK_H0 M_DATA42 DDR_A_D42 <9,10>
DDR_A_CLK#0 M16 Y22 DDR_A_D43
<9> DDR_A_CLK#0 M_CLK_L0 M_DATA43 DDR_A_D43 <9,10>
DDR_A_CLK1 M19 T21 DDR_A_D44
<9> DDR_A_CLK1 M_CLK_H1 M_DATA44 DDR_A_D44 <9,10>
DDR_A_CLK#1 M18 U23 DDR_A_D45
<9> DDR_A_CLK#1 M_CLK_L1 M_DATA45 DDR_A_D45 <9,10>
DDR_B_CLK2 N18 W23 DDR_A_D46
<10> DDR_B_CLK2 M_CLK_H2 M_DATA46 DDR_A_D46 <9,10>
DDR_B_CLK#2 N19 Y21 DDR_A_D47
<10> DDR_B_CLK#2 M_CLK_L2 M_DATA47 DDR_A_D47 <9,10>
DDR_B_CLK3 L18
<10> DDR_B_CLK3 M_CLK_H3
DDR_B_CLK#3 L17 Y20 DDR_A_D48
+1.5V <10> DDR_B_CLK#3 M_CLK_L3 M_DATA48 DDR_A_D48 <9,10>
AB22 DDR_A_D49
M_DATA49 DDR_A_D49 <9,10>
DDR_RST# L23 AC19 DDR_A_D50
<9,10> DDR_RST# M_RESET_L M_DATA50 DDR_A_D50 <9,10>
MA_EVENT_L N17 AA18 DDR_A_D51
<9,10> MA_EVENT_L M_EVENT_L M_DATA51 DDR_A_D51 <9,10>
R4 1 2 1K_0402_5% MA_EVENT_L AA23 DDR_A_D52
M_DATA52 DDR_A_D52 <9,10>
AA20 DDR_A_D53
M_DATA53 DDR_A_D53 <9,10>
DDR_CKE0_DIMMA F15 AB19 DDR_A_D54
<9,10> DDR_CKE0_DIMMA M_CKE0 M_DATA54 DDR_A_D54 <9,10>
DDR_CKE1_DIMMA E15 Y18 DDR_A_D55
<9,10> DDR_CKE1_DIMMA M_CKE1 M_DATA55 DDR_A_D55 <9,10>
AC17 DDR_A_D56
M_DATA56 DDR_A_D56 <9,10>
C Y16 DDR_A_D57 C
M_DATA57 DDR_A_D57 <9,10> +1.5V
DDR_A_ODT0 W19 AB14 DDR_A_D58
<9> DDR_A_ODT0 M0_ODT0 M_DATA58 DDR_A_D58 <9,10>
DDR_A_ODT1 V15 AC14 DDR_A_D59
<9> DDR_A_ODT1 M0_ODT1 M_DATA59 DDR_A_D59 <9,10>
DDR_B_ODT0 U19 AC18 DDR_A_D60
<10> DDR_B_ODT0 M1_ODT0 M_DATA60 DDR_A_D60 <9,10>

2
DDR_B_ODT1 W15 AB18 DDR_A_D61
<10> DDR_B_ODT1 M1_ODT1 M_DATA61 DDR_A_D61 <9,10>
AB15 DDR_A_D62 R5
M_DATA62 DDR_A_D62 <9,10>
DDR_CS0_DIMMA# T17 AC15 DDR_A_D63 1K_0402_1%
8/6 Add C78 for ESD request <9>
<9>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS1_DIMMA# W16 M0_CS_L0
M0_CS_L1
M_DATA63 DDR_A_D63 <9,10>
15 mil
DDR_CS0_DIMMB# U17
<10> DDR_CS0_DIMMB#

1
DDR_CS1_DIMMB# V16 M1_CS_L0 M23 +MEM_VREF
<10> DDR_CS1_DIMMB# M1_CS_L1 M_VREF

2
DDR_RST# DDR_A_RAS# U18
<9,10> DDR_A_RAS# M_RAS_L
DDR_A_CAS# V19 1 1 R7
<9,10> DDR_A_CAS# M_CAS_L
1 DDR_A_WE# V17 M22 M_ZVDDIO_MEM_S R6 1 2 39.2_0402_1% +1.5V 1K_0402_1%
<9,10> DDR_A_WE# M_WE_L M_ZVDDIO_MEM_S C13 C14
C78 S IC E SERIES EME450GBB22GVA 1.65G BGA 0.1U_0402_16V7K

1
180P_0402_50V8J 1000P_0402_25V8J 2 2
2

Close to CPU within 1"

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,
Size Document Number
MB A8868 Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
4019K4Sheet 6 of 47
Saturday, September 07, 2013
1 2 3 4 5
 5 4 3 2 1

+1.8VS
U1B E1R1@

R10 1 2 1K_0402_5% APU_SVC A8 H3 DP_ZVSS R20 1 UMA@ 2 150_0402_1% UMA_ENBKL R933 1 UMA@ 2 100K_0402_5%

DISPLAYPORT 1
<21> UMA_HDMI_TX2+ TDP1_TXP0 DP_ZVSS
B8

DP MISC
<21> UMA_HDMI_TX2- TDP1_TXN0
R23 1 2 1K_0402_5% APU_SVD G2 UMA_ENBKL <19> UMA_CRT_R R407 1 UMA@ 2 150_0402_1%
B9 DP_BLON H2
<21> UMA_HDMI_TX1+ TDP1_TXP1 DP_DIGON UMA_ENVDD <19>
R24 1 2 300_0402_5% APU_RST# A9 H1 UMA_PWM <19> UMA_CRT_G R408 1 UMA@ 2 150_0402_1%
<21> UMA_HDMI_TX1- TDP1_TXN1 DP_VARY_BL
R22 1 2 300_0402_5% APU_PWRGD D10 UMA_CRT_B R409 1 UMA@ 2 150_0402_1%
D <21> UMA_HDMI_TX0+ TDP1_TXP2 D
C10 B2 UMA_HDMI_CLK
<21> UMA_HDMI_TX0- TDP1_TXN2 TDP1_AUXP UMA_HDMI_CLK <21>
R26 1 2 510_0402_1% TEST_25_L C2 UMA_HDMI_DATA
TDP1_AUXN UMA_HDMI_DATA <21>
A10
<21> UMA_HDMI_TXC+ TDP1_TXP3
R25 1 2 1K_0402_5% TEST36 B10 C1
<21> UMA_HDMI_TXC- TDP1_TXN3 TDP1_HPD UMA_HDMI_HPD <21>

<19> UMA_TXOUT2+ B5 A3 LCD_EDID_CLK

LTDP0_TXP0 LTDP0_AUXP UMA_EDID_CLK <19>
A5 B3 LCD_EDID_DATA

DISPLAYPORT 0
<19> UMA_TXOUT2- LTDP0_TXN0 LTDP0_AUXN UMA_EDID_DATA <19>
APU_RST# 1 2
C103 @ 100P_0402_50V8J <19> UMA_TXOUT1+ D6 D3 R12 1 UMA@ 2 100K_0402_5%
C6 LTDP0_TXP1 LTDP0_HPD
<19> UMA_TXOUT1- LTDP0_TXN1
APU_PWRGD 1 2 C12
DAC_RED UMA_CRT_R <20> +3VS
C104 @ 100P_0402_50V8J <19> UMA_TXOUT0+ A6 D13
B6 LTDP0_TXP2 DAC_REDB A12
<19> UMA_TXOUT0- LTDP0_TXN2 DAC_GREEN UMA_CRT_G <20>
B12
D8 DAC_GREENB A13 UMA_CRT_CLK 4.7K_0402_5% 2 UMA@ 1 R83
12/13 For debug if layout cross mote

VGA DAC
<19> UMA_TXCLK+ LTDP0_TXP3 DAC_BLUE UMA_CRT_B <20>
<19> UMA_TXCLK- C8 B13
LTDP0_TXN3 DAC_BLUEB UMA_CRT_DATA 4.7K_0402_5% 2 UMA@ 1 R82
V2 E1
<22> APU_CLK CLKIN_H DAC_HSYNC UMA_CRT_HSYNC <20>
V1 E2 UMA_EDID_CLK 2K_0402_1% 2 UMA@ 1 R510
<22> APU_CLK# CLKIN_L DAC_VSYNC UMA_CRT_VSYNC <20>
D2 F2 UMA_CRT_CLK UMA_EDID_DATA 2K_0402_1% 2 UMA@ 1 R511

CLK
<22> APU_DISP_CLK DISP_CLKIN_H DAC_SCL UMA_CRT_CLK <20>
D1 D4 UMA_CRT_DATA
<22> APU_DISP_CLK# DISP_CLKIN_L DAC_SDA UMA_CRT_DATA <20>
UMA_HDMI_CLK 2K_0402_1% 2 UMA@ 1 R515
APU_SVC J1 D12 DAC_ZVSS R30 1 UMA@ 2 499_0402_1%
<43> APU_SVC SVC DAC_ZVSS
APU_SVD J2 UMA_HDMI_DATA 2K_0402_1% 2 UMA@ 1 R516
+3VS <43> APU_SVD SVD

SER
R1 PAD T3
1 @ 2 APU_SIC P3 TEST4 R2
<18,33> EC_SMB_CK2 SIC TEST5 PAD T4
TO EC R809 1 @ 2 0_0402_5% APU_SID P4 R6 12/22 Change R510, R511,R515,R516
<18,33> EC_SMB_DA2 SID TEST6
R16 1 2 1K_0402_5% APU_ALERT# R810 0_0402_5% T5 PAD T5
APU_RST# T3 TEST14 E4 to 2k that meet AMD check list
<22> APU_RST# RESET_L TEST15
R17 1 2 1K_0402_5% APU_PROCHOT# APU_PWRGD T4 K4 PAD T6
<22,43> APU_PWRGD

CTRL
PWROK TEST16 L1
TEST17 PAD T7
C R19 1 2 1K_0402_5% APU_SIC 1 @ 2 APU_PROCHOT# U1 L2 TEST_18 R33 1 2 1K_0402_5% C
<22,33> H_PROCHOT# PROCHOT_L TEST18
R34 0_0402_5% APU_THERMTRIP#_R U2 M2 TEST_19 R35 1 2 1K_0402_5%

TEST
R31 1 2 1K_0402_5% APU_SID APU_ALERT# T2 THERMTRIP_L TEST19 K1 TEST25_H R36 1 2 510_0402_1%
ALERT_L TEST25_H K2 TEST_25_L
APU_TDI N2 TEST25_L L5 TEST28_H
TDI TEST28_H PAD T9
APU_TDO N1 M5 TEST28_L PAD T8
APU_TCK P1 TDO TEST28_L M21 TEST31
TCK TEST31 PAD T10

JTAG
APU_TMS P2 J18 TEST33_H C15 1 2 0.1U_0402_16V4Z R37 1 2 51_0402_1%
APU_TRST# M4 TMS TEST33_H J19 TEST33_L C16 1 2 0.1U_0402_16V4Z R38 1 2 51_0402_1%
APU_DBRDY M3 TRST_L TEST33_L U15 TEST34_H
DBRDY TEST34_H PAD T11
APU_DBREQ# M1 T15 TEST34_L PAD T12
DBREQ_L TEST34_L H4 TEST35 R39 1 @ 2 1K_0402_5%
F4 TEST35 N5 TEST36
<43> APU_VDDNB_RUN_FB_H VDDCR_NB_SENSE TEST36
G1 R5 TEST37 PAD T15
<43> APU_VDD0_RUN_FB_H VDDCR_CPU_SENSE TEST37
T13PAD VDDIO_MEM_S_SENSE F3 R283 1 2 1K_0402_5% +1.8VS
VDDIO_MEM_S_SENSE
R931 1 2 0_0402_5% F1
<43> APU_VDD0_RUN_FB_L VSS_SENSE
Check K3
R932 1 2 0_0402_5% B4 TEST38 T1
<43> APU_VDDNB_RUN_FB_L RSVD_1 DMAACTIVE_L DMA_ACTIVE# <22>
W11
V5 RSVD_2 R40 1 2 1K_0402_5%
RSVD_3 +1.8VS
9/26 Add R931 R932 for AMD common design S IC E SERIES EME450GBB22GVA 1.65G BGA
SA00005DX00

+3VS

B
AMD HDT Debug Conn B
+1.8VS

R41

1
2
R44 1 2 1K_0402_5% APU_TRST#
10K_0402_5%
R45 1 2 1K_0402_5% APU_TCK R926
1K_0402_5%

2
R46 1 2 1K_0402_5% APU_TMS

1
R47 1 2 1K_0402_5% APU_TDI

2
B
R48 1 2 1K_0402_5% APU_DBREQ#
Q39

E
APU_THERMTRIP#_R 3 1
+1.8VS H_THERMTRIP# <24>

C
MMBT3904_NL_SOT23-3

JHDT R927 1 2 0_0402_5%

1 2 APU_TCK @
1 2
3 4 APU_TMS
3 4
5 6 APU_TDI
5 6
7 8 APU_TDO 12/22 PCH side has internal pull up +3VLAW_PCH,
7 8
APU_TRST# R846 2 @ 1 0_0402_5% 9 10 APU_PWRGD_R R854 1 @ 2 0_0402_5% APU_PWRGD so need to level shift
9 10
R847 2 @ 1 10K_0402_5% 11 12 APU_RST#_R R853 1 @ 2 0_0402_5% APU_RST#
A 11 12 A
R848 2 @ 1 10K_0402_5% 13 14 APU_DBRDY
13 14
To close APU side
R849 2 @ 1 10K_0402_5% 15 16 APU_DBREQ#
15 16
17 18 J108_PLLTST0 R851 1 @ 2 0_0402_5% TEST_19
17 18
19 20 J108_PLLTST1 R852 1 @ 2 0_0402_5% TEST_18
19 20 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

SAMTE_ASP-136446-07-B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 7 of 47
5 4 3 2 1
 A B C D E

U1D E1R1@
A7 N13
B7 VSS_1 VSS_50 N20
B11 VSS_2 VSS_51 N22
U1C E1R1@ +1.8VS_VDD L1 +1.8VS B17 VSS_3 VSS_52 P10
B22 VSS_4 VSS_53 P14
600mA VSS_5 VSS_54

TSense/PLL/DP/PCIE/IO
+APU_CORE E5 U8 0.1U_0402_16V7K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 C4 R4
E6 VDDCR_CPU_1 VDD_18_1 W8 D5 VSS_6 VSS_55 R7
VDDCR_CPU_2 VDD_18_2 1 1 1 1 1 1 1 FBMA-L11-201209-221LMA30T_0805 VSS_7 VSS_56
11000mA F5 U6 D7 R20
F7 VDDCR_CPU_3 VDD_18_3 U9 C75 @ C23 C24 C25 C26 C21 C22 D9 VSS_8 VSS_57 T6
G6 VDDCR_CPU_4 VDD_18_4 W6 10U_0603_6.3V6M D11 VSS_9 VSS_58 T9
G8 VDDCR_CPU_5 VDD_18_5 T7 2 2 2 2 2 2 2 D14 VSS_10 VSS_59 T11
H5 VDDCR_CPU_6 VDD_18_6 V7 180P_0402_50V8J 1U_0402_6.3V6K 1U_0402_6.3V6K B15 VSS_11 VSS_60 T13
VDDCR_CPU_7 VDD_18_7 VSS_12 VSS_61

CPU CORE
H7 D17 U4
1 J6 VDDCR_CPU_8 D19 VSS_13 VSS_62 U5 1
J8 VDDCR_CPU_9 E7 VSS_14 VSS_63 U7
VDDCR_CPU_10 VSS_15 VSS_64

GND
L7 NOTE-->VDD_18+VDD_18_DAC=600mA E9 U12
M6 VDDCR_CPU_11 E12 VSS_16 VSS_65 U20
M8 VDDCR_CPU_12 E20 VSS_17 VSS_66 U22
VDDCR_CPU_13 NOTE-->VDDPL_10+VDD_10=2500mA VSS_18 VSS_67
N7 F8 V8
R8 VDDCR_CPU_14 F11 VSS_19 VSS_68 V9
VDDCR_CPU_15 +1.8VS_DAC +1.8VS F13 VSS_20 VSS_69 V11
L2 G4 VSS_21 VSS_70 V13
VSS_22 VSS_71

DAC
+APU_VDDNB E8 W9 1U_0402_6.3V6K 1 2 G5 W1
E11 VDDCR_NB_1 VDD_18_DAC G7 VSS_23 VSS_72 W2
VDDCR_NB_2 1 1 1 FBMA-L11-201209-221LMA30T_0805 VSS_24 VSS_73
10000mA E13 G9 W4
F9 VDDCR_NB_3 C76 @ C28 C29 G12 VSS_25 VSS_74 W5
F12 VDDCR_NB_4 10U_0603_6.3V6M G20 VSS_26 VSS_75 W7
VDDCR_NB_5 2 2 2 VSS_27 VSS_76

GPU AND NB CORE

G11 G22 W12
G13 VDDCR_NB_6
VDDCR_NB_7
POWER 180P_0402_50V8J H6 VSS_28
VSS_29
VSS_77
VSS_78
W20
H9 +1.05VS H11 Y5
H12 VDDCR_NB_8 H13 VSS_30 VSS_79 Y7
K11 VDDCR_NB_9 +1.05VS_VDDPL J4 VSS_31 VSS_80 Y9
K13 VDDCR_NB_10 L3 J5 VSS_32 VSS_81 Y11
VDDCR_NB_11 VSS_33 VSS_82

DIS PLL
L10 U11 180P_0402_50V8J 1U_0402_6.3V6K 1 2 J7 Y13
L12 VDDCR_NB_12 VDDPL_10 FBMA-L11-201209-221LMA30T_0805 J20 VSS_34 VSS_83 Y15
VDDCR_NB_13 1 1 1 1 VSS_35 VSS_84
L14 K10 Y17
M11 VDDCR_NB_14 C77 @ C30 C31 C32 K14 VSS_36 VSS_85 Y19
M12 VDDCR_NB_15 10U_0603_6.3V6M L4 VSS_37 VSS_86 AA4
M13 VDDCR_NB_16 2 2 2 2 L6 VSS_38 VSS_87 AA22
N10 VDDCR_NB_17 0.1U_0402_16V7K L8 VSS_39 VSS_88 AB2
N12 VDDCR_NB_18 L11 VSS_40 VSS_89 AB5
N14 VDDCR_NB_19 +1.05VS_VDD L13 VSS_41 VSS_90 AB9
VDDCR_NB_20 VSS_42 VSS_91
PCIE/IO/DDR3 Phy

P11 2500mA L4 L20 AB13

P13 VDDCR_NB_21 U13 0.1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M 1 2 L22 VSS_43 VSS_92 AB17
VDDCR_NB_22 VDD_10_1 W13 FBMA-L11-201209-221LMA30T_0805 M7 VSS_44 VSS_93 AB21
2 VDD_10_2 V12 N4 VSS_45 VSS_94 AC5 2
VDD_10_3 1 1 1 1 1 1 1 VSS_46 VSS_95
+1.5V G16 T12 N6 AC9
G19 VDDIO_MEM_S_1 VDD_10_4 C94 @ C34 C35 C99 C37 C38 C39 N8 VSS_47 VSS_96 AC13
E17 VDDIO_MEM_S_2 10U_0603_6.3V6M N11 VSS_48 VSS_97 A11
2000mA J16 VDDIO_MEM_S_3 2 2 2 2 2 2 2 VSS_49 VSSBG_DAC
VDDIO_MEM_S_4
DDR3

L16
L19 VDDIO_MEM_S_5 180P_0402_50V8J 0.1U_0402_16V7K 1U_0402_6.3V6K S IC E SERIES EME450GBB22GVA 1.65G BGA
N16 VDDIO_MEM_S_6
R16 VDDIO_MEM_S_7 +3VS
DP Phy/IO

R19 VDDIO_MEM_S_8
W18 VDDIO_MEM_S_9
U16 VDDIO_MEM_S_10 A4
500mA
VDDIO_MEM_S_11 VDD_33
1 1
S IC E SERIES EME450GBB22GVA 1.65G BGA C40 C41
1U_0402_6.3V6K
2 2
0.1U_0402_16V7K

+1.5V

1U_0402_6.3V6K 1U_0402_6.3V6K
1 1 1 1 1 1
C85 C86 C87 C89 C92 C93
3 10U_0603_6.3V6M 3
2 2 2 2 2 2
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
Add for EMI request on DVT

+1.5V +1.5V

0.1U_0402_16V7K 180P_0402_50V8J
1 1 1 1 1 1 1 1
C96 C97 C98 C90 C91 C95 C102 C105
0.1U_0402_16V7K 1U_0402_6.3V6K 0.1U_0402_16V7K 180P_0402_50V8J
2 2 2 2 2 2 2 2
0.1U_0402_16V7K 180P_0402_50V8J

+1.5V

180P_0402_50V8J

1 1 1 1
C61 @ C60 @ C100 @ C101 @
0.1U_0402_16V7K
2 2 2 2

0.1U_0402_16V7K 180P_0402_50V8J

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 8 of 47
A B C D E
 5 4 3 2 1

+1.5V +1.5V

1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
3 VREF_DQ
VSS2
VSS1
DQ4
4 DDR_A_D4 Standard Type +1.5V +1.5V

1000P_0402_50V7K
DDR_A_D[0..63]

0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
1 1 DDR_A_D1 7 DQ0
DQ1
DQ5
VSS3
8 H=4.0mm DDR_A_D[0..63] <6,10>

2
C626

C627
9 10 DDR_A_MA[0..15]
VSS4 DQS#0 DDR_A_DQS#0 <6,10> DDR_A_MA[0..15] <6,10>
DDR_A_DM0 11 12 R440 R441
DM0 DQS0 DDR_A_DQS0 <6,10> DDR_A_DM[0..7]
13 14 DDR_A_DM[0..7] <6,10> 1K_0402_1% 1K_0402_1%
2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7

1
19 DQ3 DQ7 20
D VSS7 VSS8 +VREF_DQA +VREF_CAA D
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
DQ9 DQ13

2
25 26
27 VSS9 VSS10 28 DDR_A_DM1 R442 R443
<6,10> DDR_A_DQS#1 DQS#1 DM1
29 30 1K_0402_1% 1K_0402_1%
<6,10> DDR_A_DQS1 DQS1 RESET# DDR_RST# <6,10>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14

1
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
45 VSS15 VSS16 46 DDR_A_DM2
<6,10> DDR_A_DQS#2 DQS#2 DM2
47 48
<6,10> DDR_A_DQS2 DQS2 VSS17
49 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62
VSS22 DQS#3 DDR_A_DQS#3 <6,10>
DDR_A_DM3 63 64
DM3 DQS3 DDR_A_DQS3 <6,10>
65 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

+1.5V
73 74
C <6,10> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6,10> C
75 76 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
77 VDD1 VDD2 78 DDR_A_MA15
NC1 A15 2 2 2 2 2 2 2 2 2 2 2 2
79 80 DDR_A_MA14
<6,10> DDR_A_BS#2 BA2 A14
81 82 C628 C629 C630 C631 C632 C633 C634 C635 C636 C637 C638 C639
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11 @ @ @ @ @ @
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 1 1 1 1 1 1 1 1 1 1 1 1
87 A9 A7 88 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<6> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <6>
103 104
<6> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <6>
105 106
DDR_A_MA10 107 VDD11 VDD12 108
A10/AP BA1 DDR_A_BS#1 <6,10>
109 110
<6,10> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6,10>
111 112
113 VDD13 VDD14 114
<6,10> DDR_A_WE# 115 WE# S0# 116
DDR_CS0_DIMMA# <6> CRB 0.1u X1 4.7u X1 CRB 100U X2
<6,10> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 +1.5V
A13 ODT1 DDR_A_ODT1 <6>
121 122 +0.75VS
<6> DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CAA

4.7U_0603_6.3V6K
0.1U_0402_16V4Z
127 128
VSS27 VSS28

1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_A_D32 129 130 DDR_A_D36 2 1 1
DQ32 DQ36

C641

C642
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134 + C643
VSS29 VSS30

C669

C670
B 135 136 DDR_A_DM4 B
<6,10> DDR_A_DQS#4 DQS#4 DM4 330U_B2_2.5VM_R15M
137 138 1 2
<6,10> DDR_A_DQS4
139 DQS4 VSS31 140 DDR_A_D38 2 2 2 <BOM Structure>
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152
VSS36 DQS#5 DDR_A_DQS#5 <6,10> Place near JDIMML
DDR_A_DM5 153 154
DM5 DQS5 DDR_A_DQS5 <6,10>
155 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
169 VSS41 VSS42 170 DDR_A_DM6
<6,10> DDR_A_DQS#6 DQS#6 DM6
171 172
<6,10> DDR_A_DQS6 DQS6 VSS43
173 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186
VSS48 DQS#7 DDR_A_DQS#7 <6,10>
DDR_A_DM7 187 188
DM7 DQS7 DDR_A_DQS7 <6,10>
189 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
A R445 10K_0402_5% 195 DQ59 DQ63 196 A
1 2 197 VSS51 VSS52 198
SA0 EVENT# MA_EVENT_L <6,10>
0.1U_0402_16V4Z

199 200
+3VS VDDSPD SDA FCH_SDATA0 <10,24,29>
201 202
SA1 SCL FCH_SCLK0 <10,24,29>
1 203 204 +0.75VS
VTT1 VTT2
1

1
C647

C464 R446 205 206

2.2U_0603_10V6K G1 G2 Security Classification Compal Secret Data
2

2 10K_0402_5% LCN_DAN06-K4406-0102
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868
2

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 9 of 47
5 4 3 2 1

www.vinafix.vn
 5 4 3 2 1

+1.5V +1.5V DDR3 SO-DIMM B

1
JDDR3H
2
Standard Type +1.5V +1.5V
+VREF_DQB
3 VREF_DQ
VSS2
VSS1
DQ4
4 DDR_A_D4 H=8.0mm

2
1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8 R444 R450
1 1 DQ1 VSS3
9 10 1K_0402_1% 1K_0402_1%
VSS4 DQS#0 DDR_A_DQS#0 <6,9> DDR_A_D[0..63]
C648 C649 DDR_A_DM0 11 12
DM0 DQS0 DDR_A_DQS0 <6,9> DDR_A_D[0..63] <6,9>
13 14

1
2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 DDR_A_MA[0..15]
D DQ2 DQ6 DDR_A_MA[0..15] <6,9> +VREF_DQB +VREF_CAB D
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20 DDR_A_DM[0..7]
VSS7 VSS8 DDR_A_DM[0..7] <6,9>

2
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 R447 R451
25 DQ9 DQ13 26 1K_0402_1% 1K_0402_1%
27 VSS9 VSS10 28 DDR_A_DM1
<6,9> DDR_A_DQS#1 DQS#1 DM1
29 30
<6,9> DDR_A_DQS1 DDR_RST# <6,9>

1
31 DQS1 RESET# 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
45 VSS15 VSS16 46 DDR_A_DM2
<6,9> DDR_A_DQS#2 DQS#2 DM2 +1.5V
47 48
<6,9> DDR_A_DQS2 DQS2 VSS17 +1.5V
49 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D19 53 DQ18 DQ23 54
DQ19 VSS19 1 2 2 2 2 2 2
55 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29 + C199 C650 C651 C652 C653 C654 C655
DDR_A_D25 59 DQ24 DQ29 60 0.1U_0402_16V4Z
DQ25 VSS21 330U_B2_2.5VM_R15M
61 62 1 1 1 1 1 1
DDR_A_DM3 63 VSS22 DQS#3 64
DDR_A_DQS#3 <6,9> 2 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DM3 DQS3 DDR_A_DQS3 <6,9>
65 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

CRB 0.1u X1 4,7uX1

73 74
C <6,9> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6,9> C
75 76 +0.75VS
77 VDD1 VDD2 78 DDR_A_MA15
79 NC1 A15 80 DDR_A_MA14
<6,9> DDR_A_BS#2 BA2 A14

4.7U_0603_6.3V6K
0.1U_0402_16V4Z
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
A12/BC# A11 2 1
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7

C663

C664
87 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 1 2
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<6> DDR_B_CLK2 CK0 CK1 DDR_B_CLK3 <6>
103 104
<6> DDR_B_CLK#2 CK0# CK1# DDR_B_CLK#3 <6>
105 106
DDR_A_MA10 107 VDD11 VDD12 108
A10/AP BA1 DDR_A_BS#1 <6,9>
109 110
<6,9> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6,9>
111 112
113 VDD13 VDD14 114
<6,9> DDR_A_WE# WE# S0# DDR_CS0_DIMMB# <6>
115 116
<6,9> DDR_A_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 118
DDR_A_MA13 119 VDD15 VDD16 120
A13 ODT1 DDR_B_ODT1 <6>
121 122
<6> DDR_CS1_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CAB
127 128
VSS27 VSS28

1000P_0402_50V7K
0.1U_0402_16V4Z

DDR_A_D32 129 130 DDR_A_D36

DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
DQ33 DQ37 1 1
133 134
VSS29 VSS30
C665

C666
135 136 DDR_A_DM4
<6,9> DDR_A_DQS#4 DQS#4 DM4
137 138
B <6,9> DDR_A_DQS4 DQS4 VSS31 2 2 B
139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152
VSS36 DQS#5 DDR_A_DQS#5 <6,9>
DDR_A_DM5 153 154
DM5 DQS5 DDR_A_DQS5 <6,9>
155 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
169 VSS41 VSS42 170 DDR_A_DM6
<6,9> DDR_A_DQS#6 DQS#6 DM6
171 172
<6,9> DDR_A_DQS6 DQS6 VSS43
173 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186
VSS48 DQS#7 DDR_A_DQS#7 <6,9>
1 2 DDR_A_DM7 187 188
+3VS DM7 DQS7 DDR_A_DQS7 <6,9>
R84 4.7K_0402_5% 189 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198
SA0 EVENT# MA_EVENT_L <6,9>
199 200
+3VS VDDSPD SDA FCH_SDATA0 <9,24,29>
1 2 201 202
A SA1 SCL FCH_SCLK0 <9,24,29> A
1 203 204 +0.75VS
VTT1 VTT2
1

R449
C667 10K_0402_5% 205 206
2.2U_0603_10V6K C668 G1 G2
2

2 LCN_DAN06-K4806-0102
0.1U_0402_16V4Z
@
Check SMB address Security Classification Compal Secret Data
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_GRX_P[3..0] UV1A PCIE_CRX_GTX_P[3..0]

<5> PCIE_CTX_GRX_P[3..0] PCIE_CRX_GTX_P[3..0] <5>
PCIE_CTX_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
<5> PCIE_CTX_GRX_N[3..0] PCIE_CRX_GTX_N[3..0] <5>

D D

PCIE_CTX_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.1U_0402_16V7K 2 1 CV1 DIS@ PCIE_CRX_GTX_P0

PCIE_CTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 0.1U_0402_16V7K 2 1 CV2 DIS@ PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N

PCIE_CTX_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_16V7K 2 1 CV3 DIS@ PCIE_CRX_GTX_P1

PCIE_CTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 0.1U_0402_16V7K 2 1 CV4 DIS@ PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_16V7K 2 1 CV5 DIS@ PCIE_CRX_GTX_P2

PCIE_CTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 0.1U_0402_16V7K 2 1 CV6 DIS@ PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N

PCIE_CTX_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_16V7K 2 1 CV7 DIS@ PCIE_CRX_GTX_P3

PCIE_CTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 0.1U_0402_16V7K 2 1 CV8 DIS@ PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
C C
W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N

V30 W24
U31 PCIE_RX8P PCIE_TX8P W23
PCIE_RX8N PCIE_TX8N

U29 V27
T28 PCIE_RX9P PCIE_TX9P U26
PCIE_RX9N PCIE_TX9N

T30 U24
R31 PCIE_RX10P PCIE_TX10P U23
PCIE_RX10N PCIE_TX10N

R29 T26
P28 PCIE_RX11P PCIE_TX11P T27
PCIE_RX11N PCIE_TX11N

P30 T24
N31 PCIE_RX12P PCIE_TX12P T23
PCIE_RX12N PCIE_TX12N

N29 P27
M28 PCIE_RX13P PCIE_TX13P P26
PCIE_RX13N PCIE_TX13N

B M30 P24 B
L31 PCIE_RX14P PCIE_TX14P P23
PCIE_RX14N PCIE_TX14N

L29 M27
K30 PCIE_RX15P PCIE_TX15P N26
PCIE_RX15N PCIE_TX15N

CLOCK
AK30
<22> CLK_PCIE_VGA PCIE_REFCLKP
AK32
<22> CLK_PCIE_VGA# PCIE_REFCLKN

CALIBRATION
Y22 RV1 1 DIS@ 2 1.27K_0402_1%
PCIE_CALRP
RV133 1 DIS@ 2 10K_0402_5% N10 AA22 RV2 1 DIS@ 2 2K_0402_1% +1.0VS
PWRGOOD PCIE_CALRN

AL27
<22,29,30,32> APU_PCIE_RST# PERSTB

2160809024A11SEYMOU_FCBGA631
SEYMOURR1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

UV1B

AF2 VGA_HDMI_CLK+
TXCAP_DPA3P AF4 VGA_HDMI_CLK+ <21>
VGA_HDMI_CLK-
TXCAM_DPA3N VGA_HDMI_CLK- <21>
Need to check Y11
AE9 DVCLK AG3 VGA_HDMI_TX0+
DVCNTL_0 TX0P_DPA2P VGA_HDMI_TX0+ <21>
L9 AG5 VGA_HDMI_TX0-
DVCNTL_1 TX0M_DPA2N VGA_HDMI_TX0- <21>
N9 DVO DPA
DVCNTL_2 AH3 VGA_HDMI_TX1+
TX1P_DPA1P VGA_HDMI_TX1+ <21>
AE8 AH1 VGA_HDMI_TX1-
DVDATA_12 TX1M_DPA1N VGA_HDMI_TX1- <21>
AD9
AC10 DVDATA_11 AK3 VGA_HDMI_TX2+
D DVDATA_10 TX2P_DPA0P VGA_HDMI_TX2+ <21> D
AD7 AK1 VGA_HDMI_TX2-
AC8 DVDATA_9 TX2M_DPA0N VGA_HDMI_TX2- <21>
AC7 DVDATA_8 AK5
AB9 DVDATA_7 TXCBP_DPB3P AM3
AB8 DVDATA_6 TXCBM_DPB3N
AB7 DVDATA_5 AK6
TV15 AB4 DVDATA_4 TX3P_DPB2P AM5
AB2 DVDATA_3 DPB TX3M_DPB2N
Y8 DVDATA_2 AJ7
+1.8VS <18> VRAM_ID1 DVDATA_1 TX4P_DPB1P
Y7 AH6
<18> VRAM_ID0 DVDATA_0 TX4M_DPB1N
LV8
2 1 10U_0603_6.3V6M 0.1U_0402_16V4Z AK8
BLM18PG121SN1D_0603 1 TX5P_DPB0P AL7
1 1 TX5M_DPB0N
DIS@ DIS@ DIS@ DIS@
CV54 CV55 CV53
+DPC_VDD18 W6 DPC
2 2 2 V6 DPC_VDD18#3
1U_0402_6.3V4Z DP_VSSR#13 V4
+DPC_VDD18 AC6 TXCCP_DPC3P U5
+1.0VS AC5 DPC_VDD18#1 TXCCM_DPC3N
LV10
DIS@ DPC_VDD18#2 W3
2 1 0.1U_0402_16V4Z +DPC_VDD10 AA5 TX0P_DPC2P V2
BLM18PG121SN1D_0603 AA6 DPC_VDD10#1 TX0M_DPC2N
1 1 1 DPC_VDD10#2
DIS@ DIS@ DIS@ Y4
10U_0603_6.3V6M CV61 CV60 CV59 TX1P_DPC1P W5
TX1M_DPC1N
2 2 2 U1 AA3
1U_0402_6.3V4Z W1 DP_VSSR#14 TX2P_DPC0P Y2
U3 DP_VSSR#15 TX2M_DPC0N RV16
Y6 DP_VSSR#16 J8 1 2
+3VS AA1 DP_VSSR#17 DPC_CALR DIS@ 150_0402_1%
DP_VSSR#18

2 1 VGA_EDID_CLK RB/GB/BB: Grounded right

DIS@ RV139 4.7K_0402_5%
2 1 VGA_EDID_DATA I2C away. MUST not be connected
DIS@ RV140 4.7K_0402_5% LCD
VGA_EDID_CLK R1
to AVSSQ.
<19> VGA_EDID_CLK SCL
<19> VGA_EDID_DATA VGA_EDID_DATA R3
+3VS SDA
C AM26 VGA_CRT_R VGA_CRT_R 1 2 DIS@ C
GENERAL PURPOSE I/O R AK26 VGA_CRT_R <20>
RV11 150_0402_1%
10K_0402_5%2 1 RV30 VGA_PWRSEL0 U6 RB VGA_CRT_G 1 2 DIS@
<18> GPU_GPIO0 GPIO_0
U10 AL25 VGA_CRT_G RV12 150_0402_1%
<18> GPU_GPIO1 GPIO_1 G VGA_CRT_G <20>
10K_0402_5%2 1 RV131 VGA_PWRSEL1 T10 AJ25 VGA_CRT_B 1 2 DIS@
<18> GPU_GPIO2
GPU_SMB_DA2 U8 GPIO_2 GB CRT RV13 150_0402_1%
<18> GPU_SMB_DA2 GPIO_3_SMBDATA
DIS@10K_0402_5%2 1 RV32 THERM#_VGA GPU_SMB_CK2 U7 AH24 VGA_CRT_B
<18> GPU_SMB_CK2 GPIO_4_SMBCLK B VGA_CRT_B <20>
T9 AG25
@ 10K_0402_5%2 1 RV33 CLKREQ_PEG#_R T8 GPIO_5_AC_BATT DAC1 BB
VGA_ENBKL T7 GPIO_6 AH26
<19> VGA_ENBKL GPIO_7_BLON HSYNC VGA_CRT_HSYNC <18,20>
P10 AJ27
<18> SOUT_GPIO8 P4 GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC <18,20>
<18> SIN_GPIO9 GPIO_9_ROMSI
@ 10K_0402_5%2 1 RV35 GENERIC_C P2 BLM18PG121SN1D_0603
N6 GPIO_10_ROMSCK AD22 RESET 1 2 DIS@ +AVDD_VGA 70mA 2 1 +1.8VS
<18> GPU_GPIO11 GPIO_11 RSET
@ 10K_0402_5%2 1 RV31 GPU_SMB_DA2 N5 RV18 499_0402_1% 1 1 1 LV1 DIS@
<18> GPU_GPIO12 GPIO_12
N3 AG24 +AVDD_VGA DIS@ DIS@ DIS@
<18> GPU_GPIO13 GPIO_13 AVDD
@ 10K_0402_5%2 1 RV142 GPU_SMB_CK2 TV11 Y9 AE22 CV33 CV35 CV34
VGA_PWRSEL0 N1 GPIO_14_HPD2 AVSSQ 1U_0402_6.3V4Z 10U_0603_6.3V6M
<45> VGA_PWRSEL0 GPIO_15_PWRCNTL_0 2 2 2
M4 AE23 +VDD1DI
DIS@ 10K_0402_5%1 2 RV17 VGA_ENBKL THERM#_VGA R6 GPIO_16 VDD1DI AD23 0.1U_0402_16V4Z
<18> THERM#_VGA GPIO_17_THERMAL_INT VSS1DI
W10
M2 GPIO_18_HPD3
VGA_PWRSEL1 P8 GPIO_19_CTF AM12
<45> VGA_PWRSEL1 GPIO_20_PWRCNTL_1 NC/R2
P7 SEYMOUR/PARK AK12
N8 GPIO_21_BB_EN NC/R2B
<18> ROMSE_GPIO22 GPIO_22_ROMCSB
1 @ 2 CLKREQ_PEG#_R N7 AL11
<24> CLKREQ_PEG# GPIO_23_CLKREQB NC/G2 AJ11
RV27 0_0402_5%
TV14 L6 NC/G2B
TV9 L5 JTAG_TRSTB AK10
TV12 L3 JTAG_TDI NC/B2 AL9
TV13 L1 JTAG_TCK NC/B2B
TV10 K4 JTAG_TMS
2 DIS@ 1 K7 JTAG_TDO AH12
RV19 10K_0402_5% TV18 AF24 TESTEN SWAPLOCKB/C AM10
TESTEN_LEGACY NC/Y AJ9 BLM18PG121SN1D_0603
NC/COMP +VDD1DI 45mA 2 1 +1.8VS
AB13 1 1 1 LV2 DIS@
W8 GENERICA AL13 GENLK_CLK DIS@ DIS@ DIS@
GENERICB GENLK_CLK GENLK_CLK <18>
GENERIC_C W9 AJ13 CV36 CV37 CV38
W7 GENERICC GENLK_V2SYNC 1U_0402_6.3V4Z 10U_0603_6.3V6M
B AD10 GENERICD 2 2 2 B
0_0402_5% GENERICE_HPD4 AD19 0.1U_0402_16V4Z
RV143 1 2 AC14 NC/VDD2IDI AC19
+1.8VS <21> VGA_HDMI_HPD AB16 HPD1 NC/VSS2IDI
DIS@ PX_EN
1

RV20 AE20
499_0402_1% NC/A2VDD
DIS@ AE17
NC/A2VDDQ
AE19
2

TSVSSQ/A2VSSQ
+VGA_VREF AC16
VREFG AG13
SWAPLOCKA/R2SET
1

1
+3VS
RV21 CV49 DIS@
BLM18PG121SN1D_0603 249_0402_1% 0.1U_0402_16V4Z DDC/AUX AE6 VGA_CRT_CLK VGA_CRT_CLK <20> VGA_CRT_CLK RV134 2 1 4.7K_0402_5%
DIS@ 2 DIS@ PLL/CLOCK DDC1CLK AE5 VGA_CRT_DATA VGA_CRT_DATA <20> CRT
2

2 1 0.1U_0402_16V4Z +DPLL_PVDD +DPLL_PVDD AF14 DDC1DATA VGA_CRT_DATA RV135 2 1 4.7K_0402_5%

+1.8VS
LV3 1 1 1 AE14 DPLL_PVDD 75mA AD2
DIS@ CV42 DPLL_PVSS AUX1P AD4
AUX1N Follow HB uses DDC1 for CRT DIS@
DIS@ CV41 1U_0402_6.3V4Z Check voltage level
CV40 DIS@ DIS@ +DPLL_VDDC AD14 AC11 VGA_HDMI_CLK +3VS
2 2 2 DPLL_VDDC 125mA DDC2CLK AC13 VGA_HDMI_DATA
VGA_HDMI_CLK <21>
VGA_HDMI_DATA <21>
HDMI DIS@
10U_0603_6.3V6M DDC2DATA VGA_HDMI_CLK RV144 2 1 4.7K_0402_5%
1 DIS@ 2 XTALIN AM28 AD13
<29> VGA_X1 XTALIN AUX2P
RV28 0_0402_5% XTALOUT AK28 AD11 VGA_HDMI_DATA RV145 2 1 4.7K_0402_5%
XTALOUT AUX2N
AC22 AD20 DIS@
AB22 XO_IN DDCCLK_AUX3P AC20
BLM18PG121SN1D_0603 XO_IN2 DDCDATA_AUX3N
+1.0VS
2 1 0.1U_0402_16V4Z +DPLL_VDDC AE16
LV5 DDCCLK_AUX5P AD16
1 1 1 DDCDATA_AUX5N
DIS@ CV43 DIS@
DIS@ CV44 CV45 AC1
DIS@ T4 THERMAL DDC6CLK AC3
2 2 2 1U_0402_6.3V4Z <18> GPU_THERMAL_D+ T2 DPLUS DDC6DATA
<18> GPU_THERMAL_D- DMINUS
10U_0603_6.3V6M

BLM18PG121SN1D_0603 R5
A 2 1 0.1U_0402_16V4Z +TSVDD AD17 TS_FDO A
+1.8VS TSVDD
LV7 1 1 1 AC17
DIS@ DIS@ CV52 TSVSS
DIS@ CV51 1U_0402_6.3V4Z 20mA
RV97
@ CV50 DIS@
XTALOUT XTALIN 2 2 2 2160809024A11SEYMOU_FCBGA631
10U_0603_6.3V6M SEYMOURR1@
1M_0402_5%
YV1 @
2 1

27MHZ_16PF_X5H027000FG1H

@ CV94 CV103 @
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/05/18 2013/10/05

www.vinafix.vn
Issued Date Deciphered Date Title
18P_0402_50V8J 18P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 12 of 47
5 4 3 2 1
 5 4 3 2 1

UV1F

LVDS CONTROL AB11

VARY_BL VGA_PWM <19>
AB12
DIGON VGA_ENVDD <19>

D D

AH20 VGA_TZCLK+ <19>

TXCLK_UP_DPF3P AJ19
TXCLK_UN_DPF3N VGA_TZCLK- <19>
AL21 VGA_TZOUT0+ <19>
TXOUT_U0P_DPF2P AK20
TXOUT_U0N_DPF2N VGA_TZOUT0- <19>
UV1G
AH22 VGA_TZOUT1+ <19>
TXOUT_U1P_DPF1P AJ21 +1.8VS +1.8VS_DPEF DP E/F POWER DP A/B POWER +1.8VS_DPAB
TXOUT_U1N_DPF1N VGA_TZOUT1- <19>
LV15
AL23 VGA_TZOUT2+ <19> 2 1 10U_0603_6.3V6M 0.1U_0402_16V4Z AG15 220mA 130mA AE11
TXOUT_U2P_DPF0P AK22 BLM18PG121SN1D_0603 1 AG16 DPEF_VDD18#1 DPAB_VDD18#1 AF11
TXOUT_U2N_DPF0N VGA_TZOUT2- <19> 1 1 DPEF_VDD18#2 DPAB_VDD18#2
DIS@
AK24 CV89 CV99 CV73 +1.0VS_DPEF +1.0VS_DPAB
TXOUT_U3P AJ23 DIS@ DIS@ DIS@
TXOUT_U3N 2 2 2 AG20 120mA 110mA AF6
1U_0402_6.3V4Z AG21 DPEF_VDD10#1 DPAB_VDD10#1 AF7
LVTMDP +1.0VS DPEF_VDD10#2 DPAB_VDD10#2
LV32
AL15 VGA_TXCLK+ <19> 2 1 10U_0603_6.3V6M 0.1U_0402_16V4Z AG14 AE1
TXCLK_LP_DPE3P AK14 BLM18PG121SN1D_0603 1 AH14 DP_VSSR#19 DP_VSSR#1 AE3
TXCLK_LN_DPE3N VGA_TXCLK- <19> 1 1 DP_VSSR#20 DP_VSSR#2
DIS@ AM14 AG1
AH16 CV165 CV166 CV164 AM16 DP_VSSR#21 DP_VSSR#3 AG6
TXOUT_L0P_DPE2P VGA_TXOUT0+ <19> DP_VSSR#22 DP_VSSR#4
AJ15 VGA_TXOUT0- <19> DIS@ DIS@ DIS@ AM18 AH5
TXOUT_L0N_DPE2N 2 2 2 DP_VSSR#23 DP_VSSR#5
AL17 VGA_TXOUT1+ <19> 1U_0402_6.3V4Z
TXOUT_L1P_DPE1P AK16
C TXOUT_L1N_DPE1N VGA_TXOUT1- <19>
+1.8VS_DPEF AF16 200mA 130mA AE13 +1.8VS_DPAB
C

AH18 AG17 DPEF_VDD18#3 DPAB_VDD18#3 AF13

TXOUT_L2P_DPE0P VGA_TXOUT2+ <19> DPEF_VDD18#4 DPAB_VDD18#4
AJ17 VGA_TXOUT2- <19>
TXOUT_L2N_DPE0N
AL19
TXOUT_L3P AK18 +1.0VS_DPEF AF22 120mA 110mA AF8 +1.0VS_DPAB
TXOUT_L3N AG22 DPEF_VDD10#3 DPAB_VDD10#3 AF9
DPEF_VDD10#4 DPAB_VDD10#4

AF23 AF10
2160809024A11SEYMOU_FCBGA631 AG23 DP_VSSR#24 DP_VSSR#6 AG9
SEYMOURR1@ AM20 DP_VSSR#25 DP_VSSR#7 AH8
AM22 DP_VSSR#26 DP_VSSR#8 AM6
AM24 DP_VSSR#27 DP_VSSR#9 AM8
DP_VSSR#28 DP_VSSR#10

RV14 RV15
1 2 AF17 AE10 1 2
150_0402_1% DPEF_CALR DPAB_CALR 150_0402_1%
DIS@ DIS@

+1.8VS_DPEF AG18 20mA DP PLL POWER 20mA AG8 +1.8VS_DPAB

AF19 DPEF_VDD18#5 DPAB_VDD18#5 AG7
DP_VSSR#29 DP_VSSR#11

B
+1.8VS_DPEF AG19 20mA 20mA AG10 +1.8VS_DPAB
B

AF20 DPEF_VDD18#6 DPAB_VDD18#6 AG11

+1.8VS DP_VSSR#30 DP_VSSR#12
LV16
2 1 10U_0603_6.3V6M +1.8VS_DPAB
BLM18PG121SN1D_0603 1 1 1 2160809024A11SEYMOU_FCBGA631
DIS@ SEYMOURR1@
CV92 CV106 CV74
DIS@ DIS@ 0.1U_0402_16V4Z
2 2 2 DIS@
1U_0402_6.3V4Z
+1.0VS
LV33
2 1 10U_0603_6.3V6M +1.0VS_DPAB
BLM18PG121SN1D_0603 1 1 1
DIS@
CV168 CV169 CV167
DIS@ DIS@ 0.1U_0402_16V4Z
2 2 2 DIS@
1U_0402_6.3V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 13 of 47
5 4 3 2 1

www.vinafix.vn
 5 4 3 2 1

UV1D

+1.5VS MEM I/O +1.8VS

PCIE 500mA LV21
1 10U_0603_6.3V6M 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1.2A H13 AB23 +PCIE_VDDR 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 2
H16 VDDR1#1 PCIE_VDDR#1 AC23
2 2 2 1 1 1 2 2 2 2 2 VDDR1#2 PCIE_VDDR#2 2 2 2 2 2 2 BLM18PG121SN1D_0603
+ H19 AD24 DIS@
CV78 CV91 CV87 CV83 CV275 CV274 CV273 CV102 CV98 CV97 CV96 CV95 J10 VDDR1#3 PCIE_VDDR#3 AE24 CV101 CV105 CV82 CV86 CV90 CV77
330U_2.5V_M DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ J23 VDDR1#4 PCIE_VDDR#4 AE25 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ 2 1 1 1 2 2 2 1 1 1 1 1 J24 VDDR1#5 PCIE_VDDR#5 AE26 1 1 1 1 1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z J9 VDDR1#6 PCIE_VDDR#6 AF25 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M
K10 VDDR1#7 PCIE_VDDR#7 AG26
K23 VDDR1#8 PCIE_VDDR#8 +1.0VS
K24 VDDR1#9
D
K9 VDDR1#10 L23 2A 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
D

L11 VDDR1#11 PCIE_VDDC#1 L24

VDDR1#12 PCIE_VDDC#2 2 2 2 2 2 2 2 2
L12 L25
L13 VDDR1#13 PCIE_VDDC#3 L26 CV104 CV108 CV111 CV112 CV113 CV115 CV118 CV100
L20 VDDR1#14 PCIE_VDDC#4 M22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
L21 VDDR1#15 PCIE_VDDC#5 N22 1 1 1 1 1 1 1 1
L22 VDDR1#16 PCIE_VDDC#6 N23 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M
VDDR1#17 PCIE_VDDC#7 N24
PCIE_VDDC#8 R22 +VGA_CORE
PCIE_VDDC#9 T22
LEVEL PCIE_VDDC#10 U22
LV22 17mA TRANSLATION PCIE_VDDC#11 V22
+1.8VS PCIE_VDDC#12
2 1 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z +VDD_CT AA20
BLM18PG121SN1D_0603 AA21 VDD_CT#1
DIS@
2 2 2 2 2
AB20 VDD_CT#2 AA15 13A
CV119 CV123 CV127 CV131 CV135 AB21 VDD_CT#3 CORE VDDC#1 N15
DIS@ DIS@ DIS@ DIS@ DIS@ VDD_CT#4 VDDC#2 N17
1 1 1 1 1 VDDC#3 R13
I/O VDDC#4 R16
1U_0402_6.3V4Z 0.1U_0402_16V4Z AA17 VDDC#5 R18
AA18 VDDR3#1 VDDC#6 Y21
AB17 VDDR3#2 VDDC#7 T12
1U_0402_6.3V4Z 1U_0402_6.3V4Z AB18 VDDR3#3 VDDC#8 T15
+3VS VDDR3#4 VDDC#9
2 2 2 2 T17
V12 VDDC#10 T20
CV162 CV158 CV152 CV148 Y12 VDDR4#1 VDDC#11 U13
DIS@ DIS@ DIS@ DIS@ +VDDR4 U12 VDDR4#2 VDDC#12 U16
1 1 1 1 VDDR4#3 VDDC#13 U18
1U_0402_6.3V4Z 10U_0603_6.3V6M AA11 VDDC#14 V21
NC#1 VDDC#15

POWER
AA12 V15
C NC#2 VDDC#16 V17 C
V11 VDDC#17 V20
LV24 U11 NC#3 VDDC#18 Y13
2 1 0.1U_0402_16V4Z NC#4 VDDC#19 Y16
+1.8VS VDDC#20
BLM18PG121SN1D_0603 1 1 Y18
DIS@ CV172 CV173 VDDC#21 M11
DIS@ NC M12
DIS@ 1U_0402_6.3V4Z MEM CLK NC
2 2 L17
NC_VDDRHA
L16
NC_VSSRHA

PLL
+PCIE_VDDR AM30
PCIE_VDDR R21
BIF_VDDC#1 U21
75mA BIF_VDDC#2
+MPV18 L8
NC_MPV18

ISOLATED
CORE I/O M13
+SPV18 75mA H7 VDDCI#1 M15
SPV18 VDDCI#2 M16
VDDCI#3 M17
VDDCI#4 M18
LV28 VDDCI#5 M20
+1.0VS 2 1 1U_0402_6.3V4Z +SPV10 120mA H8 VDDCI#6 M21
BLM18PG121SN1D_0603 SPV10 VDDCI#7 N20
1 1 2 VDDCI#8
DIS@ CV189 CV190 CV191 J7
B DIS@ SPVSS B
DIS@ DIS@ +VGA_CORE
2 2 1
10U_0603_6.3V6M 0.1U_0402_16V4Z 2160809024A11SEYMOU_FCBGA631
LV30 SEYMOURR1@
+1.8VS 2 1 10U_0603_6.3V6M 0.1U_0402_16V4Z +MPV18
BLM18PG121SN1D_0603 1 1 1 1 1
DIS@ 1U_0402_6.3V4Z
CV276 CV309 CV303 CV308 CV302
DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2
0.1U_0402_16V4Z 1U_0402_6.3V4Z

LV31
+1.8VS 2 1 0.1U_0402_16V4Z +SPV18
BLM18PG121SN1D_0603 1 1 1
DIS@ 1U_0402_6.3V4Z
CV277 CV305 CV306
DIS@ DIS@ DIS@
2 2 2
10U_0603_6.3V6M

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

UV1E

AA27 A3
AB24 PCIE_VSS#1 GND#1 A30
AB32 PCIE_VSS#2 GND#2 AA13
AC24 PCIE_VSS#3 GND#3 AA16
AC26 PCIE_VSS#4 GND#4 AB10
AC27 PCIE_VSS#5 GND#5 AB15
AD25 PCIE_VSS#6 GND#6 AB6
AD32 PCIE_VSS#7 GND#7 AC9
AE27 PCIE_VSS#8 GND#8 AD6
AF32 PCIE_VSS#9 GND#9 AD8
D AG27 PCIE_VSS#10 GND#10 AE7 D
AH32 PCIE_VSS#11 GND#11 AG12
K28 PCIE_VSS#12 GND#12 AH10
K32 PCIE_VSS#13 GND#13 AH28
L27 PCIE_VSS#14 GND#14 B10
M32 PCIE_VSS#15 GND#15 B12
N25 PCIE_VSS#16 GND#16 B14
N27 PCIE_VSS#17 GND#17 B16
P25 PCIE_VSS#18 GND#18 B18
P32 PCIE_VSS#19 GND#19 B20
R27 PCIE_VSS#20 GND#20 B22
T25 PCIE_VSS#21 GND#21 B24
T32 PCIE_VSS#22 GND#22 B26
U25 PCIE_VSS#23 GND#23 B6
U27 PCIE_VSS#24 GND#24 B8
V32 PCIE_VSS#25 GND#25 C1
W25 PCIE_VSS#26 GND#26 C32
W26 PCIE_VSS#27 GND#27 E28
W27 PCIE_VSS#28 GND#28 F10
Y25 PCIE_VSS#29 GND#29 F12
Y32 PCIE_VSS#30 GND#30 F14
PCIE_VSS#31 GND#31 F16
GND#32 F18
GND#33 F2
GND#34 F20
M6 GND#35 F22
N11 GND#56 GND#36 F24
N12 GND#57 GND#37 F26
N13 GND#58 GND#38 F6
N16 GND#59 GND#39 F8
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
C P6 G31 C
P9 GND#63 GND#43 G8
R12 GND#64 GND#44 H14
R15 GND#65 GND#45 H17
R17 GND#66 GND#46 H2
R20 GND#67 GND#47 H20
T13 GND#68 GND#48 H6
T16 GND#69 GND#49 J27
T18 GND#70 GND#50 J31
T21 GND#71 GND#51 K11
T6 GND#72 GND#52 K2
U15 GND#73 GND#53 K22
U17 GND#74 GND#54 K6
U20 GND#75 GND#55
U9 GND#76
V13 GND#77
V16 GND#78
V18 GND#79
Y10 GND#80
Y15 GND#81
Y17 GND#82 A32
Y20 GND#83 VSS_MECH#1 AM1
R11 GND#84 VSS_MECH#2 AM32
T11 GND#85 VSS_MECH#3
GND#86

2160809024A11SEYMOU_FCBGA631

SEYMOURR1@
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 15 of 47
5 4 3 2 1
 5 4 3 2 1

UV1C

D GDDR5/DDR3 GDDR5/DDR3 D
MDA[0..63] MDA0 K27 K17 MAA0 MAA[13..0]
<17> MDA[0..63] DQA0_0 MAA0_0/MAA_0 MAA[13..0] <17>
MDA1 J29 J20 MAA1
MDA2 H30 DQA0_1 MAA0_1/MAA_1 H23 MAA2
MDA3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA3
MDA4 G29 DQA0_3 MAA0_3/MAA_3 G24 MAA4
MDA5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA5
MDA6 F32 DQA0_5 MAA0_5/MAA_5 J19 MAA6

MEMORY INTERFACE
MDA7 F30 DQA0_6 MAA0_6/MAA0_6 K19 MAA7
MDA8 C30 DQA0_7 MAA0_7/MAA0_7 J14 MAA8
MDA9 F27 DQA0_8 MAA1_0/MAA_8 K14 MAA9
MDA10 A28 DQA0_9 MAA1_1/MAA_9 J11 MAA10
MDA11 C28 DQA0_10 MAA1_2/MAA_10 J13 MAA11
MDA12 E27 DQA0_11 MAA1_3/MAA_11 H11 MAA12
MDA13 G26 DQA0_12 MAA1_4/MAA_12 G11 A_BA2 A_BA[2..0]
DQA0_13 MAA1_5/MAA_BA2 A_BA[2..0] <17>
MDA14 D26 J16 A_BA0
MDA15 F25 DQA0_14 MAA1_6/MAA_BA0 L15 A_BA1
MDA16 A25 DQA0_15 MAA1_7/MAA_BA1
MDA17 C25 DQA0_16 E32 DQMA#0 DQMA#[7..0]
DQA0_17 WCKA0_0/DQMA0_0 DQMA#[7..0] <17>
MDA18 E25 E30 DQMA#1
MDA19 D24 DQA0_18 WCKA0B_0/DQMA0_1 A21 DQMA#2
MDA20 E23 DQA0_19 WCKA0_1/DQMA0_2 C21 DQMA#3
MDA21 F23 DQA0_20 WCKA0B_1/DQMA0_3 E13 DQMA#4
MDA22 D22 DQA0_21 WCKA1_0/DQMA1_0 D12 DQMA#5
MDA23 F21 DQA0_22 WCKA1B_0/DQMA1_1 E3 DQMA#6
MDA24 E21 DQA0_23 WCKA1_1/DQMA1_2 F4 DQMA#7
MDA25 D20 DQA0_24 WCKA1B_1/DQMA1_3
MDA26 F19 DQA0_25 H28 QSA0 QSA[7..0]
DQA0_26 EDCA0_0/QSA0_0 QSA[7..0] <17>
MDA27 A19 C27 QSA1
MDA28 D18 DQA0_27 EDCA0_1/QSA0_1 A23 QSA2
MDA29 F17 DQA0_28 EDCA0_2/QSA0_2 E19 QSA3
MDA30 A17 DQA0_29 EDCA0_3/QSA0_3 E15 QSA4
C MDA31 C17 DQA0_30 EDCA1_0/QSA1_0 D10 QSA5 C
MDA32 E17 DQA0_31 EDCA1_1/QSA1_1 D6 QSA6
MDA33 D16 DQA1_0 EDCA1_2/QSA1_2 G5 QSA7
MDA34 F15 DQA1_1 EDCA1_3/QSA2_3
MDA35 A15 DQA1_2 H27 QSA#0 QSA#[7..0]
DQA1_3 DDBIA0_0/QSA0_0B QSA#[7..0] <17>
MDA36 D14 A27 QSA#1
MDA37 F13 DQA1_4 DDBIA0_1/QSA0_1B C23 QSA#2
MDA38 A13 DQA1_5 DDBIA0_2/QSA0_2B C19 QSA#3
MDA39 C13 DQA1_6 DDBIA0_3/QSA0_3B C15 QSA#4
MDA40 E11 DQA1_7 DDBIA1_0/QSA1_0B E9 QSA#5
MDA41 A11 DQA1_8 DDBIA1_1/QSA1_1B C5 QSA#6
MDA42 C11 DQA1_9 DDBIA1_2/QSA1_2B H4 QSA#7
MDA43 F11 DQA1_10 DDBIA1_3/QSA1_3B
MDA44 A9 DQA1_11 L18
DQA1_12 ADBIA0/ODTA0 ODTA0 <17>
MDA45 C9 K16
DQA1_13 ADBIA1/ODTA1 ODTA1 <17>
MDA46 F9
Close to pin K26 MDA47 D8 DQA1_14
DQA1_15 CLKA0
H26
CLKA0 <17>
+1.5VS MDA48 E7 H25
DQA1_16 CLKA0B CLKA0# <17>
MDA49 A7
MDA50 C7 DQA1_17 G9
DQA1_18 CLKA1 CLKA1 <17>
1

MDA51 F7 H9
DQA1_19 CLKA1B CLKA1# <17>
RV41 MDA52 A5
40.2_0402_1% MDA53 E5 DQA1_20 G22
DQA1_21 RASA0B RASA0# <17>
DIS@ MDA54 C3 G17
DQA1_22 RASA1B RASA1# <17>
MDA55 E1
2

MDA56 G7 DQA1_23 G19

DQA1_24 CASA0B CASA0# <17>
+MVREFDA MDA57 G6 G16
DQA1_25 CASA1B CASA1# <17>
MDA58 G1
MDA59 G3 DQA1_26 H22
1 DQA1_27 CSA0B_0 CSA0#_0 <17>
1

MDA60 J6 J22
RV43 CV202 MDA61 J1 DQA1_28 CSA0B_1
100_0402_1% 0.1U_0402_16V4Z MDA62 J3 DQA1_29 G13
B 2 DIS@ DQA1_30 CSA1B_0 CSA1#_0 <17> B
DIS@ MDA63 J5 K13
DQA1_31 CSA1B_1
2

+1.5VS +MVREFDA K26 K20

MVREFDA CKEA0 CKEA0 <17>
+MVREFSA J26 J17
MVREFSA CKEA1 CKEA1 <17>
DIS@
RV48 1 2 240_0402_1% J25 G25
MEM_CALRN0 WEA0B WEA0# <17>
RV52 1 2 240_0402_1% K25 H10
MEM_CALRP0 WEA1B WEA1# <17>
DIS@
Close to pin J26
+1.5VS DRAM_RST L10 GDDR5 / DDR3
DRAM_RST G20
MAA0_8/MAA_13 MAA13 <17>
K8 G14
CLKTESTA MAA1_8/RSVD
1

L7
RV45 CLKTESTB
40.2_0402_1%
DIS@ @ @ 2160809024A11SEYMOU_FCBGA631
RV57 2 1 51_0402_5% CV320 1 2 0.1U_0402_16V4Z SEYMOURR1@
2

+MVREFSA 2 1 1 2
RV58 @ 51_0402_5% CV321 @ 0.1U_0402_16V4Z
1

1
RV47 CV204 Debug Only, for clock observation
100_0402_1% 0.1U_0402_16V4Z
DIS@ DIS@ As short as possible
2
2

DIS@ RV53
DRAM_RST 1 2 1 2
A DRAM_RST# <17> A
RV86 10_0402_5% 51_0402_5%
DIS@
1

1
RV129 CV62
4.99K_0402_1% 120P_0402_50V8
DIS@ DIS@
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Place all these components close Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
to GPU (Within 25mm) and
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
keep all component close to AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
4019K4 B
each other (within5mm) except Rser2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 16 of 47
5 4 3 2 1
 5 4 3 2 1

MDA[0..63] UV2 UV3

<16> MDA[0..63]
UV4 UV5
MAA[13..0] +VREFC_A1 M8 E3 MDA4 +VREFC_A2 M8 E3 MDA10
<16> MAA[13..0] VREFCA DQL0 VREFCA DQL0
+VREFD_A1 H1 F7 MDA2 +VREFD_A2 H1 F7 MDA13 +VREFC_A3 M8 E3 MDA40 +VREFC_A4 M8 E3 MDA63
DQMA#[7..0] VREFDQ DQL1 F2 MDA1 VREFDQ DQL1 F2 MDA8 +VREFD_A3 H1 VREFCA DQL0 F7 MDA45 +VREFD_A4 H1 VREFCA DQL0 F7 MDA58
<16> DQMA#[7..0] DQL2 DQL2 VREFDQ DQL1 VREFDQ DQL1
MAA0 N3 F8 MDA3 MAA0 N3 F8 MDA15 F2 MDA41 F2 MDA60
QSA[7..0] MAA1 P7 A0 DQL3 H3 MDA5 MAA1 P7 A0 DQL3 H3 MDA11 MAA0 N3 DQL2 F8 MDA43 MAA0 N3 DQL2 F8 MDA59
<16> QSA[7..0] A1 DQL4 Group0 A1 DQL4 Group1 A0 DQL3 A0 DQL3
MAA2 P3 H8 MDA0 MAA2 P3 H8 MDA14 MAA1 P7 H3 MDA42 Group5 MAA1 P7 H3 MDA61 Group7
QSA#[7..0] MAA3 N2 A2 DQL5 G2 MDA7 MAA3 N2 A2 DQL5 G2 MDA9 MAA2 P3 A1 DQL4 H8 MDA46 MAA2 P3 A1 DQL4 H8 MDA56
<16> QSA#[7..0] A3 DQL6 A3 DQL6 A2 DQL5 A2 DQL5
MAA4 P8 H7 MDA6 MAA4 P8 H7 MDA12 MAA3 N2 G2 MDA44 MAA3 N2 G2 MDA62
A_BA[2..0] MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA4 P8 A3 DQL6 H7 MDA47 MAA4 P8 A3 DQL6 H7 MDA57
<16> A_BA[2..0] A5 A5 A4 DQL7 A4 DQL7
MAA6 R8 MAA6 R8 MAA5 P2 MAA5 P2
MAA7 R2 A6 D7 MDA18 MAA7 R2 A6 D7 MDA28 MAA6 R8 A5 MAA6 R8 A5
MAA8 T8 A7 DQU0 C3 MDA19 MAA8 T8 A7 DQU0 C3 MDA26 MAA7 R2 A6 D7 MDA34 MAA7 R2 A6 D7 MDA48
D MAA9 R3 A8 DQU1 C8 MDA21 MAA9 R3 A8 DQU1 C8 MDA29 MAA8 T8 A7 DQU0 C3 MDA32 MAA8 T8 A7 DQU0 C3 MDA52 D
MAA10 L7 A9 DQU2 C2 MDA22 MAA10 L7 A9 DQU2 C2 MDA27 MAA9 R3 A8 DQU1 C8 MDA38 MAA9 R3 A8 DQU1 C8 MDA51
MAA11 R7 A10/AP DQU3 A7 MDA20 MAA11 R7 A10/AP DQU3 A7 MDA30 MAA10 L7 A9 DQU2 C2 MDA35 MAA10 L7 A9 DQU2 C2 MDA54
A11 DQU4 Group2 A11 DQU4 Group3 A10/AP DQU3 A10/AP DQU3
MAA12 N7 A2 MDA16 MAA12 N7 A2 MDA24 MAA11 R7 A7 MDA37 Group4 MAA11 R7 A7 MDA50 Group6
MAA13 T3 A12 DQU5 B8 MDA17 MAA13 T3 A12 DQU5 B8 MDA31 MAA12 N7 A11 DQU4 A2 MDA36 MAA12 N7 A11 DQU4 A2 MDA55
T7 A13 DQU6 A3 MDA23 T7 A13 DQU6 A3 MDA25 MAA13 T3 A12 DQU5 B8 MDA39 MAA13 T3 A12 DQU5 B8 MDA49
M7 A14 DQU7 M7 A14 DQU7 T7 A13 DQU6 A3 MDA33 T7 A13 DQU6 A3 MDA53
A15/BA3 +1.5VS A15/BA3 M7 A14 DQU7 M7 A14 DQU7
+1.5VS A15/BA3 +1.5VS A15/BA3 +1.5VS
A_BA0 M2 B2 A_BA0 M2 B2
A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9 A_BA0 M2 B2 A_BA0 M2 B2
A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9
BA2 VDD K2 BA2 VDD K2 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7
VDD K8 VDD K8 BA2 VDD K2 BA2 VDD K2
VDD N1 VDD N1 VDD K8 VDD K8
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9 VDD N1 VDD N1
<16> CLKA0 CK VDD CK VDD VDD VDD
CLKA0# K7 R1 CLKA0# K7 R1 CLKA1 J7 N9 CLKA1 J7 N9
<16> CLKA0# CK VDD CK VDD <16> CLKA1 CK VDD CK VDD
CKEA0 K9 R9 CKEA0 K9 R9 CLKA1# K7 R1 CLKA1# K7 R1
<16> CKEA0 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD <16> CLKA1# CK VDD CK VDD
CKEA1 K9 R9 CKEA1 K9 R9
+1.5VS <16> CKEA1 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS
ODTA0 K1 A1 ODTA0 K1 A1
<16> ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CSA0#_0 L2 A8 CSA0#_0 L2 A8 ODTA1 K1 A1 ODTA1 K1 A1
<16> CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ <16> ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
RASA0# J3 C1 RASA0# J3 C1 CSA1#_0 L2 A8 CSA1#_0 L2 A8
<16> RASA0# RAS VDDQ RAS VDDQ <16> CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
CASA0# K3 C9 CASA0# K3 C9 RASA1# J3 C1 RASA1# J3 C1
<16> CASA0# CAS VDDQ CAS VDDQ <16> RASA1# RAS VDDQ RAS VDDQ
WEA0# L3 D2 WEA0# L3 D2 CASA1# K3 C9 CASA1# K3 C9
<16> WEA0# WE VDDQ WE VDDQ <16> CASA1# CAS VDDQ CAS VDDQ
E9 E9 WEA1# L3 D2 WEA1# L3 D2
VDDQ VDDQ <16> WEA1# WE VDDQ WE VDDQ
F1 F1 E9 E9
QSA0 F3 VDDQ H2 QSA1 F3 VDDQ H2 VDDQ F1 VDDQ F1
QSA2 C7 DQSL VDDQ H9 QSA3 C7 DQSL VDDQ H9 QSA5 F3 VDDQ H2 QSA7 F3 VDDQ H2
DQSU VDDQ DQSU VDDQ QSA4 C7 DQSL VDDQ H9 QSA6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
DQMA#0 E7 A9 DQMA#1 E7 A9
C DQMA#2 D3 DML VSS B3 DQMA#3 D3 DML VSS B3 DQMA#5 E7 A9 DQMA#7 E7 A9 C
DMU VSS E1 DMU VSS E1 DQMA#4 D3 DML VSS B3 DQMA#6 D3 DML VSS B3
VSS G8 VSS G8 DMU VSS E1 DMU VSS E1
QSA#0 G3 VSS J2 QSA#1 G3 VSS J2 VSS G8 VSS G8
QSA#2 B7 DQSL VSS J8 QSA#3 B7 DQSL VSS J8 QSA#5 G3 VSS J2 QSA#7 G3 VSS J2
DQSU VSS M1 DQSU VSS M1 QSA#4 B7 DQSL VSS J8 QSA#6 B7 DQSL VSS J8
VSS M9 VSS M9 DQSU VSS M1 DQSU VSS M1
VSS P1 VSS P1 VSS M9 VSS M9
DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 VSS P1 VSS P1
<16> DRAM_RST# RESET VSS RESET VSS VSS VSS
T1 T1 DRAM_RST# T2 P9 DRAM_RST# T2 P9
L8 VSS T9 L8 VSS T9 RESET VSS T1 RESET VSS T1
ZQ/ZQ0 VSS ZQ/ZQ0 VSS L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

J1 B1 1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ

1
RV61 L1 B9 RV62 L1 B9 J1 B1 J1 B1
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 RV63 L1 NC/ODT1 VSSQ B9 RV64 L1 NC/ODT1 VSSQ B9
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
DIS@ L9 D8 L9 D8 243_0402_1% J9 D1 243_0402_1% J9 D1
NCZQ1 VSSQ E2 DIS@ NCZQ1 VSSQ E2 L9 NC/CE1 VSSQ D8 DIS@ L9 NC/CE1 VSSQ D8
2

DIS@ VSSQ E8 VSSQ E8 DIS@ NCZQ1 VSSQ E2 NCZQ1 VSSQ E2

2
CLKA0 1 2 VSSQ F9 VSSQ F9 VSSQ E8 VSSQ E8
RV81 56_0402_1% VSSQ G1 VSSQ G1 VSSQ F9 VSSQ F9
VSSQ G9 VSSQ G9 VSSQ G1 VSSQ G1
VSSQ VSSQ VSSQ G9 VSSQ G9
CLKA0# 1 2 96-BALL 96-BALL VSSQ VSSQ
RV82 56_0402_1% SDRAM DDR3 SDRAM DDR3 96-BALL 96-BALL
DIS@ CV234 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 SDRAM DDR3 SDRAM DDR3
0.01U_0402_25V7K @ @ K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
DIS@ +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS @ +1.5VS +1.5VS @ +1.5VS
1

1
CLKA1 1 2 RV65 RV66 RV67 RV68 RV69 RV70 RV71 RV72
B RV83 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

2

2
CLKA1# 1 2 +VREFC_A1 +VREFD_A1 +VREFC_A2 +VREFD_A2 +VREFC_A3 +VREFD_A3 +VREFC_A4 +VREFD_A4
RV84 56_0402_1%
1

1
DIS@ 1 1 1 1 1 1 1 1
CV252 RV73 CV209 RV76 CV210 RV77 CV207 RV78 CV211 RV79 CV208 RV74 CV212 RV75 CV213 RV80 CV214
0.01U_0402_25V7K 4.99K_0402_1% 0.1U_0402_16V4Z 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z
2 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
2

2
+1.5VS +1.5VS +1.5VS +1.5VS

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV231 CV215 CV232 CV216 CV233 CV235 CV236 CV253 CV217 CV218 CV219 CV220 CV221 CV222 CV223 CV249 CV224 CV237 CV225 CV226 CV238 CV239 CV227 CV254 CV240 CV228 CV241 CV229 CV242 CV243 CV230 CV255
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

+1.5VS +1.5VS
+1.5VS +1.5VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV177 CV176 CV178 CV182 CV179 CV183 CV181 CV184 CV248 CV192 CV193 CV205 CV194 CV206 CV203 CV245
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CV260 CV244 CV250 CV257 CV251 CV258 CV256 CV259 CV268 CV261 CV262 CV265 CV263 CV266 CV264 CV267
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A

+1.5VS +1.5VS
+1.5VS
+1.5VS +1.5VS
10U_0603_6.3V 1 1
2 2 2 CV247 CV270
CV284 CV283 CV282 1 1 10U_0603_6.3V 10U_0603_6.3V
DIS@ DIS@
10U_0603_6.3V
CV246
10U_0603_6.3V
CV269
10U_0603_6.3V
DIS@
2
DIS@
2
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 1 DIS@ Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
DIS@ DIS@
10U_0603_6.3V 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 17 of 47
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
GPU STRAPS +3VS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

<12> GPU_GPIO0 @ RV109 2 1 10K_0402_5% Straps Name Pin Name Net Name DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
<12> GPU_GPIO1 @ RV110 2 1 10K_0402_5%
Transmitter Power Savings Enable
<12> GPU_GPIO2 @ RV111 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 GPU_GPIO0 0: 50% Tx output swing 0
1: Full Tx output swing
<12> SOUT_GPIO8 @ RV125 2 1 10K_0402_5%
D <12> SIN_GPIO9 @ RV113 2 1 10K_0402_5% PCI Express Transmitter De-emphasis Enable D
TX_DEEMPH_EN GPIO1 GPU_GPIO1 0: Tx de-emphasis disabled 0
<12> ROMSE_GPIO22 @ RV114 2 1 10K_0402_5% 1: Tx de-emphasis enabled

<12> GPU_GPIO11 RV115 2 1 10K_0402_5% PCIE GNE2 ENABLED 0

<12> GPU_GPIO12 @ RV116 2 1 10K_0402_5% BIF_GEN2_EN_A GPIO2 GPU_GPIO2 0 = Advertises the PCIe device as 2.5 GT/s capable at power-on 5.0 GT/s capability will be
<12> GPU_GPIO13 @ RV117 2 1 10K_0402_5% 1 = Advertises the PCIe device as 5.0 GT/s capable at power-on. controlled by software

<12,20> VGA_CRT_HSYNC DIS@ RV119 2 1 10K_0402_5%

<12,20> VGA_CRT_VSYNC DIS@ RV118 2 1 10K_0402_5% RESERVED GPIO_8_ROMSO SOUT_GPIO8 RESERVED 0

<12> GENLK_CLK @ RV120 2 1 10K_0402_5% RESERVED GPIO_21_BB_EN N.C RESERVED 0 (Internal pulldown)

VGA Controller
0: VGA Controller capacity enabled
VGA_DIS GPIO_9_ROMSI SIN_GPIO9 1: The device will not be recognized as the system’s VGA controller 0 (Enable)

GPU by the system BIOS GPU by VBIOS Enable external BIOS ROM device
BIOS_ROM_EN GPIO_22_ROMCSB ROMSE_GPIO22 0 - Disable external BIOS ROM device 0
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1) 1 - Enable external BIOS ROM device

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

GPIO[13:11] MEMORY SIZE GPIO[13:11] GPU_GPIO11 a) If BIOS_ROM_EN = 1, then Config[2:0] defines the ROM type
CONFIG(2:0) GPIO[13:11] GPU_GPIO12 b) If BIOS_ROM_EN = 0, then Config[2:0] defines 0 0 1 (256M)
128MB GPU_GPIO13 the primary memory aperture size.
0 0 0
256MB
1 0 0
0 0 1
64MB
(M25P05A)
0 1 0
C C

RESERVED GENLK_CLK GENLK_CLK 0

AUD[1:0]:
External VGA Thermal Sensor EC_SMB_CK2 <7,33>
00 - No audio function;
01 - Audio for DisplayPort only;
For Internal Thermal Sensor AUD[1] HSYNC VGA_CRT_HSYNC 10 - Audio for DisplayPort and HDMI if dongle is detected; 0 0
EC_SMB_DA2 <7,33>
AUD[0] VSYNC VGA_CRT_VSYNC 11 - Audio for both DisplayPort and HDMI.
2

+3VS
1 RV141 RV138
@ 0_0402_5% 0_0402_5%
CV304 DIS@ DIS@
0.1U_0402_16V4Z
1

2
UV12 @
1 8 1 DIS@ 2
VDD SCLK GPU_SMB_CK2 <12>
<12> GPU_THERMAL_D+ RV136 0_0402_5%
1 2 7 1 DIS@ 2
D+ SDATA GPU_SMB_DA2 <12>
@ RV137 0_0402_5%
CV307 3 6
D- ALERT# THERM#_VGA <12>
2200P_0402_50V7K
2 4 5
<12> GPU_THERMAL_D- THERM# GND STRAPS PIN GPU VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 1,0

ADM1032ARMZ-2REEL_MSOP8 512M 64Mx16 (x4) SAM K4W1G1646G-BC11 SA00004GS00 10

B B
1G 128Mx16 (x4) SAM K4W2G1646C-HC11 SA000047Q00 11

Seymour-S3

VRAM_ID[1:0] DVDATA
(1,0)

+1.8VS
1

RV123 RV122
10K_0402_5% 10K_0402_5%
@ @
2

VRAM_ID1 <12> Need to check the VBIOS setting

VRAM_ID0 <12>
1

RV127 RV126
10K_0402_5% 10K_0402_5%
@ @
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 18 of 47

5 4 3 2 1
 A B C D E F G H

UMA
1 UMA@ 2 LCD_TXOUT0+ +LCD_VDD +3VALW
<7> UMA_TXOUT0+
R309 0_0402_5% 4/23 Change R117 +3VS to +3VALW for LVDS
<7> UMA_TXOUT0- 1 UMA@ 2 LCD_TXOUT0-
power down sequence

1
R289 0_0402_5%

1
<7> UMA_TXOUT1+ 1 UMA@ 2 LCD_TXOUT1+ R110
R293 0_0402_5% 100_0805_5% R117
1 UMA@ 2 LCD_TXOUT1- 100K_0402_5% +3VS
<7> UMA_TXOUT1-
R291 0_0402_5%

2
1 1 UMA@ 2 LCD_TXOUT2+ 1
<7> UMA_TXOUT2+

2
R305 0_0402_5%

6
<7> UMA_TXOUT2- 1 UMA@ 2 LCD_TXOUT2-
R287 0_0402_5% 2 W=80mils
<7> UMA_TXCLK+ 1 UMA@ 2 LCD_TXCLK+ Q1A C265
R304 0_0402_5% 2 0.047U_0402_25V7K

3
S
<7> UMA_TXCLK- 1 UMA@ 2 LCD_TXCLK- 2N7002KDWH_SOT363-6
R303 0_0402_5% 1 1 2
R133 2LCDPWR_GATE
G
Q17

1
<7> UMA_EDID_CLK 1 UMA@ 2 LCD_EDID_CLK 68K_0402_5% 1 AO3413_SOT23

3
R308 0_0402_5% D

1
1 UMA@ 2 LCD_EDID_DATA C261 +LCD_VDD
<7> UMA_EDID_DATA
R307 0_0402_5% 4700P_0402_25V7K W=80mils
LCD_ENVDD 5 2
Q1B 1
1 UMA@ 2 LCD_ENVDD 2N7002KDWH_SOT363-6 C260
<7> UMA_ENVDD

4
R358 0_0402_5% 0.1U_0402_10V7K

2
1 UMA@ 2 EC_ENBKL
<7> UMA_ENBKL EC_ENBKL <33> 2
R359 0_0402_5% R116
100K_0402_5%
4/23 Change R110,R133,C265,C261 for LVDS

1
For RF @ power down sequence
C256 47P_0402_50V8J
1 2
DISCRETE 4/23 Change R388 +3VS to +5VS
W=20mils CAM@ 1 2
0.1U_0402_10V7K R78 CAM@ 0_0402_5%
1 DIS@ 2 LCD_TXOUT0+ +5VS 1 CAM@ 2 +5VS_LVDS_CAM 1 2 4/23 Change R388 +3VS_LVDS_CAM L55 @
<13> VGA_TXOUT0+ USB20_N5 <24>
R503 0_0402_5% R388 0_0603_5% C257 USB20_N5_R 1 2
1 DIS@ 2 LCD_TXOUT0- JLVDS @ 2 to +5VS_LVDS_CAM 1 2
<13> VGA_TXOUT0-
R263 0_0402_5% 1 1
1 DIS@ 2 LCD_TXOUT1+ 1 2 USB20_N5_R 3 USB20_P5_R 4 3 USB20_P5 <24>
2 <13> VGA_TXOUT1+ 2 4 3 2
R265 0_0402_5% 3 USB20_P5_R D84 AZ5125-02S.R7G_SOT23-3
1 DIS@ 2 LCD_TXOUT1- 3 4 WCM-2012-900T_0805
<13> VGA_TXOUT1- 4 @

1
R264 0_0402_5% 5 INT_MIC_CLK
5 INT_MIC_CLK <31> R73
1 DIS@ 2 LCD_TXOUT2+ 6 INT_MIC_DATA 2A 1 2
<13> VGA_TXOUT2+ 6 INT_MIC_DATA <31>
R298 0_0402_5% 7 +LCD_VDD R104CAM@ 0_0402_5% 300_0402_5%
1 DIS@ 2 LCD_TXOUT2- 7 8 @
<13> VGA_TXOUT2- 8 1 1
R504 0_0402_5% 9 Reserve for EMI request

2
1 DIS@ 2 LCD_TXCLK+ 9 10 C252 C235
<13> VGA_TXCLK+ 10 +3VS 1
R297 0_0402_5% 11 LCD_EDID_CLK 0.1U_0402_10V7K 4.7U_0805_10V4Z C300
1 DIS@ 2 LCD_TXCLK- 11 12 LCD_EDID_DATA 2 2
<13> VGA_TXCLK- 12 10P_0402_50V8J
R296 0_0402_5% 13
1 DIS@ 2 LCD_EDID_CLK 13 14 LCD_TXOUT0- 2@
<12> VGA_EDID_CLK 14
R300 0_0402_5% 15 LCD_TXOUT0+
1 DIS@ 2 LCD_EDID_DATA 15 16
<12> VGA_EDID_DATA 16
R299 0_0402_5% 17 LCD_TXOUT1- For RF @
17 18 LCD_TXOUT1+ C258 47P_0402_50V8J
18 Reserved for EHCI CRC errors
19 +LCD_INV 1 2
1 DIS@ 2 LCD_ENVDD 19 20 LCD_TXOUT2-
<13> VGA_ENVDD 20
R350 0_0402_5% 21 LCD_TXOUT2+ 2
1 DIS@ 2 EC_ENBKL 21 22 1
<12> VGA_ENBKL 22
R357 0_0402_5% 23 LCD_TXCLK- 3
23 24 LCD_TXCLK+ D85 AZ5125-02S.R7G_SOT23-3
31 24 25 LED_PWM
Close to LVDS Connector 32 GND1
GND2
25
26
26 BKOFF#_R
@
JLVDS1
33 27
34 GND3 27 28 12
35 GND4 28 29 GND 11
GND5 29 1.5A GND
1 DIS@ 2 LCD_TZOUT0+ 36 30 +LCD_INV 10 LCD_TZOUT0-
<13> VGA_TZOUT0+ GND6 30 10
R500 0_0402_5% 9 LCD_TZOUT0+
1 DIS@ 2 LCD_TZOUT0- 21 9 8 LCD_TZOUT1-
<13> VGA_TZOUT0- 8
R506 0_0402_5% STARC_107K30-000001-G2 @ 7 LCD_TZOUT1+
1 DIS@ 2 LCD_TZOUT1+ C270 47P_0402_50V8J 7 6 LCD_TZOUT2-
3 <13> VGA_TZOUT1+ 6 3
R507 0_0402_5% For RF 5 LCD_TZOUT2+
1 DIS@ 2 LCD_TZOUT1- 5 4 LCD_TZCLK-
<13> VGA_TZOUT1- 4
R508 0_0402_5% 3 LCD_TZCLK+ LED_PWM 1 2 2 DIS@ 1 VGA_PWM <13>
1 DIS@ 2 LCD_TZOUT2+ 3 2 RB751V40_SC76-2 D17 0_0402_5% R333
<13> VGA_TZOUT2+ 2
R509 0_0402_5% 1
1 DIS@ 2 LCD_TZOUT2- 1
<13> VGA_TZOUT2-

1
R512 0_0402_5%
1 DIS@ 2 LCD_TZCLK+ ACES_87036-1001-CP R234 2 UMA@ 1
<13> VGA_TZCLK+ @ UMA_PWM <7>
R513 0_0402_5% 47K_0402_5% 0_0402_5% R332
1 DIS@ 2 LCD_TZCLK-
<13> VGA_TZCLK-
R514 0_0402_5%

2
1.5A
+LCD_INV B+
L16
2 1 BKOFF#_R 1 2
BKOFF# <33>
1 1 FBMA-L11-201209-221LMA30T_0805 D15 RB751V40_SC76-2

1
C262 C264
68P_0402_50V8J 0.1U_0402_25V6 R122
2 2
10K_0402_5%
B+

2
For EMI
Reserve for LVDS panel

1 1 1 1
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

4 C251 C281 C489 C490 4

@ @ @ @
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 19 of 47
A B C D E F G H
 A B C D E

CRT CONNECTOR
If=1A
+5VS +CRT_VCC_R +CRT_VCC
Remove D3~D5 on DVT D6
2 F1 40 mils
1 1 1 2 1
3 1
0.5A_8V_KMC3S050RY
RB491D_SOT23-3 C247
0.1U_0402_16V4Z
CRT_R L20 1 2 NBQ100505T-800Y_0402 CRT_R_L @ 2

CRT_G L19 1 2 NBQ100505T-800Y_0402 CRT_G_L

CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L

JCRT
6
UMA T75 PAD 11

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
R140 R141 R147 CRT_R_L 1

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 7

1
<7> UMA_CRT_R 1 UMA@ 2 CRT_R CRT_DDC_DAT 12
R221 0_0402_5% C241 C242 C248 C243 C250 C249 CRT_G_L 2
<7> UMA_CRT_G 1 UMA@ 2 CRT_G 8 G 16
R222 0_0402_5% 2 2 2 2 2 2 HSYNC 13 17
G
<7> UMA_CRT_B 1 UMA@ 2 CRT_B CRT_B_L 3

2
R223 0_0402_5% +CRT_VCC 9
1 UMA@ 2 CRT_HSYNC VSYNC 14
<7> UMA_CRT_HSYNC
R224 0_0402_5% T76 PAD 4
1 UMA@ 2 CRT_VSYNC 10
<7> UMA_CRT_VSYNC
R235 0_0402_5% CRT_DDC_CLK 15
<7> UMA_CRT_CLK 1 UMA@ 2 CRT_CLK 5
R238 0_0402_5%
1 UMA@ 2 CRT_DATA +CRT_VCC SUYIN_070546FR015S251ZR
<7> UMA_CRT_DATA
R285 0_0402_5% @

1 2
2 C244 0.1U_0402_16V4Z 2 1 2
Close to CRT Connector R150 10K_0402_5%

5
1
D98 @

P
OE#
CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC CRT_R_L 6 3 CRT_B_L
A Y L18 10_0402_5% I/O4 I/O2

G
U6 +CRT_VCC
SN74AHCT1G125GW_SOT353-5

3
C268 5 2
DISCRETE 1 2
+CRT_VCC VDD GND

5
1
0.1U_0402_16V4Z
1 DIS@ 2 CRT_R CRT_G_L 4 1

P
OE#
<12> VGA_CRT_R I/O3 I/O1
R232 0_0402_5% CRT_VSYNC 2 4 D_CRT_VSYNC 1 2 VSYNC
A Y

10P_0402_50V8J

10P_0402_50V8J
1 DIS@ 2 CRT_G L17 10_0402_5% 1 1 AZC099-04S.R7G_SOT23-6
<12> VGA_CRT_G

G
R233 0_0402_5% U7
1 DIS@ 2 CRT_B SN74AHCT1G125GW_SOT353-5 C245 C246
<12> VGA_CRT_B

3
R229 0_0402_5% @ @ D97 @
1 DIS@ 2 CRT_HSYNC 2 2 CRT_DDC_CLK 6 3 HSYNC
<12,18> VGA_CRT_HSYNC I/O4 I/O2
R230 0_0402_5%
1 DIS@ 2 CRT_VSYNC
<12,18> VGA_CRT_VSYNC
R231 0_0402_5%
<12> VGA_CRT_CLK 1 DIS@ 2 CRT_CLK +CRT_VCC 5 2
R225 0_0402_5% VDD GND
<12> VGA_CRT_DATA 1 DIS@ 2 CRT_DATA
R226 0_0402_5%
CRT_DDC_DAT 4 1 VSYNC
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
Close to CRT Connector
+CRT_VCC

3 +3VS Reserve ESD for CRT connector on DVT 3

2
R153 R163
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A

CRT_CLK 1 6 CRT_DDC_CLK

5
2N7002KDWH_SOT363-6
Q205B
CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002KDWH_SOT363-6
C285 C287
C288 C286 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2@
@ 2 2@

4 4

<Schematic Path>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 20 of 47
A B C D E
 A B C D E

+3VS
+HDMI_5V_OUT

D53 F2
+5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
VGA_DVI_TXC- IHDMI@ 1 2 HDMI_R_CK-
R157 22_0402_5% PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY
1 HDMI@ HDMI@ 1 1
L8 DHDMI@ C202 C259 C216
IHDMI@ 1 2 560P_0402_50V7K 0.1U_0402_16V4Z 560P_0402_50V7K
1 2

1
2 1 @ HDMI@ @
<7> UMA_HDMI_CLK 2 2 2
1 R435 0_0402_5% R184 R185 1
4.7K_0402_5% 4.7K_0402_5% 4 3
DHDMI@ HDMI@ HDMI@ 4 3

2
<12> VGA_HDMI_CLK 2 1 WCM-2012-900T_0805

2
G
R391 0_0402_5% VGA_DVI_TXC+ IHDMI@ 1 2 HDMI_R_CK+ 4/23 Add C202 and C216 for EMI request
R173 22_0402_5%
3 1 HDMI_SCLK VGA_DVI_TXD0- IHDMI@ 1 2 HDMI_R_D0-

2
HDMI@ R175 22_0402_5%

D
Q26
DHDMI@ BSH111_SOT23-3 L9 DHDMI@
<12> VGA_HDMI_DATA 2
R401
1
0_0402_5%
3 1 HDMI_SDATA 1
1 2
2
HDMI Connector

D
HDMI@
IHDMI@ Q27 4 3 JHDMI @
2 1 BSH111_SOT23-3 4 3 HDMI_HPD_C 19
<7> UMA_HDMI_DATA HP_DET
R438 0_0402_5% WCM-2012-900T_0805 +HDMI_5V_OUT 18
VGA_DVI_TXD0+ IHDMI@ 1 2 HDMI_R_D0+ 17 +5V
R180 22_0402_5% HDMI_SDATA 16 DDC/CEC_GND
VGA_DVI_TXD1- IHDMI@ 1 2 HDMI_R_D1- HDMI_SCLK 15 SDA
DISCRETE R182 22_0402_5% 14 SCL
Reserved
13
L10 DHDMI@ HDMI_R_CK- 12 CEC 20
CV296 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC+ 1 2 11 CK- GND 21
<12> VGA_HDMI_CLK+ 1 2 CK_shield GND
HDMI_R_CK+ 10 22
CV293 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC- HDMI_R_D0- 9 CK+ GND 23
<12> VGA_HDMI_CLK- D0- GND
4 3 8
CV294 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0+ 4 3 HDMI_R_D0+ 7 D0_shield
<12> VGA_HDMI_TX0+ D0+
2 WCM-2012-900T_0805 HDMI_R_D1- 6 2
CV297 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0- VGA_DVI_TXD1+ IHDMI@ 1 2 HDMI_R_D1+ 5 D1-
<12> VGA_HDMI_TX0- D1_shield
R183 22_0402_5% HDMI_R_D1+ 4
CV299 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1+ VGA_DVI_TXD2- IHDMI@ 1 2 HDMI_R_D2- HDMI_R_D2- 3 D1+
<12> VGA_HDMI_TX1+ D2-
R187 22_0402_5% 2
CV298 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1- HDMI_R_D2+ 1 D2_shield
<12> VGA_HDMI_TX1- D2+
L11 DHDMI@
CV295 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2+ 1 2 HONGL_13-13201904CP
<12> VGA_HDMI_TX2+ 1 2
CV300 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2-
<12> VGA_HDMI_TX2-
4 3
4 3
WCM-2012-900T_0805 +HDMI_5V_OUT
VGA_DVI_TXD2+ IHDMI@ 1 2 HDMI_R_D2+ R148
R188 22_0402_5% HDMI_HPD_U 1 2 HDMI_HPD_C
2 1K_0402_5%
C266 HDMI@ 2

2
0.1U_0402_16V4Z R189 C267

1
HDMI@ U10 100K_0402_5% 0.1U_0402_16V4Z
D95 @ 1 HDMI@ HDMI@
UMA

OE#
HDMI_R_D0+ 1 1 109 HDMI_R_D0+ 2 4 HDMI_HPD 1
A Y

1
G
HDMI_R_D0- 2 2 98 HDMI_R_D0- 74AHCT1G125GW_SOT353-5
C838 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC+ HDMI@
<7> UMA_HDMI_TXC+

3
HDMI_R_D2+ 4 4 77 HDMI_R_D2+
C837 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC-
<7> UMA_HDMI_TXC-
HDMI_R_D2- 5 5 6 6 HDMI_R_D2-
3 C843 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0+ 3
<7> UMA_HDMI_TX0+
3 3
C844 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0- HDMI_R_CK+ 1 HDMI@ 2
<7> UMA_HDMI_TX0- 8 R195 499_0402_1%
C841 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1+ HDMI_R_CK- 1 HDMI@ 2
<7> UMA_HDMI_TX1+
R197 499_0402_1%
C842 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1- AZ1045-04F_DFN2510P10E-10-9 HDMI_R_D1- 1 HDMI@ 2
<7> UMA_HDMI_TX1-
R198 499_0402_1%
C839 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2+ HDMI_R_D1+ 1 HDMI@ 2 IHDMI@ DHDMI@
<7> UMA_HDMI_TX2+
R201 499_0402_1% +3VS 2 1 1 2 +3VS
C840 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2- HDMI_R_D0+ 1 HDMI@ 2 R571 R572
<7> UMA_HDMI_TX2-
R202 499_0402_1% 2.2K_0402_5% 2.2K_0402_5%
D94 @ HDMI_R_D0- 1 HDMI@ 2 1 IHDMI@ 2 HDMI_HPD 2 DHDMI@1
<7> UMA_HDMI_HPD VGA_HDMI_HPD <12>
HDMI_R_D1+ 1 1 109 HDMI_R_D1+ R203 499_0402_1% 0_0402_5% R436 R392 0_0402_5%
HDMI_R_D2- 1 HDMI@ 2

2
HDMI_R_D1- 2 2 9 8 HDMI_R_D1- R205 499_0402_1%
HDMI_R_D2+ 1 HDMI@ 2
HDMI_R_CK+ 4 4 77 HDMI_R_CK+ R206 499_0402_1% R190 @
100K_0402_5%

1
HDMI_R_CK- 5 5 6 6 HDMI_R_CK- D Q6

1
+5VS 2 2N7002_SOT23-3
D96 @ 3 3 G HDMI@
HDMI_HPD_C 6 3 HDMI_SDATA S

3
I/O4 I/O2 8

+5VS 5 2 AZ1045-04F_DFN2510P10E-10-9
VDD GND
4 4

+HDMI_5V_OUT 4 1 HDMI_SCLK
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev
Reserve ESD for HDMI conn. on DVT AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 21 of 47
A B C D E

www.vinafix.vn
 A B C D E

U2A

HUDSON-2
APU_PCIE_RST#_R AE2 AF3 PCI_CLK0 R260 1 2 22_0402_5%
PCIE_RST# PCICLK0 CLK_PCI_TPM_FCH <32>
LPC_RST#_R AD5 AF1

PCI CLKS
A_RST# PCICLK1/GPO36 PCI_CLK1 <26>
AF5
C147 1 2 0.1U_0402_16V7K UMI_RXP0_C AE30 PCICLK2/GPO37 AG2
<5> UMI_RX0P
C148 1 2 0.1U_0402_16V7K UMI_RXN0_C AE32 UMI_TX0P PCICLK3/GPO38 AF6
PCI_CLK3 <26> Strap
<5> UMI_RX0N UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <26>
C149 1 2 0.1U_0402_16V7K UMI_RXP1_C AD33
<5> UMI_RX1P UMI_TX1P
C150 1 2 0.1U_0402_16V7K UMI_RXN1_C AD31 AB5
<5> UMI_RX1N UMI_TX1N PCIRST#
C151 1 2 0.1U_0402_16V7K UMI_RXP2_C AD28
<5> UMI_RX2P UMI_TX2P
C152 1 2 0.1U_0402_16V7K UMI_RXN2_C AD29 PCIE_RST# is for PCIE devices on APU
<5> UMI_RX2N UMI_TX2N
C153 1 2 0.1U_0402_16V7K UMI_RXP3_C AC30 AJ3
<5> UMI_RX3P UMI_TX3P AD0/GPIO0
C154 1 2 0.1U_0402_16V7K UMI_RXN3_C AC32 AL5 APU_PCIE_RST#_R R247 1 2 33_0402_5%
1 <5> UMI_RX3N UMI_TX3N AD1/GPIO1 APU_PCIE_RST# <11,29,30,32> 1
AG4
AD2/GPIO2

2
AB33 AL6 1
<5> UMI_TX0P UMI_RX0P AD3/GPIO3
AB31 AH3 C299 R248

PCI EXPRESS INTERFACES

<5> UMI_TX0N UMI_RX0N AD4/GPIO4
AB28 AJ5 100K_0402_5%
<5> UMI_TX1P UMI_RX1P AD5/GPIO5
AB29 AL1 150P_0402_50V8J @
<5> UMI_TX1N UMI_RX1N AD6/GPIO6 2
Y33 AN5
<5> UMI_TX2P

1
Y31 UMI_RX2P AD7/GPIO7 AN6
<5> UMI_TX2N UMI_RX2N AD8/GPIO8
Y28 AJ1
<5> UMI_TX3P UMI_RX3P AD9/GPIO9
Y29 AL8 A_RST# is for LPC devices
<5> UMI_TX3N UMI_RX3N AD10/GPIO10 AL3
R94 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7 LPC_RST#_R R259 1 2 33_0402_5%
PCIE_CALRP AD12/GPIO12 LPC_RST# <33,34>
+VDDAN_11_PCIE R88 1 2 2K_0402_1% PCIE_CALRN AF31 AJ6
PCIE_CALRN AD13/GPIO13

2
AK7 1
C718 1 2 0.1U_0402_16V7K PCIE_FTX_LANRX_P0 V33 AD14/GPIO14 AN8 C298 R257
LAN <30> PCIE_FTX_C_LANRX_P0
C720 1 2 0.1U_0402_16V7K PCIE_FTX_LANRX_N0 V31 GPP_TX0P AD15/GPIO15 AG9 100K_0402_5%
<30> PCIE_FTX_C_LANRX_N0 GPP_TX0N AD16/GPIO16
C721 1 2 0.1U_0402_16V7K PCIE_FTX_WLANRX_P1W30 AM11 150P_0402_50V8J @
<29> PCIE_FTX_C_WLANRX_P1 GPP_TX1P AD17/GPIO17 2
C719 1 2 0.1U_0402_16V7K PCIE_FTX_WLANRX_N1W32 AJ10
WLAN <29> PCIE_FTX_C_WLANRX_N1

1
AB26 GPP_TX1N AD18/GPIO18 AL12
AB27 GPP_TX2P AD19/GPIO19 AK11
AA24 GPP_TX2N AD20/GPIO20 AN12
AA23 GPP_TX3P AD21/GPIO21 AG12
GPP_TX3N AD22/GPIO22 AE12
AD23/GPIO23 PCI_AD23 <26>
AA27 AC12
<30> PCIE_FRX_C_LANTX_P0 GPP_RX0P AD24/GPIO24 PCI_AD24 <26>
AA26 AE13 Strap
<30> PCIE_FRX_C_LANTX_N0 GPP_RX0N AD25/GPIO25 PCI_AD25 <26>
W27 AF13
<29> PCIE_FRX_WLANTX_P1 GPP_RX1P AD26/GPIO26 PCI_AD26 <26>
V27 AH13

PCI INTERFACE
<29> PCIE_FRX_WLANTX_N1 GPP_RX1N AD27/GPIO27 PCI_AD27 <26>
V26 AH14 1 2
GPP_RX2P AD28/GPIO28 VGA_PWRGD <45>
W26 AD15 R243 @ 0_0402_5%
W24 GPP_RX2N AD29/GPIO29 AC15 GPIO30
W23 GPP_RX3P AD30/GPIO30 AE16 GPIO31 +3VS
GPP_RX3N AD31/GPIO31 AN3
CBE0# AJ8 @
2 CBE1# AN10 1 2 GPIO30 1 2 2
R95 1 2 2K_0402_1% CLK_CALRN F27 CBE2# AD12 R337 10K_0402_5% R334 10K_0402_5%
+1.1VS_CKVDD CLK_CALRN CBE3# AG10
FRAME# AK9 1 2 GPIO31 1 2
DEVSEL# AL10 R340 10K_0402_5% R339 10K_0402_5%
Input from external clock generator G30 IRDY# AF10 DIS@
PCIE_RCLKP TRDY# UMA@
NC for internal clock generator G28 AE10
SS PCIE_RCLKN PAR AH1
R26 STOP# AM9
<7> APU_DISP_CLK DISP_CLKP PERR#
APU Display T26 AH8
<7> APU_DISP_CLK# DISP_CLKN SERR# AG15
H33 REQ0# AG13
NSS H31 DISP2_CLKP REQ1#/GPIO40 AF15
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17
REQ3#/CLK_REQ5#/GPIO42 T16 Function GPIO30 GPIO31
T24 AD16
<7> APU_CLK APU_CLKP GNT0#
APU T23 AD13 Discrete 1 0
<7> APU_CLK# APU_CLKN GNT1#/GPO44 AD21
J30 GNT2#/SD_LED/GPO45 AK17
<11> CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 T99 UMA 1 1
K29 AD19
VGA <11> CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN# AH9
H27 LOCK#
H28 GPP_CLK0P AF18
GPP_CLK0N INTE#/GPIO32 +RTCVCC +RTCBATT
AE18
INTF#/GPIO33

0.1U_0402_10V7K

RB751V-40_SOD323-2
J27 AC16
K26 GPP_CLK1P INTG#/GPIO34 AD18
GPP_CLK1N INTH#/GPIO35 1

C269

1
F33 @
<29> CLK_PCIE_WLAN GPP_CLK2P
WLAN F31 D13

CLOCK GENERATOR
<29> CLK_PCIE_WLAN# GPP_CLK2N 2

D14
B25 LPC_CLK0 R558 1 2 22_0402_5%
SS E33 LPCCLK0 CLK_PCI_EC <26,33> RB751V-40_SOD323-2
<30> CLK_PCIE_LAN GPP_CLK3P
LAN E31 D25 LPC_CLK1 R258 1 2 22_0402_5%
<30> CLK_PCIE_LAN# CLK_PCI_DDR <26,34>

2
GPP_CLK3N LPCCLK1 D27
3 LAD0 LPC_AD0 <32,33,34> 3
M23 C28 +RTCBATT
GPP_CLK4P LAD1 LPC_AD1 <32,33,34> +3VL
M24 A26 LPC_AD2 <32,33,34>
GPP_CLK4N LAD2 A29
LAD3 LPC_AD3 <32,33,34> If use GCLK, please delete D14
M27 A31
LPC
GPP_CLK5P LFRAME# LPC_FRAME# <32,33,34>
M26 B27 DMA active. The FCH drives the DMA_ACTIVE# to
GCLK@ GPP_CLK5N LDRQ0# AE27
1 2 32K_X1 N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19 APU to notify DMA activity. This will cause the APU
<29> FCH_RTCX1_R GPP_CLK6P SERIRQ/GPIO48 SERIRQ <32,33>
R240 0_0402_5% N26
GPP_CLK6N
to reestablish the UMI link quicker.
Place close to Y2 R23
R24 GPP_CLK7P G25
GPP_CLK7N DMA_ACTIVE# DMA_ACTIVE# <7>
E28 APU_PROCHOT#_R 1 @ 2
PROCHOT# H_PROCHOT# <7,33>
GCLK@ N27 E26 R15 0_0402_5%
GPP_CLK8P APU_PG APU_PWRGD <7,43>
1 2 25M_X1 R27 G26
<29> FCH_X1_R GPP_CLK8N LDT_STP#
R241 0_0402_5% F26
APU

APU_RST# APU_RST# <7> S5_CORE_EN is for S5+ mode

J26 used to turn off +1.1VALW and
Place close to Y1 14M_25M_48M_OSC
4/23 Change R241 from GCLK@ to @ for USB30 S5_CORE_EN
H7 T100 +3VALW of FCH on S5+ mode
F1 1
RTC_CLK_R 2
wake issue RTCCLK RTC_CLK <26,33>
F3 R261 0_0402_5%
C294 1 2 27P_0402_50V8J 25M_X1 C31 INTRUDER_ALERT# E6 +RTCVCC_R
NOGCLK@ 25M_X1 VDDBT_RTC_G
4/23 Change R271 and add R277,R268,C305,+RTCBATT_D
1

G2 32K_X1
S5 PLUS

Y1 R242 32K_X1
25MHZ_20PF_7A25000012 1M_0402_5% 25M_X2 C33 +RTCVCC +RTCBATT_D
NOGCLK@ NOGCLK@ 25M_X2
2

G4 32K_X2 20 mils R271 R277 R268

1 2
NOGCLK@ 32K_X2 1 2 1 2+RTCBATT_R 1 2
C293 27P_0402_50V8J 120_0402_5% 120_0402_5% 1K_0402_5%
4/23 Change C294,C293,Y1,R242 to mount for USB30 1 1

1
218-0755091 A13 HUDSON-M3L FCBGA 656P C38 C296 C295 JCMOS 1
wake issue M3LR1@ @ C305
4 0.1U_0402_16V4Z 1U_0402_6.3V6K 4

2
2 2 0.1U_0402_16V4Z
C292 1 2 18P_0402_50V8J 32K_X1 2
CMOS Setting
NOGCLK@ Place under DDR
1

Door
R245 Y2
20M_0402_5% 32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@ NOGCLK@
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

2

C291
1 2
18P_0402_50V8J
32K_X2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
NOGCLK@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4 B

Date: Saturday, September 07, 2013 Sheet 22 of 47

A B C D E
 A B C D E

HDMI_EN# (Internal 8.2K PU)

HDMI_EN# H L
Non-HDMI
SKU SKU HDMI SKU
If an SPI ROM is shared between FCH
U2B and the Embedded Controller, a 10-k
1
pull-up resistor to +3.3V_S5 is installed 1
HUDSON-2 @
AK19 AL14 2 1
<27> SATA_FTX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73 +3VALW_FCH
AM19 AN14 R455 1K_0402_1% Check
<27> SATA_FTX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74
HDD AJ12
AL20 SD_CD/GPIO75 AH12
<27> SATA_FRX_C_DTX_N0 SATA_RX0N SD_WP/GPIO76
AN20 AK13 FCH_SPI_CS1# 1 @ 2 from QMLE4
<27> SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77

SD CARD
AM13 R115 10K_0402_5%
AN22 SD_DATA1/SDATO_2/GPIO78 AH15
<27> SATA_FTX_DRX_P1 SATA_TX1P SD_DATA2/GPIO79
AL22 AJ14
<27> SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
ODD
AH20 AC4
<27> SATA_FRX_C_DTX_N1 SATA_RX1N GBE_COL
4MB SPI ROM & Non-shared ROM
AJ20 AD3
<27> SATA_FRX_C_DTX_P1 SATA_RX1P GBE_CRS AD9
AJ22 GBE_MDCK W10
AH22 SATA_TX2P GBE_MDIO AB8
SATA_TX2N GBE_RXCLK AH7
AM23 GBE_RXD3 AF7 +3VALW_FCH
AK23 SATA_RX2N GBE_RXD2 AE7 C498
SATA_RX2P GBE_RXD1 SA00003K800
AD7 1 2
AH24 GBE_RXD0 AG8 U13
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1 FCH_SPI_CS1# 1 8 0.1U_0402_16V4Z
SATA_TX3N GBE_RXERR AB7 FCH_SPI_MISO 2 CS# VCC 7 FCH_SPI_HOLD# FCH_SPI_CLK_R
AN24 GBE_TXCLK AF9 FCH_SPI_WP# 3 SO/SIO1 HOLD# 6 FCH_SPI_CLK_R

GBE LAN
AL24 SATA_RX3N GBE_TXD3 AG6 4 WP# SCLK 5 FCH_SPI_MOSI
SATA_RX3P GBE_TXD2 AE8 +3VALW_FCH GND SI/SIO0
GBE_TXD1

1
AL26 AD8 W25Q32BVSSIG_SO8
AN26 SATA_TX4P GBE_TXD0 AB9 R111
SATA_TX4N GBE_TXCTL/TXEN AC2 33_0402_5%

SERIAL ATA
AJ26 GBE_PHY_PD AA7 R112 1 2FCH_SPI_WP# @
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR 10K_0402_5%

2
SATA_RX4P GBE_PHY_INTR

2
FCH-M3L NC pin AN29
AL28 SATA_TX5P V6 FCH_SPI_MISO
R108 1 2FCH_SPI_HOLD#
10K_0402_5% C160 2
SATA_TX5N SPI_DI/GPIO164 V5 FCH_SPI_MOSI
SPI_DO/GPIO163 22P_0402_50V8J
AK27 V3 FCH_SPI_CLK @
SATA_RX5N SPI_CLK/GPIO162

SPI ROM
AM27 T6 FCH_SPI_CS1#
To avoid LED flashing
SATA_RX5P SPI_CS1#/GPIO165 V1 FCH_SPI_WP# Socket: SP07000F500/SP07000H900
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6
+5VS NC7 L30
AL31 VGA_RED FCH_SPI_CLK 1 2 FCH_SPI_CLK_R
1 2 SATA_LED# AL33 NC8 R113 0_0402_5%
R448 10K_0402_5% NC9 L32
2 1 AH33 VGA_GREEN
R454 20K_0402_5% AH31 NC10 C161
NC11 M29
VGA_BLUE 22P_0402_50V8J
AJ33 @
AJ31 NC12
5/17 Add R113 and reserve C161 for EMI request

VGA DAC
NC13 M28
VGA_HSYNC/GPO68 N30
VGA_VSYNC/GPO69
M33 +3VALW_FCH
1K_0402_1% 2 1 R128 SATA_CALRP AF28 VGA_DDC_SDA/GPO70 N32
SATA_CALRP VGA_DDC_SCL/GPO71 GBE_PHY_INTR R121 1 2 10K_0402_5%

FCH-M3L NC pin
+AVDD_SATA 931_0402_1% 2 1 R130 SATA_CALRN AF27
SATA_CALRN K31
VGA_DAC_RSET
SATA_LED# AD22
<35> SATA_LED# SATA_ACT#/GPIO67 V28
AUX_VGA_CH_P V29
AF21 AUX_VGA_CH_N
VGA MAINLINK
SATA_X1 U28
AUXCAL
T31
3 ML_VGA_L0P T33 3
AG21 ML_VGA_L0N T29
SATA_X2 ML_VGA_L1P T28
ML_VGA_L1N R32
ML_VGA_L2P R30 +3VALW_FCH
ML_VGA_L2N P29
ML_VGA_L3P P28 SLP_CHG# 1 @ 2
ML_VGA_L3N <28> SLP_CHG#
R126 10K_0402_5%

C29
ML_VGA_HPD/GPIO229

T48 AH16 N2 1 2
AM15 FANOUT0/GPIO52 VIN0/GPIO175 R137 10K_0402_5%
<36> ODD_PWR FANOUT1/GPIO53
AJ16 HW MONITOR M3 1 2
FANOUT2/GPIO54 VIN1/GPIO176 R138 10K_0402_5%
AK15 L2 1 2
AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 R145 10K_0402_5%
AL16 FANIN1/GPIO57 N4 1 2
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 R139 10K_0402_5%
P1 1 2
1 2 K6 VIN4/SLOAD_1/GPIO179 R142 10K_0402_5%
R151 10K_0402_5% TEMPIN0/GPIO171 P3 SLP_CHG#1 2
VIN5/SCLK_1/GPIO180 R143 10K_0402_5%
1 2 K5 M1 1 2
R146 10K_0402_5% TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R144 10K_0402_5%
M5 1 2
1 2 K3 VIN7/GBE_LED3/GPIO182 RF148 10K_0402_5%
R149 10K_0402_5% TEMPIN2/GPIO173
AG16
1 2 M6 NC1 AH10
R152 10K_0402_5% TEMPIN3/TALERT#/GPIO174 NC2 A28
NC3
Need to enable internal
4 G27 4
NC4 pull down to leave
L4 unconnected
NC5
12/22 Follow the last Compal CRB board
218-0755091 A13 HUDSON-M3L FCBGA 656P C38

M3LR1@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 23 of 47
A B C D E
 A B C D E

U2D
PCIE_RST2 : Reset PCIE device on Hudson 3
HUDSON-2
T17 AB6 G8

USB MISC
R2 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
<33> EC_LID_OUT# RI#/GEVENT22#
ODD_PLUGIN# W7 B9 USB_RCOMP R154 1 2 11.8K_0402_1%
<27> ODD_PLUGIN# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
T3
<33> SLP_S3# SLP_S3#
W2 H1
<33> SLP_S5# SLP_S5# USB_FSD1P/GPIO186
J4 H3
<33> PBTN_OUT# PWR_BTN# USB_FSD1N
N7
<33> FCH_PWRGD PWR_GOOD H6

USB 1.1
TEST0 T9 USB_FSD0P/GPIO185 H5
For FCH internal debug use

ACPI / WAKE UP EVENTS

TEST0 USB_FSD0N
FCH-M3L NC pin
+3VALW_FCH TEST1 T10
1 (Internal 10K pull-down) TEST2 V9 TEST1/TMS H10 1
R179 1 @ 2 2.2K_0402_5% TEST0 TEST2 USB_HSD13P G10
AE22 USB_HSD13N
<33> GATEA20 GA20IN/GEVENT0#
R181 1 @ 2 2.2K_0402_5% TEST1 K10
AG19 USB_HSD12P J12
<33> KB_RST# KBRST#/GEVENT1# USB_HSD12N
RF183 1 @ 2 2.2K_0402_5% TEST2 R9
<33> EC_SCI#
<33> EC_SMI#
C26
T5
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
USB_HSD11P
USB_HSD11N
G12
F12
USB20_P11 <28>
USB20_N11 <28> USB 3.0-Left2
Root
U4
FCH_PCIE_WAKE# K1 SYS_RESET#/GEVENT19# K12
<30> FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 <28>
V7 K13 USB 3.0-Left1
IR_RX1/GEVENT20# USB_HSD10N USB20_N10 <28>
H_THERMTRIP# R10
<7> H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
FCH-M3L NC pin
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P D11
U2 USB_HSD9N
<33> EC_RSMRST# RSMRST# E10
USB_HSD8P USB20_P8 <29>
AG24 F10 WLAN (BT)
CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N USB20_N8 <29>
AE24
<30> CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63
AE26 C10
AF22 SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
USB_HSD7P
USB_HSD7N
A10
USB20_P7 <32>
USB20_N7 <32> Cardreader Root

USB 2.0
AH17
AG18 SATA_IS4#/FANOUT3/GPIO55 H9
AF24 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P G9
<31> FCH_SPKR SPKR/GPIO66 USB_HSD6N
SM Bus 0-->S0 PWR domain==> SO-DIMM, WLAN FCH_SCLK0 AD26

GPIO
<9,10,29> FCH_SCLK0 SCL0/GPIO43
FCH_SDATA0 AD25 A8
SM Bus 1-->S5 PWR domain==> no use <9,10,29> FCH_SDATA0
FCH_SCLK1 T7 SDA0/GPIO47 USB_HSD5P C8
USB20_P5 <19>
FCH_SDATA1 R7 SCL1/GPIO227 USB_HSD5N USB20_N5 <19> Int. Camera
SDA1/GPIO228
FCH-M3L NC pin
2 1 EC_RSMRST# AG25 F8
<29> CLKREQ_WLAN# CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P
R282 100K_0402_5% AG22 E8
1 @ 2 HDA_BITCLK J2 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N
R324 10K_0402_5% AG26 IR_LED#/LLB#/GPIO184 C6
1 @ 2 AZ_SDIN0_HD V8 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P A6
2 R325 10K_0402_5% LAN_EN W8 DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N 2
<30> LAN_EN GBE_LED0/GPIO183
1 @ 2 AZ_SDIN1_HD Y6 C5
R326 10K_0402_5% V10 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P A5
1
R327
@ 2
10K_0402_5%
AZ_SDIN2_HD
<12> CLKREQ_PEG#
CLKREQ_PEG#
AA8
AF25
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
USB_HSD2N

USB_HSD1P
C1
USB20_P1 <27>
Root
1 @ 2 AZ_SDIN3_HD C3
USB_HSD1N USB20_N1 <27>
R329 10K_0402_5%
M7 E1
BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB20_P0 <27>
12/22 Reserve R326,R327,R329 but R8 E3
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 <27>
T59 T1

USB OC
AMD have internal pull down ODD_DA#_FCH P6 USB_OC5#/IR_TX0/GEVENT17# C16 USBSS_CALRP R864 1 2 1K_0402_1%
T58 F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP A16 USBSS_CALRN R865 1 2 1K_0402_1%
USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN +FCH_VDD_11_SSUSB_S
T56 P5
USB_OC1# J7 USB_OC2#/TCK/GEVENT14# A14
USB_OC1# is for left USB3.0 ports <28> USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# is for right USB2.0 ports <27> USB_OC0# T8 C14
USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
C12
USB_SS_RX3P
FCH-M3L NC pin
A12
USB_SS_RX3N
R159 1 2 33_0402_5% HDA_BITCLK AB3 D15
<31> AZ_BITCLK_HD AZ_BITCLK USB_SS_TX2P
R160 1 2 33_0402_5% HDA_SDOUT AB1 B15
<31> AZ_SDOUT_HD AZ_SDOUT USB_SS_TX2N
AZ_SDIN0_HD AA2

HD AUDIO
+3VALW_FCH <31> AZ_SDIN0_HD AZ_SDIN0/GPIO167
AZ_SDIN1_HD Y5 E14
AZ_SDIN1/GPIO168 USB_SS_RX2P

USB 3.0
AZ_SDIN2_HD Y3 F14
AZ_SDIN3_HD Y1 AZ_SDIN2/GPIO169 USB_SS_RX2N
R161 1 2 33_0402_5% HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15 USB30_TX1P
Internal Pull-up <31> AZ_SYNC_HD AZ_SYNC USB_SS_TX1P USB30_TX1P <28>
R162 1 2 33_0402_5% HDA_RST# AE4 G15 USB30_TX1N
<31> AZ_RST_HD# AZ_RST# USB_SS_TX1N USB30_TX1N <28>
1 @ 2 H_THERMTRIP#
R278 10K_0402_5%
USB_SS_RX1P
H13 USB30_RX1P
USB30_RX1P <28>
LP2
1 @ 2 EC_LID_OUT# G13 USB30_RX1N
USB_SS_RX1N USB30_RX1N <28>
R272 10K_0402_5%
1 2 FCH_PCIE_WAKE# T61 K19 J16 USB30_TX0P
3 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_TX0P <28> 3
R276 10K_0402_5% T19 J19 H16 USB30_TX0N
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_TX0N <28>
1 2 USB_OC0# J21
R318 10K_0402_5% SPI_CS2#/GBE_STAT2/GPIO166
USB_SS_RX0P
J15 USB30_RX0P
USB30_RX0P <28>
LP1
1 2 USB_OC1# K15 USB30_RX0N
USB_SS_RX0N USB30_RX0N <28>
R319 10K_0402_5%
1 2 FCH_SCLK1 D21
R288 10K_0402_5% (GPIO189/GPIO190) QMLE4: Detect UMA/PX C20 PS2KB_DAT/GPIO189 H19 R165 1 2 10K_0402_5%
1 2 FCH_SDATA1 (GPIO191) QMLE4: PXS_RST# D23 PS2KB_CLK/GPIO190 SCL2/GPIO193 G19 R167 1 2 10K_0402_5%
RF289 10K_0402_5% (GPIO192) QMLE4: PXS_PWREN C22 PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194 G22 R227 1 2 10K_0402_5%
PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 R228 1 2 10K_0402_5%
12/22 SMBus Not Implemented use 10k pull up SDA3_LV/GPIO196 E22
to +3VALW_PCH EC_PWM0/EC_TIMER0/GPIO197 H22
+3VS F21 EC_PWM1/EC_TIMER1/GPIO198 J22 EC_PWM2
E20 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 H21
EC_PWM2 <26> strap pin
1 2 FCH_SCLK0 F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
RF287 2.2K_0402_5% A22 KSO_2/GPIO211 K21
1 2 FCH_SDATA0 E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
RF291 2.2K_0402_5% A20 KSO_4/GPIO213 KSI_1/GPIO202 F22
1 @ 2 CLKREQ_WLAN# J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
R292 8.2K_0402_5% H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
1 @ 2 CLKREQ_LAN# G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
R290 8.2K_0402_5% B21 KSO_8/GPIO217 KSI_5/GPIO206 C24
1 2 WD_PWRGD K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
R320 10K_0402_5% D19 KSO_10/GPIO219 KSI_7/GPIO208
A18 KSO_11/GPIO220
C18 KSO_12/GPIO221
B19 KSO_13/GPIO222
+3VALW_FCH +3VS B17 KSO_14/GPIO223
A24 KSO_15/GPIO224
+3VS D17 KSO_16/GPIO225
KSO_17/GPIO226
2

Place R425 and C363 R312 R311

4 10K_0402_5% 10K_0402_5% 4
close to FCH for ESD 218-0755091 A13 HUDSON-M3L FCBGA 656P C38
@
2
1

Q32A M3LR1@
ODD_DA#_FCH 1 @ 2 ODD_DA#_Q 6 1
ODD_DA# <27>
1 R425 0_0402_5%
C363 2N7002KDWH_SOT363-6
0.1U_0402_16V4Z
2
@ Q32B in page14
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 24 of 47
A B C D E
 A B C D E

+3VS +1.1VS
L22 U2C
1007mA
1 2 +VDDPL_33_SYS +VCC_VDDCR_11 1 2
MBK1608221YZF_2P 102mA HUDSON-2 RF184 0_0805_5%

C181

2.2U_0402_6.3V6M

C182

0.1U_0402_16V7K

C183

0.1U_0402_16V7K

C184

0.1U_0402_16V7K

C185

1U_0402_6.3V6K

C186

1U_0402_6.3V6K

C177

10U_0603_6.3V6M
220 ohm +3VS 1 2 +VDDIO_33_PCIGP AB17 T14
VDDIO_33_PCIGP_1 VDDCR_11_1

22U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1 1 RF185 0_0603_5% AB18 T17 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2

C176

C178

C187

C179
AE9 T20

PCI/GPIO I/O
AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16
1 1 1 1
AG7 VDDIO_33_PCIGP_4 VDDCR_11_4 U18 (C117=>2.2uF// 22uF?)
2 2 AC13 VDDIO_33_PCIGP_5 VDDCR_11_5 V14 2 2 2 2 2
VDDIO_33_PCIGP_6 VDDCR_11_6

CORE S0
AB12 V17
2 2 2 2 AB13 VDDIO_33_PCIGP_7 VDDCR_11_7 V20
AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17
1 AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS 1
VDDIO_33_PCIGP_10 42ohm @ 100MHz
47mA 340mA
del +VDDPL_33_MLDAC power plane +VDDPL_33_SYS H24 H26 +1.1VS_CKVDD 1 2
VDDPL_33_SYS VDDAN_11_CLK_1 J25 RF187 0_0603_5%
20mA VDDAN_11_CLK_2

C189

0.1U_0402_16V7K

C190

0.1U_0402_16V7K

C191

1U_0402_6.3V6K

C192

1U_0402_6.3V6K

C193

22U_0603_6.3V6M
V22 K24

CLKGEN I/O
VDDPL_33_DAC VDDAN_11_CLK_3
demo board connect to GND
12mA L22 1 1 1 1 1
U22 VDDAN_11_CLK_4 M22
VDDPL_33_ML VDDAN_11_CLK_5 N21
30mA VDDAN_11_CLK_6 (C193=>2.2uF)
T22 N22
VDDAN_33_DAC VDDAN_11_CLK_7 P22 2 2 2 2 2
VDDPL_33_SSUSB_S 11mA VDDAN_11_CLK_8
+VDDPL_33_SSUSB_S L18
For Hudson3 USB3.0 only VDDPL_33_SSUSB_S
14mA
For Hudson2, connect to GND +VDDPL_33_USB_S D7 1088mA +1.1VS
VDDPL_33_USB_S AB24 +VDDAN_11_PCIE 42ohm @ 100MHz
11mA VDDAN_11_PCIE_1
+VDDPL_33_PCIE AH29 Y21 +VDDAN_11_PCIE 1 2
VDDPL_33_PCIE VDDAN_11_PCIE_2 AE25 R191 0_0805_5%
12mA

PCI EXPRESS
VDDAN_11_PCIE_3

C195

0.1U_0402_16V7K

C196

1U_0402_6.3V6K

C197

22U_0603_6.3V6M
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23
supply for the RGB outputs VDDAN_11_PCIE_5 1 1 1
@ AA22
1 2 M31 VDDAN_11_PCIE_6 AF26
C194 2.2U_0603_6.3V4Z LDO_CAP VDDAN_11_PCIE_7 AG27 (C197=>2.2uF//0.1uF//1uF)
VDDAN_11_PCIE_8 2 2 2
7mA
V21
VDDPL_11_DAC +1.1VS
1337mA
demo board connect to GND
AA21 +AVDD_SATA 42ohm @ 100MHz
VDDAN_11_SATA_1 Y20 1 2
del +FCH_VDDAN_33_DAC power plane 226mA VDDAN_11_SATA_4
Y22 AB21 R194 0_0805_5%
VDDAN_11_ML_1 VDDAN_11_SATA_2

C203

0.1U_0402_16V7K

C204

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

C206

22U_0603_6.3V6M
V23 AB22

SERIAL ATA
MAIN LINK
V24 VDDAN_11_ML_2 VDDAN_11_SATA_3 AC22
VDDAN_11_ML_3 VDDAN_11_SATA_5 1 1 1 1
V25 AC21
VDDAN_11_ML_4 VDDAN_11_SATA_6 AA20
VDDAN_11_SATA_7 AA18 (Add 22uF & 0.1uF?)
2 VDDAN_11_SATA_8 AB20 2 2 2 2 2
VDDAN_11_SATA_9 AC19
AB10 VDDAN_11_SATA_10 +3VALW_FCH
VDDIO_33_GBE_S
59mA
AB11 N18 +VDDIO_33_S 1 2
AA11 VDDCR_11_GBE_S_1 VDDIO_33_S_1 L19 RF195 0_0402_5%

GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2

C207

1U_0402_6.3V6K

C208

1U_0402_6.3V6K

C209

2.2U_0402_6.3V6M
M18
1 2 AA9 VDDIO_33_S_3 V12 1 1 1

3.3V_S5 I/O
R196 0_0402_5% AA10 VDDIO_GBE_S_1 VDDIO_33_S_4 V13
+3VALW_FCH VDDIO_GBE_S_2 VDDIO_33_S_5 Y12 (C207/C208=0.1uF?)
L21 VDDIO_33_S_6 Y13
470mA VDDIO_33_S_7 2 2 2
1 2 +VDDAN_33_USB G7 W11
VDDAN_33_USB_S_1 VDDIO_33_S_8
10U_0603_6.3V6M

10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805 H8
+3VALW_FCH VDDAN_33_USB_S_2 +3VALW_FCH
C212

C213

C214

1U_0402_6.3V6K

C215

1U_0402_6.3V6K

C290

0.1U_0402_16V7K
220 ohm/2A J8
L6 K8 VDDAN_33_USB_S_3 L14
1 1 1 1 1 VDDAN_33_USB_S_4 5mA
1 2+VDDPL_33_SSUSB_S K9 G24 +VDDXL_3.3V 1 2 +VDDXL_3.3V
MBK1608221YZF_2P M9 VDDAN_33_USB_S_5 VDDXL_33_S MBK1608221YZF_2P
VDDAN_33_USB_S_6 Tie to +3.3V_S5 rail if USB3 Wake
C198

2.2U_0402_6.3V6M

C200

0.1U_0402_16V7K

C217

2.2U_0402_6.3V6M
M10 220 ohm
220 ohm
Check Caps 2 2 2 2 2 N9 VDDAN_33_USB_S_7 is supported; otherwise, tie to
1 1
N10 VDDAN_33_USB_S_8 1 (Add 0.1uF?) +3.3V_S0 rail.
M12 VDDAN_33_USB_S_9 Hudson-2 designs: Tie to +3.3V_S0
N12 VDDAN_33_USB_S_10 rail.
2 2 M11 VDDAN_33_USB_S_11 2
+1.1VALW VDDAN_33_USB_S_12
L24 140mA +1.1VALW
1 2 +VDDAN_11_USB_S U12 187mA

USB
MBK1608221YZF_2P U13 VDDAN_11_USB_S_1 N20 +VDDCR_1.1V 1 2
VDDAN_11_USB_S_2 VDDCR_11_S_1
C219

2.2U_0402_6.3V6M

C220

0.1U_0402_16V7K
C234

0.1U_0402_16V7K

220 ohm M20 RF197 0_0603_5%

+3VALW_FCH VDDCR_11_S_2

C221

1U_0402_6.3V6K

C222

1U_0402_6.3V6K
1 1 1
L7 1 1
1 2 +VDDPL_33_USB_S @
MBK1608221YZF_2P
2 2 2
C210

2.2U_0402_6.3V6M

C211

0.1U_0402_16V7K

3 3
220 ohm 2 2
1 1
Add C234 follow AMD
+1.1VALW
L13
reccommandation 10/28 +1.1VALW
2 2
42mA
1 2 +VDDCR_11V_USB T12 70mA L15
MBK1608221YZF_2P T13 VDDCR_11_USB_S_1 J24 +VDDPL_11_SYS_S 1 2
VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C223

10U_0603_6.3V6M

C224

0.1U_0402_16V7K

C225

0.1U_0402_16V7K

220 ohm MBK1608221YZF_2P

0.1U_0402_16V7K
C226

2.2U_0402_6.3V6M

C228
1 1 1 220 ohm
1 1
+3VS
L23 (C223:10uF?) 2 2 2
1 2 +VDDPL_33_PCIE 2 2
MBK1608221YZF_2P
220 ohm +3VALW_FCH
+FCH_VDD_11_SSUSB_S
C218

2.2U_0402_6.3V6M

282mA 12mA
1 P16 M8 +VDDAN_33_HWM 1 2
1 R199 2 +VDDAN_11_SSUSB M14 VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S RF198 0_0402_5% AMD reply:
(Add 2.2uF?) 40mils VDDAN_11_SSUSB_S_2

C232

2.2U_0402_6.3V6M

C233

0.1U_0402_16V7K
0_0603_5% N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C229

1U_0402_6.3V6K

C230

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

P13 1 1 it to +3.3V_S5 directly if HWM is not used.

2 P14 VDDAN_11_SSUSB_S_4
1 1 1 VDDAN_11_SSUSB_S_5
USB SS

@ @
2 2
2 2 2
424mA
N16
+3VS N17 VDDCR_11_SSUSB_S_1 +3VS
L12 P17 VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3 26mA
1 2 +VDDPL_33_SATA M17 AA4 +VDDIO_AZ 1 2 VDDIO_AZ_S should be tied to
MBK1608221YZF_2P VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R200 0_0402_5% +3.3/1.5V_S5 rail if Wake on Ring
C227

2.2U_0402_6.3V6M

220 ohm POWER C236 1 2 2.2U_0402_6.3V6M is supported

1
4 2 L25 1 1 R237 2 +VDDCR_11_SSUSB 4
+1.1VALW 218-0755091 A13 HUDSON-M3L FCBGA 656P C38
0_0603_5%
(Add 2.2uF?) (Add 0.1uF?)
C237

10U_0603_6.3V6M

C238

1U_0402_6.3V6K

C239

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805 M3LR1@
2
42 ohm/4A 1 1 1 1

2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 25 of 47
A B C D E
 5 4 3 2 1

DEBUG STRAPS
U2E

HUDSON-2
STRAP PINS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
A3 T25
A33 VSS VSS T27
B7 VSS VSS U6
VSS VSS PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
B13 U14
D9 VSS VSS U17
D D13 VSS VSS U20 D
VSS VSS PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
E5 U21 PULL
E12 VSS VSS U30 HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PLL ILA PLL PCIE STRAPS MEM BOOT
E16 VSS VSS U32 STRAPS DISABLED HIGH AUTORUN
E29 VSS VSS V11 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
F7 VSS VSS V16
F9 VSS VSS V18
F11 VSS VSS W4
VSS VSS PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F13 W6
F16 VSS VSS W25 LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F17 VSS VSS W28 STRAP MODE ENABLED AUTORUN
F19 VSS VSS Y14 DEFAULT DEFAULT DEFAULT DEFAULT
F23 VSS VSS Y16
F25 VSS VSS Y18
F29 VSS VSS AA6 +3VALW_FCH +3VALW_FCH
G6 VSS VSS AA12
G16 VSS VSS AA13 +3VS +3VS +3VS +3VALW_FCH +3VALW_FCH
G32 VSS VSS AA14
VSS VSS

RF202 10K_0402_5%

RF203 10K_0402_5%

R204 10K_0402_5%

RF205 10K_0402_5%

RF206 10K_0402_5%

R207 10K_0402_5%

R208 10K_0402_5%
H12 AA16
H15 VSS VSS AA17
VSS VSS

1
H29 AA25
GROUND

J6 VSS VSS AA28

J9 VSS VSS AA30 @ @ @ @
VSS VSS <22> PCI_AD27
J10 AA32
C VSS VSS C
J13 AB25
<22> PCI_AD26

2
J28 VSS VSS AC6
J32 VSS VSS AC18
VSS VSS <22> PCI_AD25
K7 AC28
VSS VSS <22> PCI_CLK1
K16 AD27
VSS VSS <22> PCI_AD24
K27 AE6
VSS VSS <22> PCI_CLK3
K28 AE15
VSS VSS <22> PCI_AD23
L6 AE21
VSS VSS <22> PCI_CLK4
L12 AE28
L13 VSS VSS AF8
VSS VSS <22,33> CLK_PCI_EC

R209 2.2K_0402_5%

R210 2.2K_0402_5%

R211 2.2K_0402_5%

R212 2.2K_0402_5%

R213 2.2K_0402_5%
L15 AF12
VSS VSS

1
L16 AF16
VSS VSS <22,34> CLK_PCI_DDR
L21 AF33
M13 VSS VSS AG30 @ @ @ @ @
VSS VSS <24> EC_PWM2
M16 AG32
M21 VSS VSS AH5
<22,33> RTC_CLK

2
M25 VSS VSS AH11
VSS VSS R214 10K_0402_5%

R215 10K_0402_5%

R216 10K_0402_5%

R217 10K_0402_5%

R218 10K_0402_5%

R219 2.2K_0402_5%

R220 2.2K_0402_5%
N6 AH18
N11 VSS VSS AH19
VSS VSS
1

1
N13 AH21
N23 VSS VSS AH23
N24 VSS VSS AH25 @ @ @
P12 VSS VSS AH27
P18 VSS VSS AJ18
B B
2

2
P20 VSS VSS AJ28
P21 VSS VSS AJ29
P31 VSS VSS AK21
P33 VSS VSS AK25
R4 VSS VSS AL18
R11 VSS VSS AM21
R25 VSS VSS AM25
R28 VSS VSS AN1
T11 VSS VSS AN18
T16 VSS VSS AN28
T18 VSS VSS AN33
VSS VSS
N8 T21
VSSAN_HWM VSSPL_DAC L28
K25 VSSAN_DAC K33
VSSXL VSSANQ_DAC N28
H25 VSSIO_DAC
VSSPL_SYS R6
EFUSE

218-0755091 A13 HUDSON-M3L FCBGA 656P C38

A A
M3LR1@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 26 of 47
5 4 3 2 1

www.vinafix.vn
 A B C D E

SATA HDD Conn. SATA ODD Conn (for 14")

JHDD @
Close to JHDD
1
GND 2 SATA_FTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
RX+ SATA_FTX_DRX_P0 <23>
3 SATA_FTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
RX- SATA_FTX_DRX_N0 <23>
4
GND 5 SATA_FRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
TX- SATA_FRX_C_DTX_N0 <23>
6 SATA_FRX_DTX_P0 C370 1 2 0.01U_0402_25V7K JODD @
TX+ SATA_FRX_C_DTX_P0 <23>
7 1
GND GND 2 SATA_FTX_14C_DRX_P1
A+ 3 SATA_FTX_14C_DRX_N1
A- 4
GND 5 SATA_FRX_14_DTX_N1
1 8 B- 6 SATA_FRX_14_DTX_P1 1
3.3V +3VS B+
9 7
3.3V 10 GND
3.3V 11 8 ODD_PLUGIN#
GND DP ODD_PLUGIN# <24>
12 9 +5VS_ODD
GND 13 +5V 10 +5VS_ODD
GND +5V 1 Place components closely ODD CONN.
14 11 ODD_DA# C365 1.6A
5V +5VS MD ODD_DA# <24>
15 14 12 0.1U_0402_10V7K
5V 16 15 GND1 GND 13 @
5V GND2 GND 1 2 1 1 1 1 1
17 C364 C352 C353 C354
GND 18 SANTA_206001-1 @ @ C355 C360
Reserved 19 220P_0402_50V6K 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V6K 0.1U_0402_10V7K
23 GND 20 2 2 2 2 2 2
24 GND 12V 21 0.1U_0402_10V7K
GND 12V 22 +5VS
12V Place closely JHDD SATA CONN. 5/16 Change C364 to 220p for ESD request
1.2A
SUYIN_127043FB022G278ZR
1 1 1 1
C356 C357 C358 C359
10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
2 2 2 2

SATA ODD Conn (for 15")

2 2

@ JODDC

14 12
13 G2 12 11 SATA_FTX_14C_DRX_P1
G1 11 10 SATA_FTX_14C_DRX_N1
10 9
JODDB @ 9 8 SATA_FRX_14_DTX_N1
1 8 7 SATA_FRX_14_DTX_P1
1 2 SATA_FTX_C_DRX_P1 C391 1 2 0.01U_0402_25V7K SATA_FTX_DRX_P1 7 6
2 SATA_FTX_DRX_P1 <23> 6
3 SATA_FTX_C_DRX_N1 C390 1 2 0.01U_0402_25V7K SATA_FTX_DRX_N1 5
3 SATA_FTX_DRX_N1 <23> 5
4 4
4 5 SATA_FRX_DTX_N1 C389 1 2 0.01U_0402_25V7K SATA_FRX_C_DTX_N1 4 3
5 SATA_FRX_C_DTX_N1 <23> 3
6 SATA_FRX_DTX_P1 C398 1 2 0.01U_0402_25V7K SATA_FRX_C_DTX_P1 2
6 SATA_FRX_C_DTX_P1 <23> 2
7 1
7 8 ODD_PLUGIN# 1
8 9
9 +5VS_ODD
10 ACES_50504-0120N-001
10 11 ODD_DA#
11 12
12 13
GND 14
GND
ACES_88058-120N

3 3

Power Button & RUSB connector

For debug USB20_P1 1 @ 2 USB20_P1_R USB20_P0 1 @ 2 USB20_P0_R
<24> USB20_P1 <24> USB20_P0
RR48 0_0402_5% RR31 0_0402_5%
+3VL LR8 LR7
JUSIO SW5 4 3 4 3
1 1 2 4 3 4 3
1
2

2 USB20_P1_R
2 3 USB20_N1_R 3 4 R397 1 2 1 2
3 Place on TOP 1 2 1 2
4
G
G

4 5 USB20_P0_R NTC017-DA1J-D160T_4P 100K_0402_5% WCM-2012-900T_0805 WCM-2012-900T_0805

6
5

5 6 USB20_N0_R USB20_N1 1 @ 2 USB20_N1_R USB20_N0 1 @ 2 USB20_N0_R

<24> USB20_N1 <24> USB20_N0
1

6 7 ON/OFFBTN# RR47 0_0402_5% RR30 0_0402_5%

7 @

1
8 ON/OFFBTN#
8 ON/OFFBTN# <33> R71 R72
9 +5VS_PWR_ON_LED 2 1 +5VS 1
9 10 R29 C473 300_0402_5% 300_0402_5%
10 +USB_VCCA
11 0_0603_5% 0.1U_0402_25V6 @ @
11 12 @
2

2
12 13 2
GND 1 1
14 C289 C297
GND
10P_0402_50V8J 10P_0402_50V8J
ACES_88058-120N
@ For EMI request 2@ 2@
4 +5VALW W=80mils 4
2.5A +USB_VCCA
For EMI
U14
2 6 2 1 Reserved for EHCI CRC errors Reserved for EHCI CRC errors
3 IN OUT 7 C373 1000P_0402_50V7K
USB_EN# 4 IN OUT 8
<28,33> USB_EN# EN/ENB OUT
1 5 USB_OC0# <24>
GND OCB
SY6288DCAC_MSOP8
1 Security Classification Compal Secret Data Compal Electronics, Inc.
SA00004KB00 C362 2012/05/18 2013/10/05 Title
4.7U_0805_10V4Z
Issued Date Deciphered Date
SA00003TV00 2@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 27 of 47
A B C D E
 5 4 3 2 1

+USB_VCCB
+5VALW USB20_DN10 1 2 USB20_N10
RR44 0_0402_5%
W=80mils
USB20_DP10 1 2 USB20_P10 +5VALW W=60mils 4.7U_0805_10V4Z 0.1U_0402_10V7K
2.5A
1
RR45 0_0402_5% +USB_VCCB
For EMI 1
RB73 U48 1 1 1
4.7K_0402_5% 2 6 2 1 + CR40 CR42 CR41 CR43
@ 3 IN OUT 7 C361 1000P_0402_50V7K
U15 @ USB_CHG_EN# 4 IN OUT 8
<33> USB_CHG_EN#
2
CEN 1 8 SLP_CHG# 1 EN/ENB OUT 5 2 2 2 2
CEN CB SLP_CHG# <23> GND OCB USB_OC1# <24>
USB20_DN10 2 7 USB20_N10 1
DM TDM USB20_N10 <24>
1

USB20_DP10 3 6 USB20_P10 SY6288DCAC_MSOP8 220U_6.3V_M 1000P_0402_50V7K

DP TDP USB20_P10 <24>
RB74 SELCDP 4 5 +5VALW SA00004KB00 CR39
4.7K_0402_5% 9 SELCDP VDD 4.7U_0805_10V4Z
D D
@ Thermal Pad SA00003TV00 2@
SLG55584AVTR_TDFN8_2X2 +USB_VCCC
1 1
2

CB25 CB49 W=80mils

0.1U_0402_16V7K 10U_0603_6.3V6M
PJ30
@ @ 4.7U_0805_10V4Z 0.1U_0402_10V7K
2 2 2 1 @
2 1 1
1 1 1
+5VALW PAD-OPEN 2x2m + CR47 CR46 CR45 CR44
Q8 @
@
1 3 2 2 2 2

S
+USB_VCCC +USB_VCCB
Pull-up for SLGC55584AV
1

AO3413_SOT23 220U_6.3V_M 1000P_0402_50V7K

RB75 1 @ 2

G
+5VALW

2
4.7K_0402_5% R568 100K_0402_5%
@
USB_EN#
<27,33> USB_EN#
2

JUSBA
SELCDP USB30_TX0P_C_L 9 Support S/C
1 SSTX+
+USB_VCCB VBUS
USB30_TX0N_C_L 8
SSTX-
1

USB20_DP10 1 @ 2 USB20_P10_L USB20_P11 1 @ 2 USB20_P11_L USB20_N10_L 2

<24> USB20_P11 D-
RB76 RR26 0_0402_5% RR39 0_0402_5% 7
4.7K_0402_5% LR3 WCM-2012-900T_0805 USB20_P10_L 3 GND 10
@ 4 3 4 3 USB30_RX0P_L 6 D+ GND 11
4 3 4 3 4 SSRX+ GND 12
2

USB30_RX0N_L 5 GND GND 13

1 2 1 2 SSRX- GND
1 2 1 2 OCTEK_USB-09EAEB
WCM-2012-900T_0805 LR4 @
USB20_DN10 1 @ 2 USB20_N10_L USB20_N11 1 @ 2 USB20_N11_L
<24> USB20_N11
RR25 0_0402_5% RR38 0_0402_5%

1
C C

SLP_CHG# SELCDP Function R76 R77

300_0402_5% 300_0402_5% JUSBB
DCP autodetect with @ @ USB30_TX1P_C_L 9
1 SSTX+
0 X mouse/keyboard wakeup +USB_VCCC
2

2
USB30_TX1N_C_L 8 VBUS
1 1 SSTX-
C303 C304 USB20_N11_L 2
7 D-
1 0 S0 charging with SDP only 10P_0402_50V8J 10P_0402_50V8J GND
USB20_P11_L 3 10
2@ 2@ USB30_RX1P_L 6 D+ GND 11
4 SSRX+ GND 12
1 1 S0 charging with CDP or SDP only GND GND
USB30_RX1N_L 5 13
SSRX- GND
Reserved for EHCI CRC errors Reserved for EHCI CRC errors OCTEK_USB-09EAEB
@

USB30_RX0P 1 @ 2 USB30_RX0P_L
<24> USB30_RX0P
RR19 0_0402_5%
KINGCORE WCM-2012HS-670T
1 2
1 2

4 3
4 3 DR7 @
LR1 USB30_TX0P_C_L 1 1 109 USB30_TX0P_C_L
USB30_RX0N 1 @ 2 USB30_RX0N_L
<24> USB30_RX0N DR1
RR20 0_0402_5% @ USB30_TX0N_C_L 2 2 98 USB30_TX0N_C_L
USB20_P10_L 2
1 2 USB30_TX0P_C 1 @ 2 USB30_TX0P_C_L 2 1 USB30_RX0P_L 4 4 77 USB30_RX0P_L
<24> USB30_TX0P 1
CB21 0.1U_0402_16V7K RR32 0_0402_5% USB20_N10_L 3
KINGCORE WCM-2012HS-670T 3 USB30_RX0N_L 5 5 6 6 USB30_RX0N_L
B B
1 2
1 2 AZC199-02SPR7G_SOT23-3 3 3

4 3 8
4 3
LR2 YSCLAMP0524P_SLP2510P8-10-9
Change ESD Diode for EMI request
<24> USB30_TX0N 1 2 USB30_TX0N_C 1 @ 2 USB30_TX0N_C_L
CB22 0.1U_0402_16V7K RR22 0_0402_5%

DR8 @
USB30_RX1P 1 @ 2 USB30_RX1P_L USB30_TX1P_C_L 1 1 109 USB30_TX1P_C_L
<24> USB30_RX1P
RR42 0_0402_5%
KINGCORE WCM-2012HS-670T DR4
@ USB30_TX1N_C_L 2 2 98 USB30_TX1N_C_L
1 2 USB20_P11_L 2
1 2 2 1 USB30_RX1P_L 4 4 77 USB30_RX1P_L
USB20_N11_L 3 1
4 3 3 USB30_RX1N_L 5 5 6 6 USB30_RX1N_L
4 3
LR5 AZC199-02SPR7G_SOT23-3 3 3
USB30_RX1N 1 @ 2 USB30_RX1N_L
<24> USB30_RX1N 8
RR40 0_0402_5%

<24> USB30_TX1P 1 2 USB30_TX1P_C 1 @ 2 USB30_TX1P_C_L Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9
CB23 0.1U_0402_16V7K RR43 0_0402_5%
KINGCORE WCM-2012HS-670T
1 2
1 2

4 3
4 3
LR6
<24> USB30_TX1N 1 2 USB30_TX1N_C 1 @ 2 USB30_TX1N_C_L
A A
CB24 0.1U_0402_16V7K RR41 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 28 of 47
5 4 3 2 1
 +3V_WLAN
40 mils +1.5VS_WLAN
For SED
For SED
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Slot 1 Half PCIe Mini Card-WLAN 1 1 1 1 1 1

1
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254
47P_0402_50V8J @ @ @ 47P_0402_50V8J

2
2 2 2 @ 2 2 2 @ WLAN&BT Combo module circuits
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
BT BT
on module on module
1 2
RM20 0_0402_5% Enable Disable
+3V_WLAN
4/23 Add RM20 and change UM5,RM21 to @
BT_ON H L
Add WLAN_RST# on DVT

5
UM5
1 @

P
<11,22,30,32> APU_PCIE_RST# IN1 +1.5VS
4 WLAN_RST#_R
2 O
<33> WLAN_RST# IN2

2
RM21 1 R328 2 E51_RXD_R
<33> BT_ON

1
SN74AHC1G08DCKR_SC70-5 100K_0402_5% 1K_0402_5%

3
@ PJ33
PAD-OPEN 2x2m For isolate BT_CTRL and
@ Compal Debug Card.

1
WLAN_RST# 1 2
RM19 0_0402_5%

2
@
+1.5VS_WLAN
+3V_WLAN

@ JWLAN
R1443 1 2
0_0402_5% 3 1 2 4
BT_ON 1 2BT_CTRL_R 5 3 4 6
7 5 6 8
<24> CLKREQ_WLAN# 7 8
9 10
11 9 10 12
<22> CLK_PCIE_WLAN# 11 12
13 14
<22> CLK_PCIE_WLAN 13 14
15 16
15 16
R27
+3VALW TO +3V_WLAN
17 18 0_0402_5%
19 17 18 20 WLAN_OFF# 1 @ 2
19 20 WL_OFF# <33> +3VS
21 22 WLAN_RST#_R
23 21 22 24
<22> PCIE_FRX_WLANTX_N1 23 24 +3VS
25 26 Vgs=-4.5V,Id=3A,Rds<97mohm
<22> PCIE_FRX_WLANTX_P1 25 26
27 28
29 27 28 30
29 30 FCH_SCLK0 <9,10,24>

1
31 32 FCH_SDATA0 <9,10,24> 2
<22> PCIE_FTX_C_WLANRX_N1 31 32
33 34 R156
<22> PCIE_FTX_C_WLANRX_P1 33 34

2
35 36 USB20_N8 <24> 100K_0402_5% C907
37 35 36 38 @ 0.1U_0402_10V7K PJ27
WLAN/ WiFi USB20_P8 <24>BT

2
39 37 38 40 1@
+3V_WLAN JUMP_43X79

2
39 40

3
S
41 42 R155@ @
41 42 R75

1
G
43 44 1 2 2 Q210
43 44 <33> WLAN_PWR#
45 46 300_0402_5% AO3413_SOT23

1
R18 47 45 46 48 @ 47K_0402_5% D @
2

1
10_0402_5%2 E51_TXD_R 49 47 48 50 @
<33> E51_TXD
2

1 2 E51_RXD_R 51 49 50 52 C908 +3V_WLAN

<33> E51_RXD 51 52 1
0_0402_5% 53 54 C302 0.01U_0402_25V7K
R28 G1 G2 1
10P_0402_50V8J
Debug card using Add WLAN power circuit on DVT
@ BELLW_80003-7041 2@

Change JWLAN symbol to 4/23 Change R156,R155,C907,C908,Q210 to @

SP07000TB00 on DVT Reserved for EHCI CRC errors

Green Clock Generator

+3VL +3V_LAN +3VALW_FCH +1.8VS
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1 1 1 1
CCL1 CCL2 CCL3 CCL7
GCLK@ GCLK@ GCLK@ GCLK270@ 1
2 2 2 2 CCL6
1
CCL12 2.2U_0603_6.3V6K
22U_0805_6.3V6M UCL1 GCLK270@ 2
GCLK@
GCLK@
2 10 14
+RTCBATT VBAT VDD_RTC_OUT +RTCBATT_D

+3VL 15
+V3.3A
+3VALW 2
VDD 9 FCH_RTCX1_R_R 1 2
32kHz FCH_RTCX1_R <22>
RCL1 GCLK@ 0_0402_5%

+1.8VS 11 12 VGA_X1_R 1 2
VDDIO_27M 27MHz VGA_X1 <12>
RCL4 GCLK270@ 33_0402_5%
+3V_LAN 8 6 LAN_X1_R_R 1 2
VDDIO_25M_A 25MHz_A LAN_X1_R <30>
RCL3 GCLK@ 33_0402_5% 1
+3VALW_FCH 1 2 3 5 FCH_X1_R_R 1 2
VDDIO_25M_B 25MHz_B FCH_X1_R <22>
RCL10 0_0402_5% RCL2 GCLK@ 33_0402_5% CCL10
CLK_X1 1 5P_0402_50V8C
1 @ 2 CLK_X2 16 XTAL_IN 2
+3VS XTAL_OUT
GND1
GND2
GND3

GND4

RCL11 0_0402_5%
For EMI
SLG3NB270VTR_TQFN16_2X3
4
7
13

17

4/23 Change UCL1.2 to +3VALW, UCL1.14 to +RTCVCC_D and

LAN_X1_R_R 1 @ 2
GCLK@ add RCL10,RCL11 for USB30 wake issue RCL5 0_0402_5%
YCL1 25MHZ 12PF X3G025000DK1H-X

CLK_X1 1 3 CLK_X2
1 3
GND GND Reserved for Swing Level adjustment
1 1
For UMA ( Close GCLK side )
CCL4 2 4 CCL5 UCL1
18P_0402_50V8J 18P_0402_50V8J
GCLK@ GCLK@
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SLG3NB238VTR_TQFN16_2X3
GCLK238@ SCHEMATIC, MB A8868
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 29 of 47
 A B C D E

UL1 +3V_LAN CL3 to CL6 close to Pin 27,39,47,48

Add test point +LAN_VDD10 CL7 to CL8 close to Pin 12,42
<22> PCIE_FRX_C_LANTX_P0 CL1 1 2 0.1U_0402_10V7K PCIE_FRX_LANTX_P0 22 31 for pin37 on DVT
HSOP LED3/EEDO 37 LL1
8111FVB@ 1 2
LED1/EESK TL1
<22> PCIE_FRX_C_LANTX_N0 CL2 1 2 0.1U_0402_10V7K PCIE_FRX_LANTX_N0 23 40 +LAN_REGOUT 1 2 CL3 0.1U_0402_10V7K
HSON LED0 2.2UH +-5% NLC252018T-2R2J-N 1 2
PCIE_FTX_C_LANRX_P0 17 30 RL2 2 @ 1 10K_0402_5% 1 1 CL4 0.1U_0402_10V7K
<22> PCIE_FTX_C_LANRX_P0 HSIP EECS
LAN_EN PCIE_FTX_C_LANRX_N0 18 32 RL1 2 @ 1 10K_0402_5% Layout Note: LL1 must be 1 2
<24> LAN_EN <22> PCIE_FTX_C_LANRX_N0 HSIN EEDI

2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_10V7K

G
2N7002_SOT23-3 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_10V7K 1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ 200mil to LL1 8111FVB@ 2 2 8111FVB@ CL6 0.1U_0402_10V7K
<24> CLKREQ_LAN# CLKREQB MDIP0
QL53 2 LAN_MDI0- 1 2

S
APU_PCIE_RST# 25 MDIN0 4 LAN_MDI1+ 8111FVB@ CL7 0.1U_0402_10V7K
1 <11,22,29,32> APU_PCIE_RST# PERSTB MDIP1 1
5 LAN_MDI1- 1 2
19 MDIN1 7 LAN_MDI2+ 8111FVB@ CL8 0.1U_0402_10V7K
<22> CLK_PCIE_LAN REFCLK_P NC/MDIP2
20 8 LAN_MDI2-
<22> CLK_PCIE_LAN# REFCLK_N NC/MDIN2
1 @ 2 10 LAN_MDI3+
RL28 0_0402_5% NC/MDIP3 11 LAN_MDI3-
LAN_X1 43 NC/MDIN3
4/23 Mount QL53 and RL24 and change RL28,RL26 CKXTAL1 +LAN_VDD10 +LAN_EVDD10
+3VS to @ for LAN disable LAN_X2 44 13 +LAN_VDD10
+LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
RL24 2 1 10K_0402_5% LANCLK_REQ# CKXTAL2 DVDD10 29 1 2 CL22 close to pin 3, respectively
DVDD10 41 LL2 0_0603_5%
DVDD10 CL23,CL24,CL25 close to pin 6,9,41, respectively
FCH_PCIE_WAKE# 28 1 1
<24> FCH_PCIE_WAKE# LANWAKEB 1 2
+3V_LAN ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
RL25 2 @ 1 10K_0402_5% FCH_PCIE_WAKE# 39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
14 12 +3V_LAN 1 2
RL21 2 @ 1 10K_0402_5% 15 NC/SMBCLK AVDD33 42 CL21 0.1U_0402_10V7K
RL22 1 @ 2 1K_0402_5% 38 NC/SMBDATA AVDD33 47 1 2
+3V_LAN GPO/SMBALERT AVDD33 Close to Pin 21
48 8111FVB@ CL22 0.1U_0402_10V7K
AVDD33 1 2
ENSWREG 33 8111FVB@ CL23 0.1U_0402_10V7K
+3VS LAN_EN 1 @ 2 ENSWREG 21 +3V_LAN +LAN_VDDREG 1 2
EVDD10 +LAN_EVDD10
RL26 0_0402_5% +LAN_VDDREG 34 8111FVB@ CL24 0.1U_0402_10V7K
35 VDDREG 3 1 2 1 2
VDDREG AVDD10 +LAN_VDD10
6 8111FVB@ LL3 0_0603_5% 1 1 8111FVB@ CL25 0.1U_0402_10V7K
AVDD10
1

9
1 2 46 AVDD10 45 CL28 CL29
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10 4.7U_0603_6.3V6K 0.1U_0402_10V7K
RL6 24 36 +LAN_REGOUT 8111FVB@ 2 2 8111FVB@
@ 49 GND REGOUT
60 mils
2

PGND
For P/N and footprint
ISOLATE# 1 2 WOL_EN#
2 RL433 0_0402_5% RTL8111F-CGT_QFN48_6x6
Please place them to ISPD page 2
Placement near to YL1
8111FVB@

RL8 GCLK@ UL1

RL7 1 2 LAN_X2
<29> LAN_X1_R
15K_0402_5% RTL8105E RTL8111E/F 0_0402_5%
Sx Enable Sx Disable S0
Wake up Wake up Pin14 NC NC CL43 10PF_0402_50V9 8105E-VL/VD 8105E-VL/VD
1 2 1 2 +3V_LAN
8111F/F-VB
Pin15 NC 10K ohm PD RL29 22_0402_5% 8105E-VD 10/100M
GCLK@ GCLK@
PWM Mode LDO Mode 8105ELDO@
WOL_EN# LOW HIGH HIGH

1
Pin38 NC 1K ohm PH RL4 0 ohm NC
RL4 (Pull High)
0_0402_5%
8111FVB@ NC 0 ohm
+3VALW TO +3V_LAN Reserve +3VALW_FCH NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL23 (Pull Down)

2
ENSWREG
Vgs=-4.5V,Id=3A,Rds<97mohm to +3V_LAN for saving LAN_X1 1 3 LAN_X2
1 3

1
+3VALW power consumption on DVT
GND GND RL23
+3VALW +3VALW_FCH 0_0402_5%
1 2 4 1
CL26 CL27 8105ELDO@
27P_0402_50V8J 27P_0402_50V8J

2
1

2 NOGCLK@ NOGCLK@
RL147 CL483 2 2
100K_0402_5% @
2
PAD-OPEN 2x2m

@ 0.1U_0402_10V7K
2

1 PJ31
2
2

S
@ RL432 @ QL51 PJ29 @
LAN Conn.
2

G
1 2 2 JUMP_43X39
<33> WOL_EN#
1

@
+3V_LAN
1

47K_0402_5% 2 AO3413_SOT23 D
1

3 @ JRJ45 @ 3
1

CL482 RJ45_MIDI0+ 1
PR1+
0.01U_0402_25V7K
1 UL3 RJ45_MIDI0- 2
2 PR1-
1
CL682 LAN_MDI1+ 1 16 RJ45_MIDI1+ RJ45_MIDI1+ 3 For ESD
TD+ TX+ PR2+

1
CL681 1U_0402_6.3V6K LAN_MDI1- 2 15 RJ45_MIDI1- CL39 1000P_0402_50V7K
4.7U_0805_10V4Z 1 3 TD- TX- 14 2 1 1 2 RJ45_MIDI2+ 4 D92

1
@ 2 4 CT CT 13 RL11 75_0402_1% PR3+
NC NC AZC199-02SPR7G_SOT23-3
5 12 CL40 1000P_0402_50V7K RJ45_MIDI2- 5
NC NC PR3-

3
6 11 2 1 1 2
LAN_MDI0+ 7 CT CT 10 RJ45_MIDI0+ RL12 75_0402_1% RJ45_MIDI1- 6

3
LAN_MDI0- 8 RD+ RX+ 9 RJ45_MIDI0- PR2-
RD- RX- RJ45_MIDI3+ 7 9
Reserve ESD for LAN on DVT PR4+ GND 10
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. 10/100M transformer_NS681695 RJ45_MIDI3- 8 GND
D99 @ UL4 8111FVB@ PR4-

2
LAN_MDI1+ 6 3 LAN_MDI0+ SANTA_130452-S
I/O4 I/O2 LAN_MDI2+ 1 16 RJ45_MIDI2+ 8111FVB@ D93
LAN WOL
LAN_EN ISOLATEB

2
LAN_MDI2- 2 TD+ TX+ 15 RJ45_MIDI2- CL41 1000P_0402_50V7K 8111FVB@
TD- TX- AZC199-02SPR7G_SOT23-3
S0 Sx S0 Sx 3 14 2 1 1 2 @
CT CT

1
+3V_LAN 5 2 4 13 RL13 75_0402_1%
VDD GND NC NC
---------------------------------------------- 5 12 CL42 1000P_0402_50V7K

1
6 NC NC 11 2 1 1 2
CT CT For ESD
0 0 0 0 1 1 LAN_MDI3+ 7
RD+ RX+
10 RJ45_MIDI3+ RL15 75_0402_1%
LAN_MDI1- 4 1 LAN_MDI0- LAN_MDI3- 8 9 RJ45_MIDI3- 8111FVB@ 8111FVB@
0 1 0 0 1 1 I/O3 I/O1 RD- RX-
AZC099-04S.R7G_SOT23-6
1 0 1 1 1 1 10/100M transformer_NS681695
1 1 1 1 1 0* 1 RJ45_GND 1 2 LANGND
D100 @ CL36 1000P_1808_3KV7K 1 1
LAN_MDI2+ 6 3 LAN_MDI3+ CL34 CL37 CL38
4 I/O4 I/O2 0.1U_0402_25V6 @ 4
* 2
2
220P_0402_50V6K
2
4.7U_0603_6.3V6K
Place CL34 colse
S3: after SUSP# assert low over 100ms +3V_LAN 5
VDD GND
2 to LAN chip
S4/S5: after SYSON assert low over 100ms
LAN_MDI2- 4 1 LAN_MDI3-
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 30 of 47
A B C D E
 A B C D E

35mA for 3.3V level

close to pin 25 close to pin 38 RA18
UA1 +3VS 1 2 0.1U_0402_16V4Z +DVDD_IO +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 2 +5VS
RA28 0_0603_5% 2 1 2 1 1 0_0603_5%
MIC1_R_R 4.7U_0603_6.3V6K CA58 MIC1_R_C_R 22 1 +DVDD_IO 2 1
MIC1_R_L 4.7U_0603_6.3V6K CA57 MIC1_R_C_L 21 MIC1_R DVDD 9 +3VS_DVDD CA4 CA42 CA47 CA37 CA50 CA39
MIC1_L DVDD_IO CA3 @ 10U_0603_6.3V6M
MIC2_R 17 25 +AVDD 1 2 1 2 2
MIC2_L 16 MIC2_R AVDD1 38 +AVDD 1 2 10U_0603_6.3V6M 10U_0603_6.3V6M
MIC2_L AVDD2 10U_0603_6.3V6M
+MIC1_VREFO_L 31 39 +PVDD 0.1U_0402_16V4Z
30 MIC1_VREFO_L PVDD1 46 +PVDD 1 2 +3VS_DVDD LA7
+MIC1_VREFO_R MIC1_VREFO_R PVDD2 +3VS
+MIC2_VREFO 29 RA17 0_0603_5% 2 1 +PVDD 1 2 0.1U_0402_10V7K +5VS
1 MIC2_VREFO 1
1 2 PBY160808T-601Y-N_2P 1

1
15 45 SPKR+ CA5 CA45 CA36 0.1U_0402_10V7K
14 LINE2_R SPK_OUT_R+ 44 SPKR- CA40 CA41 CA43
LINE2_L SPK_OUT_R- 1 2 10U_0805_6.3V6M
close to pin39

2
10U_0603_6.3V6M 2 1 2
20 40 SPKL+ 10U_0603_6.3V6M
MONO_OUT SPK_OUT_L+ 41 SPKL-
1 2 MONO_IN 12 SPK_OUT_L-
PCBEEP place close to chip
CA59 100P_0402_50V8J 75_0402_1% 1
0.01U_0402_25V7K 10 33 RA19 HP_R <32> CA38 0.1U_0402_10V7K
<24> AZ_SYNC_HD SYNC HPOUT_R
@ CA65 1 2 32 RA20
11 HPOUT_L 75_0402_1% HP_L <32>
<24> AZ_RST_HD# RESET# 2
close to pin19 5 AZ_SDOUT_HD <24>
SDATA_OUT 8 AZ_SDIN0_HD_R 2 1
close to pin 28 SDATA_IN AZ_SDIN0_HD <24>
2 RA34 1AC_JDREF 19 RA26 33_0402_5%
10U_0603_6.3V6M1 2CA60 20K_0402_1% 28 JDREF 6 AZ_BITCLK_HD
LDO_CAP BCLK AZ_BITCLK_HD <24>
27
2 1CPVEE 34 VREF
AC_VREF CA54 2.2U_0603_10V6K 35 CPVEE 23 @ CA51
CBN NC For EMI
1 1 2 1 36 24 AZ_BITCLK_HD 2 1 1 2 @
CA53 2.2U_0603_10V6K CBP NC 48 10_0402_5% RA29 please place near codec
CA55 CA56 NC 10P_0402_50V8J
2.2U_0603_6.3V6K <19> INT_MIC_DATA 2
2 2 @ INT_MIC_CLK_R 3 GPIO0/DMIC_DATA 26
0.1U_0402_10V7K GPIO1/DMIC_CLK AVSS1 37
AVSS2 42
SENSE_A 13 PVSS1 43
2 @ 1 SENSE_B 18 SENSE_A PVSS2 7
RA40 20K_0402_1% SENSE_B DVSS
47 AGND EC Beep
2 <33> EC_MUTE#
4 EAPD
PD# Thermal Pad
49
<33> EC_BEEP#
1 RA7 2 Beep sound 2
47K_0402_5%

For EMI ALC259-VC2-CG_MQFN48_6X6

RA42 PCI Beep CA13

INT_MIC_CLK_R 1 RA8 2 1 2 MONO_IN
<19> INT_MIC_CLK <24> FCH_SPKR
FBMA-10-100505-301T
CAM@ DGND 47K_0402_5%
0.1U_0402_10V7K
1
EC_MUTE# Internal AMP
CA52 CAM@ Hight Enable
220P_0402_50V7K LOW Disable

2
2
RA12 CA18
4.7K_0402_5% 100P_0402_50V8J

1
EC_MUTE#
2W 4ohm =40mil placement near Audio Codec

2
+MIC2_VREFO
1W 8ohm =20mil
Analog MIC SPKL+ 2
RA30
1 SPK_L1
RA50
4.7K_0402_5%
0_0603_5% 2
CA32 To solve noise issue

1
@ 2
1

10U_0603_6.3V6M CA30
RA27 1 1U_0402_6.3V4Z
4.7K_0402_5% 2 @
CA35 1
AMIC@ Change int. MIC
@
2

to MB on DVT RA31 10U_0603_6.3V6M

AMIC@ AMIC@ SPKL- 2 1 1 SPK_L2
3 CA26 RA38 JMIC 0_0603_5% 3
MIC2_L 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% INT_MIC 1
2 1 SPKR+ 2
RA32
1 SPK_R1
Ext.MIC/LINE IN JACK
2 0_0603_5% 2
CA27 3 CA33
MIC2_R 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% 1 2 4 GND @ RA22
CA28 RA39 220P_0402_50V7K GND 10U_0603_6.3V6M RA23 2 1
1 2 +MIC1_VREFO_R
AMIC@ AMIC@ AMIC@ ACES_50271-0020N-001 CA31 1K_0402_5% 2.2K_0402_5%
@ 2 1U_0402_6.3V4Z MIC1_R_R 2 1
MIC1_R <32>
close to Codec CA34 @
@ 1
1 1
CA7 CA6 RA33 10U_0603_6.3V6M MIC1_R_L 2 1
1 MIC1_L <32>
SPKR- 2 1 SPK_R2 1K_0402_5%
470P_0402_50V8J 470P_0402_50V8J 0_0603_5% RA24 2 1 +MIC1_VREFO_L
2 2 2.2K_0402_5%
4/23 Add CA6,CA7 for EMI request RA25

4/23 Add CA64,CA67,CA68,CA77 for EMI request

SPK Conn.
@ DA9 AZ5125-02S.R7G_SOT23-3
CA64 1 2 0.1U_0603_50V7K 2
Sense Pin Impedance Codec Signals Function CA63 1 2 0.1U_0603_50V7K 1
place close to chip @ 3
39.2K PORT-I (PIN 32, 33) Headphone out CA61 1 2 0.1U_0603_50V7K CA67 1 2 0.1U_0603_50V7K
<32> MIC_SENSE 2 1 SENSE_A @ JSPK
RA37 20K_0402_1% CA66 1 2 0.1U_0603_50V7K SPK_R1 1
SPK_R2 2 1
20K PORT-B (PIN 21, 22) Ext. MIC CA62 1 2 0.1U_0603_50V7K SPK_L1 3 2
SENSE A SPK_L2 4 3
1 2 4
4
10K PORT-C (PIN 23, 24) @ ACES_85204-0400N 4
<32> NBA_PLUG
RA36 39.2K_0402_1% RA35 0_0603_5% CA77 1 2 0.1U_0603_50V7K 2 @
5.1K (PIN 48) 1
@ 3
CA68 1 2 0.1U_0603_50V7K
39.2K PORT-E (PIN 14, 15) DA8 AZ5125-02S.R7G_SOT23-3
@

SENSE B 20K PORT-F (PIN 16, 17) Analog MIC

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 31 of 47
A B C D E
 5 4 3 2 1

CardReader Conn.

D D
ACES_88058-120N
14 1 2 USB20_P7_R
<24> USB20_P7
@ RR1 13 GND RR67 0_0402_5%
+3VS 1 2 +3VS_CR 12 GND LR9 @
11 12 4 3
0_0603_5% USB20_N7_R 10 11 4 3
USB20_P7_R 9 10
8 9 1 2
HP_R 7 8 1 2
<31> HP_R
HP_L 6 7 WCM-2012-900T_0805
<31> HP_L
5 6 1 2 USB20_N7_R
<24> USB20_N7
MIC1_L 4 5 RR66 0_0402_5%
<31> MIC1_L
3 4

1
MIC1_R
<31> MIC1_R
MIC_SENSE 2 3 R74
<31> MIC_SENSE
NBA_PLUG 1 2 300_0402_5%
<31> NBA_PLUG 1 @
@ JCRIO

2
1
C301
Update JCRIO pin definition on DVT
10P_0402_50V8J
2@

Reserved for EHCI CRC errors

C C

CT2 CT4
0.1U_0402_10V7K 0.1U_0402_10V7K
TPM9655@ TPM9655@
CT5
0.1U_0402_10V7K

TPM1.2 on board 0.1U_0402_10V7K

TPM9655@

0.1U_0402_10V7K
+3VS

+VSB_TPM RT12 2 1 0_0603_5% +3VS

TPM9655@

1
1 2 TPM_XTALI 2 2 2 RT13 2 RT10 2 1 0_0603_5% +3VALW
CT1 22P_0402_50V8J 0_0603_5% TPM9635@
TPM9635@ CT2 CT4 CT5 TPM9655@ CT8
TPM9635@ TPM9635@ TPM9635@ TPM9635@

2
1

1 1 1 +VDD_TPM 1 0.1U_0402_10V7K CT8

2

@ RT1 0.1U_0402_10V7K
YT1 10M_0402_5% TPM9655@
32.768KHZ_12.5P_1TJF125DP1A000D +VSB_TPM
TPM9635@ 0.1U_0402_10V7K
1

UT1
24
19
10

5
1 2 TPM_XTALO
CT6 22P_0402_50V8J

VSB
VDD
VDD
VDD
B TPM9635@ LPC_AD0 26 B
<22,33,34> LPC_AD0 LAD0
LPC_AD1 23
<22,33,34> LPC_AD1 LAD1
LPC_AD2 20
<22,33,34> LPC_AD2 LAD2
LPC_AD3 17 6 TPM_GPIO PAD @ T62
<22,33,34> LPC_AD3 LAD3 GPIO
LPC_FRAME# 22 2 TPM_GPIO2 PAD @ T63
<22,33,34> LPC_FRAME# LFRAME# GPIO2
<11,22,29,30> APU_PCIE_RST# PLT_RST# 16 Base I/O Address
LPC_PD# 28 LRESET#
LPCPD#
0 = 02Eh
SERIRQ 27 1 =* 04Eh +3VS
<22,33> SERIRQ SERIRQ
21
<22> CLK_PCI_TPM_FCH LCLK TPM9635@

1
TPM9635@ 1 2 1 2
TPM9635@ SLB 9635 TT 1.2 0_0402_5%
+VSB_TPM 10P_0402_50V8J CT7 RT4 10_0402_5% 15 8 RT5 1 2 TPM9635@
RT11 1 2 0_0402_5% CLKRUN# TEST1 9 RT3
TPM9635@ TESTB1/BADD 4.7K_0402_5%
1

2
PP
RT7 3
NC

2
@ 4.7K_0402_5% TPM_XTALO 14 12 TPM9655@
XTALO NC 1 0_0402_5% RT6
2

+3VS TPM_XTALI 13 NC RT14 1 2 APU_PCIE_RST#

XTALI/32K IN 4.7K_0402_5%
@
1

GND
GND
GND
GND

1
1

RT8
RT2 TPM9635@ RT8 TPM9655@
TPM9635@ 0_0402_5% 0_0402_5% SLB 9635 TT 1.2_TSSOP28
25
18
11
4

4.7K_0402_5% TPM9635@
2
2

A A
LPC_PD#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 32 of 47
5 4 3 2 1
 5 4 3 2 1

+3VL +3VL

0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3

1 1 1 1 1 1 0.1U_0402_10V7K
CB1 CB2 CB5 CB7 1 2
0.1U_0402_10V7K
For EMI CB4 CB6
2 2 2 2 2 2

111
125
0.1U_0402_10V7K 1000P_0402_50V7K

22
33
96

67
9
CLK_PCI_EC UB1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
1
RB3
10_0402_5%
@ GATEA20 1 21 WL_BT_LED#
D <24> GATEA20 GATEA20/GPIO00 GPIO0F WL_BT_LED# <35> D
KB_RST# 2 23 EC_BEEP# BATT_TEMPA 1 2
<24> KB_RST# EC_BEEP# <31>
2

SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 CB9 100P_0402_50V8J

1 <22,32> SERIRQ SERIRQ GPIO12
CB11 LPC_FRAME# 4 27
<22,32,34> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J LPC_AD3 5 ACIN_D 1 2
<22,32,34> LPC_AD3 LPC_AD3
@ LPC_AD2 7 PWM Output CB10 100P_0402_50V8J
2 <22,32,34> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMPA
<22,32,34> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA <37>
LPC_AD0 10 LPC & MISC 64
<22,32,34> LPC_AD0 LPC_AD0 GPIO39 65 ADP_I
ADP_I/GPIO3A ADP_I <37,38>
CLK_PCI_EC 12 AD Input 66
<22,26> CLK_PCI_EC CLK_PCI_EC GPIO3B
LPC_RST# 13 75
<22,34> LPC_RST# PCIRST#/GPIO05 GPIO42
EC_RST# 37 76 EC_ENBKL
+3VL EC_RST# IMON/GPIO43 EC_ENBKL <19>
RB2 EC_SCI# 20
<24> EC_SCI# EC_SCII#/GPIO0E
47K_0402_5% WLAN_PWR# 38
<29> WLAN_PWR# GPIO1D
1 2 EC_RST# 68
DAC_BRIG/GPIO3C 70 EN_DFAN1
Add WLAN_PWR# on DVT EN_DFAN1/GPIO3D EN_DFAN1 <5>
1 2 DA Output 71
CB12 0.1U_0402_10V7K KSI0 55 IREF/GPIO3E 72
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F +3VL
KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <31>
KSI4 59 84 USB_EN# LID_SW# 1 2
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# <27,28>
KSI5 60 85 RB35 47K_0402_5%
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <35>
KSO0 39 88 TP_DATA +5VS
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <35>
KSO1 40
KSO2 41 KSO1/GPIO21 TP_CLK 1 2
KSO3 42 KSO2/GPIO22 97 VGATE RB8 @ 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <43>
KSO4 43 98 WOL_EN#
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN# <30>
KSO5 44 99 TP_DATA 1 2
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH VCIN0_PH connect to RB9 @ 4.7K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <37>
C KSO7/GPIO27 SPI Device Interface power portion (9012 only)
C
KSO8 47
KSO9 48 KSO8/GPIO28 119 SYSON 1 2
KSI[0..7] KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 RB10 4.7K_0402_5%
<34> KSI[0..7] KSO10/GPIO2A SPIDO/GPIO5C
KSO11 50 SPI Flash ROM 126
KSO[0..15] KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128
<34> KSO[0..15] KSO12/GPIO2C SPICS#/GPIO5A
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73
81 KSO15/GPIO2F ENBKL/GPIO40 74
RP7 82 KSO16/GPIO48 PECI_KB930/GPIO41 89
1 8 EC_SMB_CK1 KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_FULL_LED#
+3VL BATT_CHG_LED#/GPIO52 BATT_FULL_LED# <35>
2 7 EC_SMB_DA1 91 WLAN_RST#
CAPS_LED#/GPIO53 WLAN_RST# <29>
+3VS 3 6 EC_SMB_CK2 EC_SMB_CK1 77 GPIO 92 1 2
<37,38> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_SUSP_LED# <35>
4 5 EC_SMB_DA2 EC_SMB_DA1 78 93 BATT_CHG_LOW_LED# RB14 0_0402_5%
<37,38> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# <35>
EC_SMB_CK2 79 SM Bus 95 SYSON
<7,18> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <36,40>
2.2K_0804_8P4R_5% EC_SMB_DA2 80 121 VR_ON
<7,18> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <43>
127
PM_SLP_S4#/GPIO59
VCOUT0_PH_L 1 @ 2
VS_ON <39>
SLP_S3# 6 100 EC_RSMRST# RB34 0_0402_5%
<24> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <24>
SLP_S5# 14 101 EC_LID_OUT# VCOUT0_PH connect to power portion (9012 only)
<24> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <24>
EC_SMI# 15 102 PROCHOT_IN
<24> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 PROCHOT_IN <37>
16 103 H_PROCHOT_EC
17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0_PH_L
USB_CHG_EN# 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF#
<28> USB_CHG_EN# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <19>
BT_ON 19 GPIO 106 PBTN_OUT# RB18
<29> BT_ON GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <24>
25 107 FCH_PWR_EN 330K_0402_5%
EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 FCH_PWR_EN <36,41>
FAN_SPEED1 28 108 2 1 +3VL
<5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
WL_OFF# 29
<29> WL_OFF# EC_PME#/GPIO15
E51_TXD 30
<29> E51_TXD EC_TX/GPIO16
E51_RXD 31 110 ACIN_D ACIN_D 2 1
<29> E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <38>
FCH_PWRGD 32 112 EC_ON_R RB751V40_SC76-2 DB1
B <24> FCH_PWRGD PCH_PWROK/GPIO18 EC_ON/GPXIOD02 B
PWR_SUSP_LED# 1 2 34 114 ON/OFFBTN#
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <27>
RB13 @ 0_0402_5% 36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <35>
1 2 116 SUSP#
SUSP#/GPXIOD05 SUSP# <36,40,41,42,45>
RB16 1K_0402_5% 117
GPXIOD06 118
PECI_KB9012/GPXIOD07
AGND/AGND

T14 122 SUSP# 1 2

1 @ 2 XCLKO 123 XCLKI/GPIO5D 124 +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

<22,26> RTC_CLK XCLKO/GPIO5E V18R

@ RB20 0_0402_5% 1
GND0

1 2 LPC_RST# VR_ON 1 2
CB13 1U_0402_6.3V6K CB15 RB23 10K_0402_5%
1

1 4.7U_0805_10V4Z
@ RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113

69

1 2 SUSP# 100K_0402_5% 20P_0402_50V8

CB14 180P_0402_50V8J
2
2

Close to EC
H_PROCHOT# <7,22>
Low Active (+1.5V)

1
RB27 RB36 D QB1
Voltage Comparator Pins FOR 9012 A3
100K_0402_5% EC_ON_R 1 2 H_PROCHOT_EC 2 2N7002_SOT23-3
EC_ON <39> <37> H_PROCHOT_EC
1 2 E51_TXD G
VCIN0 pin109 2.2K_0402_5% High Active
>1.2V <1.2V 1 S

3
VCIN1 pin102 1U_0402_6.3V6K
CB50
VCOUT0 pin104 2
HIGH LOW
A +3VS A
VCOUT1 pin103 LOW HIGH
H_PROCHOT_EC 1 @ 2
RB6 10K_0402_5%
For KB9012 EC_ON low pulse work around

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 33 of 47
5 4 3 2 1
 1 2 3 4 5 6 7 8

Place the PAD under DDR DIMM.

LPC Debug Port
@
E-T_3801K-F10N-01L

12
GND 11
GND 10
10 +3VS
9
9 8
A LPC_RST# <22,33> A
8 7 CLK_PCI_DDR
7 CLK_PCI_DDR <22,26>
6
6 LPC_FRAME# <22,32,33>
5
5 LPC_AD3 <22,32,33>
4
4 LPC_AD2 <22,32,33>
3
3 LPC_AD1 <22,32,33>
2
2 LPC_AD0 <22,32,33>
1
1
JDB
C457@ R393@
1 2 1 2 CLK_PCI_DDR

22P_0402_50V8J 22_0402_5%

For EMI

For EMI
Close to JKB

B B

KSO2 1 2
C404 100P_0402_50V8J
KSO1 1 2
C405 100P_0402_50V8J
KSO0 1 2
C406 100P_0402_50V8J
KSO4 1 2
KEYBOARD CONN. KSO3
C407
1
100P_0402_50V8J
2
C408 100P_0402_50V8J
KSO5 1 2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] <33>
KSO14 1 2
KSO[0..15] C410 100P_0402_50V8J
KSO[0..15] <33>
KSO6 1 2
C411 100P_0402_50V8J
KSO7 1 2
C412 100P_0402_50V8J
KSO13 1 2
JKB
C413 100P_0402_50V8J
1 KSO8 1 2
1 2 KSO15 C415 100P_0402_50V8J
2 3 KSO14 KSO9 1 2
3 4 KSO13 C416 100P_0402_50V8J
4 5 KSO12 KSO10 1 2
5 6 KSO11 C417 100P_0402_50V8J
6 7 KSO10 KSO11 1 2
C 7 8 KSO9 C418 100P_0402_50V8J C
8 9 KSO8 KSO12 1 2
9 10 KSO7 C419 100P_0402_50V8J
10 11 KSI7 KSO15 1 2
11 12 KSI6 C420 100P_0402_50V8J
12 13 KSO6 KSI7 1 2
13 14 KSI5 C421 100P_0402_50V8J
14 15 KSO5 KSI2 1 2
15 16 KSI4 C422 100P_0402_50V8J
16 17 KSI3 KSI3 1 2
17 18 KSI2 C423 100P_0402_50V8J
18 19 KSI1 KSI4 1 2
19 20 KSO4 C424 100P_0402_50V8J
20 21 KSI0 KSI0 1 2
21 22 KSO3 C425 100P_0402_50V8J
22 23 KSO2 KSI5 1 2
26 23 24 KSO1 C427 100P_0402_50V8J
27 GND 24 25 KSO0 KSI6 1 2
GND 25 C429 100P_0402_50V8J
ACES_50524-02501-001 KSI1 1 2
C431 100P_0402_50V8J
@

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 34 of 47
1 2 3 4 5 6 7 8
 5 4 3 2 1

Touchpad Connector
(Reserve 7 pins for LED & Win8 TP)

+3VL +5VS +5VALW

JTP
1
2 1
TP_CLK 3 2
D <33> TP_CLK 3 D
TP_DATA 4
<33> TP_DATA 4
5
LID_SW# 6 5
<33> LID_SW# 6
BATT_FULL_LED# 7
<33> BATT_FULL_LED# 7
BATT_CHG_LOW_LED# 8
<33> BATT_CHG_LOW_LED# 8
PWR_SUSP_LED# 9
<33> PWR_SUSP_LED# 9
HDD_LED# 10
WL_BT_LED# 11 10 13
<33> WL_BT_LED# 11 G1
12 14
12 G2
ACES_50504-0120N-001
@

CPU VGA PCH BATT

Screw Hole H1
H_4P2
H2
H_4P6
H3
H_4P2x4P6
H4
H_3P5
H5
H_3P0
H8
H_3P0
HDD LED @ @ @ @ @ @

1
C C
SATA_LED# <23>
2

R404
+3VS 2 1 6 1
10K_0402_5%
5

Q9A
2N7002KDWH_SOT363-6
HDD_LED# 3 4

Q9B
2N7002KDWH_SOT363-6
1 @ 2
R50 0_0402_5%

PTH
NPTH

H7 H10 H11 H12 H13 H14 H15 H17 H18 H9 H16 H20 H21
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0N H_3P0 H_3P0x4P0N H_3P0N H_3P0N H_3P0
@ @ @ @ @ @ @ @ @ @ @ @ @

1
B B

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4

@ @ @ @

1
ISPD
U2
ZZZ PJP1
PCB FCH
DC-IN
AMD A13 HUDSON-M3L R3
PCB LA-8868P REV1 PJP1 45@ M3LR3@

UV1
U1 U1 U1

A
CPU GPU A

2160809024A11SEYMOU_FCBGA631
AMD E2-1800 R1_UNBW AMD E2-1800 R3 AMD E1-1200 R3 SEYMOURR3@
E2R1@ E2R3@ E1R3@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 35 of 47
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

Vgs=10V,Id=9A,Rds=18.5mohm
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +1.5V +1.5VS

4.7U_0805_10V4Z 4.7U_0805_10V4Z +5VS Vgs=10V,Id=9A,Rds=18.5mohm 4.7U_0805_10V4Z

1 1 1 1 1 1
Q29 C459 C460 Q30 C461 C462 Q31 C463 C465

470_0805_5%

470_0805_5%

470_0805_5%
8 1 8 1 For EMI 8 1
D S D S D S

2
7 2 7 2 1U_0402_6.3V6K 7 2
D S 2 2 D S 2 2 D S 2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 3 R406 6 3 R411 6 3 R412
5 D S 4 5 D S 4 5 D S 4
D G D G 2 2 D G
1U_0402_6.3V6K C822 C821 1U_0402_6.3V6K
1 SI4800BDY_SO8 1 R410 2 SI4800BDY_SO8 1 R416 2 SI4800BDY_SO8 1 R417 2 1
+VSB +VSB +VSB

3 1

3 1

3 1
0.022U_0402_25V7K

0.01U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 47K_0402_5% 1 1 47K_0402_5% @ @ 1 1 220K_0402_5%
1

6
1 1

0.1U_0402_25V6
C472
C466 R415 Q10A Q10B C467 C468 R413 Q11A Q11B C469 C470 R414 Q12A Q12B
330K_0402_5% 200K_0402_5% 820K_0402_5%
2 2 2 SUSP 5 2 2 @ 2 SUSP 5 2 2 2 SUSP 5
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
2

2
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

4
+5VALW +1.5V
+5VALW
2

2
+1.8VS +0.75VS
R56 R478 +5VALW

2
100K_0402_5% 470_0805_5%

2
R422

2
R254 R477 100K_0402_5%
1

3 1
FCH_PWR_EN# R432 470_0805_5% 470_0805_5%
100K_0402_5%

1
Q218B SUSP

1
3

6
Q25B 2N7002KDWH_SOT363-6 5 SYSON#

6
Q25A

6
<33,41> FCH_PWR_EN 1 @ 2 5 2N7002KDWH_SOT363-6 Q21B Q21A

4
R62 0_0402_5% Q218A SUSP# 2 2N7002KDWH_SOT363-6
<33,40,41,42,45> SUSP#
1

SUSP 5 2 SUSP
4

2 2 2N7002KDWH_SOT363-6 2
Q25A in page22 <33,40> SYSON

1
R67 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

1
100K_0402_5%

1
2

+3VALW

2
C530 Vgs=-4.5V,Id=3A,Rds<97mohm
0.1U_0402_10V7K

2
1

3
S
R8 Q3 PJ2

2
G
FCH_PWR_EN# 1 2 2 JUMP_43X79
@
+3VALW_FCH

1
47K_0402_5% 2 AO3413_SOT23 D

1
C527
0.01U_0402_25V7K
1
2
1
C529
3 C526 3
1U_0402_6.3V6K
4.7U_0805_10V4Z 1
2

+5VS TO +5VS_ODD +1.1VALW to +1.1VS +1.1VS

2
R419
+5VS +1.1VALW +1.1VS 470_0805_5%

Vgs=10V,Id=14.5A,Rds=6mohm 4.7U_0805_10V4Z

3 1
+5VALW
1 1
Q44 C476 C475
2 8 1 Q23B
D S
2

C471 Vgs=-4.5V,Id=3A,Rds<97mohm +5VS_ODD 7 2

R458 0.1U_0402_16V7K 6 D S 3 2 2 SUSP 5 2N7002KDWH_SOT363-6
100K_0402_5% 5 D S 4
D G
2

1 1U_0402_6.3V6K

4
3

S
R456 Q45 PJ28 FDS6676AS_SO8 1 R418 2
2

+VSB
1

4.7U_0805_10V4Z
ODD_PWR# 1 2 2 JUMP_43X79 R457 1 1 220K_0402_5%

6
0.1U_0402_25V6
@ 470_0805_5%
+5VS_ODD
1

47K_0402_5% 2
D C474 C477 R420 Q23A
1

AO3413_SOT23 820K_0402_5%
1

3 1
6

C255 2 2 2 1 2 SUSP
Q53A 0.01U_0402_25V7K 2N7002KDWH_SOT363-6 R385 0_0402_5%

2
1 Q53B
1 2

1
2 2N7002KDWH_SOT363-6 1 C201
<23> ODD_PWR
C680 5 ODD_PWR# 0.1U_0402_16V4Z
C679 1U_0402_6.3V6K 2N7002KDWH_SOT363-6 @
1

4.7U_0805_10V4Z 2 1
4

@ 2
4
Need to delay after 4
+3VS ramp up

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 36 of 47
A B C D E
 A B C D

PL1
HCB2012KF-121T50_0805 PH1 under CPU botten side :
1 2
VIN CPU thermal protection at 93 +-3 degree C Please locate these parts
PL2
Near EC chip
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2
+3VL
PJP1 <33,38> ADP_I

1000P_0402_50V7K

1000P_0402_50V7K

12.1K_0402_1%
100P_0402_50V8J
1
+

1
1K_0402_1%
100P_0402_50V8J
1

PR4
2
1
+ <33> H_PROCHOT_EC 1

PC1

PC2

PC3

PC4

PR1
2
10K_0402_1%

PR2
3

2
-

2
4
-
SINGA_2DW-0005-B03

100K_0402_1%_TSM0B104F4251RZ
@
<33> PROCHOT_IN <33> VCIN0_PH

0.1U_0402_10V7K

0.1U_0402_10V7K
1

1
20K_0402_1%
PC11

PC12
PR3

PH1
2

2
1

2
PL3 @
HCB2012KF-121T50_0805 2012/07/11
1 2
GND connect to EC pin69 GND
VMB
PJP2 PL4
1 HCB2012KF-121T50_0805
1 2 1 2
2 3 BATT+
EC_SMCA
3 4 EC_SMDA
4

0.01U_0402_25V7K
5 TS_A
5

10U_0805_25V6K
6
6
@PJSOT24CW_SOT323-3

2
7 3 1
+VSBP
2

7 B+
1

1
PC6

PC7

0.22U_0603_25V7K

0.1U_0603_25V7K
CCM_C250137GR007M262ZR PC5

100K_0402_1%
PD1

1000P_0402_50V7K
2

PC9
1
PR6

PC8
2

2
VL

2
PQ1

2
PD2 PR7 TP0610K-T1-GE3_SOT23-3
@PJSOT24CW_SOT323-3 22K_0402_1%
2 1 2 VSB_N_001

1VSB_N_003
1
3 PR8
100K_0402_1%

1 2 PR9
EC_SMB_CK1 <33,38>

1
PR10 100_0402_1% 0_0402_5% D
1 2VSB_N_002 2 PQ2
<39,41> POK
1 2 G SSM3K7002FU_SC70-3
EC_SMB_DA1 <33,38>

.1U_0402_16V7K
PR11 100_0402_1% S

3
1

PC10
PJP3
1 2 2 1
PR12 24K_0402_1%
+3VL +VSBP +VSB

2
PAD-OPEN 2x2m
1 2
BATT_TEMPA <33>
PR13 1K_0402_1%

3 3

RTC Battery

- PBJ1 + PR14
560_0603_5%
PR15
560_0603_5%
2 1 +RTCBATT_001 1 2+RTCBATT_0021 2 +RTCBATT

@MAXEL_ML1220T10

SP093MX0000

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 37 of 47
A B C D
 A B C D

for reverse input protection

1
D
BQ24725_0012 PQ209
G SSM3K7002FU_SC70-3
S

3
1
PR225 PR226 1

1 2 1 2

1M_0402_5% 3M_0402_5%

VIN PQ203 P1 PQ205 P2 B+ PL201 CHG_B+ PQ207

TPCA8057-H_PPAK56-8-5 DMG4406LSS_SO8 PR211 DMG4406LSS_SO8
0.01_2512_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1 8 1 4 1 2 8 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2 2 7 7 2

0.1U_0402_25V6
5 3 3 6 2 3 6 3
2200P_0402_50V7K

0.1U_0402_25V6
5 VIN 5

PC216
1

1
@0_0402_5%

PC211

PC212

PC213

PC214

PC215

0.01U_0402_50V7K
PR231

@0_0402_5%
PC231

PR232
4

PC234
PD230

2
BAS40CW_SOT323-3 @ @
PC230

2
1

2
0.1U_0402_25V6

2
2

1BQ24725_VCC11
BQ24725_ACDRV_1

1
BQ24725_BATDRV 1 2BQ24725_BATDRV_1

PC235
0.047U_0402_25V7K PR233

2
1 2 4.12K_0603_1%
PC237

10_1206_1%
PC236 1 2BQ24725_BST1
0.1U_0402_25V6

PR228

5
0_0603_5%
PR229
PD231

0.1U_0603_25V7K
RB751V-40_SOD323-2
2
PQ201 2

2
1
PC238
AON7408L

BQ24725_BST 2

BQ24725_REGN2
4

BQ24725_VCC
4.12K_0603_1%

4.12K_0603_1%

PC239

BQ24725_LX
2
1

1 2 DH_CHG BATT+
PR234

PR235

DH_CHG
PL202
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR222

3
2
1
1 2 0.02_1206_1%

BQ24725_ACP

BQ24725_ACN
BQ24725_LX 1 2 CHG 1 4
2

1U_0603_25V6K

5
6
7
8
2 3

20

19

18

17

16
PU200

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
CSOP1
1

@4.7_1206_5%
PQ202

VCC

PHASE

HIDRV

BTST

REGN

@10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR206
21 AO4468L_SO8

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC224

PC225
PC221

PC222

PC223
1

1
1 15 DL_CHG 4
ACN LODRV

PC240

PC241
BQ24725_SNUB 2

2
2 14
ACP GND PR236

3
2
1

2
BQ24725ARGRR_VQFN20_3P5X3P5 10_0603_1%
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR237
6.8_0603_1%

@680P_0603_50V8J
BQ24725_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN

PC206
+3VALW 1 2 BQ24725_ACOK 5 11 BQ24725_BATDRV PC242
PR238 @10K_0402_1% ACOK ACDET BATDRV 0.1U_0603_16V7K

2
IOUT

SDA

ILIM
SCL
3 3

1 2 +3VALW
+3VL
6

10
PR239 10K_0402_1%
PR241
BQ24725_ILIM 1 2

0.01U_0402_25V7K
1 2
<33> ACIN

100K_0402_1%
PR240 10K_0402_1% 150K_0402_1%

1
BQ24725_IOUT

PC243
PR242

1
BQ24725_ACDET

VIN 1 2BQ24725_ACDET1

2
154K_0402_1%

PR243
2
1

270K_0402_1%
PR244
2

PC251
Vin Dectector 2 1
0.22U_0402_16V7K

66.5K_0402_1%

EC_SMB_CK1 <33,37>
1

100P_0402_50V8J
Min. Typ Max.
1

100_0402_5%
PR245
PC244

PR246

H-->L 17.23V
EC_SMB_DA1 <33,37>
2

L--> H 17.63V
2

PC245
2 1
ILIM and external DPM ADP_I <33,37>
100P_0402_50V8J
3.97A
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 38 of 47
A B C D
 A B C D E

2VREF_8205

1
PC333
1 1U_0603_16V6K 1

2
PR330 PR350
13.7K_0402_1% 30K_0402_1%
1 2 1 2

PR331 PR351
B+ 3/5V_B+
20K_0402_1% 20K_0402_1%
3/5V_B+
PL331 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR337 PR357
2200P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6

0.1U_0402_25V6
121K_0402_1% 105K_0402_1%
@680P_0603_50V7K

1 2 1 2
1

1
PC338

PC339

PC340

PC353

PC354

PC358
1
PC334

1
PU330
2

5
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
2

1
PC341
4 10U_0805_6.3V6M 25
PQ331 P PAD

2
AON7408L
7 24 4 PQ351
VO2 VO1 AON7408L

1
2
3
PC335 8 23 PR355 PC355
2 0.1U_0402_10V7K PR333 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K 2
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2

3
2
1
2.2_0402_5% BOOT2 BOOT1
PL332 UG_3V 10 21 UG_5V PL352
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE2 UGATE1 2.2UH_ETQP3W2R2WFN_8.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP 5
PHASE2 PHASE1

5
LG_3V 12 19 LG_5V
LGATE2 LGATE1

SKIPSEL
1

1
4.7_1206_5%

4.7_1206_5%
220U_6.3V_M

220U_6.3V_M
VREG5
PR336

PR356
1 1

GND

VIN

NC
EN
Ipeak=5A + +
PC331

PC351
4 4
POK <37,41>
Imax=3.5A PR334
1 SNUB_3V 2

13

14

15

16

17

18

SNUB_5V 2
499K_0402_1% RT8205LZQW(2)_WQFN24_4X4
F=305kHZ 2 PQ332 1 2 3/5V_B+_001 PQ352 2
5/17 emc

AON7406L 3/5V_B+ FDMC7692S_MLP8-5 6/18

Total capacitor
1
2
3

3
2
1

680P_0603_50V8J
footprint change footprint change

1
680P_0603_50V8J

330u
VL

1
ESR=15m ohm

PC356
PR338 PC342
PC336

100K_0402_1% 1U_0603_10V6K
2

2
1
PC359
Ipeak=10.5A
4.7U_0805_10V6K Imax=8.5A

2
F=245kHZ
3/5V_B+
Total capacitor

1
330u
ENTRIP1

ENTRIP2

2VREF_8205
3 PC360 ESR=15m ohm 3

2
0.1U_0603_25V7K
6

D D
PQ333A 2N_3_5V_001 5 PQ333B
SSM6N7002FU_US6 G G SSM6N7002FU_US6

S S
1

6/18 EOL

PR339 PJP333
100K_0402_5% PJP352 2 1
PR340 1 2 1 2 +3VLP +3VL
VL +5VALWP +5VALW (5A,200mils ,Via NO.= 10)
2.2K_0402_1% PAD-OPEN 2x2m
1

1 2
PAD-OPEN 4x4m
<33> EC_ON PR341
PQ334
DRC5115E0L_SOD323-3 PJP332
0_0402_5% 1 2 +3VALW (4A,120mils ,Via NO.= 8)
1 2EC_ON_001 2 +3VALWP
<33> VS_ON PAD-OPEN 4x4m
4.7U_0805_25V6-K
1

PC343

3
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date 2013/10/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 39 of 47
A B C D E
 5 4 3 2 1

0.75Volt +/- 5%
D TDC 0.7A D

Peak Current 1A
PL151
HCB1608KF-121T30_0603
B+ 1 2 1.5V_B+
PR155
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%
@680P_0603_50V7K

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

@4.7U_0805_25V6-K
DH_1.5V +0.75VSP
1

1
PC151

0.22U_0402_10V6K
PC153

PC154

PC157

PC158

PC155

@10U_0805_6.3V6K
10U_0805_6.3V6K

10U_0805_6.3V6K
SW_1.5V
2

1
PC260

PC261

PC262
1
5
DL_1.5V

16

17

18

19

20
PU150

2
PHASE

UGATE

BOOT

VTT
VLDOIN
21
PAD
4 15 1
LGATE VTTGND

PQ151 PR152 14 2
PL152 AON7408L 16.9K_0402_1% PGND VTTSNS

1
2
3
1UH_PCMB063T-1R0MS_12A_20% 1 2CS_1.5V
2 1 13 3
C +1.5VP PC159 CS RT8207MZQW_WQFN20_3X3 GND C

5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
VDDP VTTREF
220U_6.3V_M

PR157
1

5.1_0603_5%
Ipeak=14A 1
1 2 VDD_1.5V 11 5 +1.5VP
VDD VDDQ
Imax=9.8A +
PC152

PGOOD
PR156 4

1
TON
F=313kHZ 4.7_1206_5% +5VALW PC161

FB
S5

S3
SNUB_+1.5VP 2

1
2 0.033U_0402_16V7K
Total capacitor

2
1 PQ152 PC160
2
3

10

6
1110u FDMC7692S_MLP8-5 1U_0603_10V6K
+5VALW

2
footprint change 2012/7/12
ESR=5m ohm
PR154
10K_0402_1%
FB_1.5V 2 1 +1.5VP

TON_1.5V
1

PC156
680P_0603_50V8J
2

Mode Level +0.75VSP VTTREF_1.5V

2
PR158
S5 L off off

1
887K_0402_1% PR160 PC162
S3 L off on PR159 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
S0 H on on 0_0402_5%

2
1 2 EN_1.5V
<33,36> SYSON

1
B
Note: S3 - sleep ; S5 - power off B

EN_0.75VSP
1

PC163
@0.1U_0402_10V7K
2

PR162
0_0402_5%
PJP152 2 1
1 2 <33,36,41,42,45> SUSP#
PAD-OPEN 4x4m

1
PJP153
1 2 (12A,480mils ,Via NO.= 24) PC164
+1.5VP +1.5V @0.1U_0402_10V7K

2
PAD-OPEN 4x4m

PJP76
1 2
A +0.75VSP +0.75VS (1A,40mils ,Via NO.= 3) A

PAD-OPEN 3x3m

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/12/30 Deciphered Date 2013/10/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom SAMSUNG B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 40 of 47
5 4 3 2 1
 5 4 3 2 1

1.1valwp
Peak Current 4A

680P_0402_50V7K
current limited 6A

2
PC174

1 SNUB_+1.1VALWP
D D

4.7_1206_5%
2
PR161
PL154 PL153

1
4
HCB1608KF-121T30_0603 0.47UH_PCMB063T-R47MS_18A_20%
1 2 1.1V_B+ 10 2 +1.1VALWP_LX 1 2
+5VALW

PG
PVIN LX
+1.1VALWP
9 3
PVIN LX

22U_0805_6.3V6M

@220P_0402_25V8K
10K_0402_1%

@68P_0402_50V8J
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
8
SVIN

@220P_0402_25V8K

2200P_0402_50V7K
@68P_0402_50V8J

@100P_0402_50V8J

22U_0805_6.3V6M

22P_0402_50V8J
PR164

PC249

PC247
PR163

1
PC250

PC248

PC246
@0_0402_5% 6
FB
1

PC173

PC167

PC172

PC166

PC165

PC170
1 2 EN_1.1V 5
<37,39> POK EN

PC168

PC171
PU151

SS
TP

LX

2
PR166 SY8036LDBC_DFN10_3x3
2

1
0_0402_5% PC169 +1.1VALWP_FB

11

1
1 2 @0.1U_0402_10V7K
<33,36> FCH_PWR_EN

2
11.5K_0402_1%
2

PR165

1
C C

PJP112
1 2
+1.1VALWP +1.1VALW (4A,240mils ,Via NO.= 8)
PAD-OPEN 4x4m

PU180
PL181 SY8032ABC_SOT23-6 PL182
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
+5VALW 1 2 VIN_1.8VSP 4 3 LX_1.8VSP 1 2
IN LX +1.8VSP
1

68P_0402_50V8J
PC184 5 2
PG GND

1
22U_0805_6.3V6M

1
4.7_1206_5%

PC188
6 1
2

FB EN

PR186
PR181
20K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
SNUB_1.8VSP 2

1
B B

PC182

PC183
FB_1.8VSP
<33,36,40,42,45> SUSP# 1 2 EN_1.8VSP

2
1
680P_0402_50V7K
PR183
0.1U_0402_10V7K

47K_0402_1%
1

PR182
1

PC187

PC186
10K_0402_1%

1
PR184

2
@47K_0402_5%
2
2

PJP182
1 2 (3A,120mils ,Via NO.= 6)
+1.8VSP +1.8VS
A PAD-OPEN 4x4m A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 41 of 47
5 4 3 2 1
 5 4 3 2 1

D D

+1.1VALW +5VALW

1
PJ101

1
JUMP_43X79

2
2

1
PC93

1
PC124 1U_0603_6.3V6M

2
22U_0805_6.3V6M

2
PU100
6
PR98 +1.05VSP_VIN 5 VCNTL 3
VIN VOUT +1.05VSP
9 4
VIN VOUT

1
0_0402_5%

39P_0402_50V8J

22U_0805_6.3V6M
1

1
C 1 2 +1.05VSP_EN 8 PR100 C
<33,36,40,41,45> SUSP# EN
1 2+1.05VSP_POK 7 2

PC90

PC95
10K_0402_1%

GND
+3VS POK FB

2
PR97

2
1
@1K_0402_1% +1.05VSP_FB

1
PC94 APL5916KAI-TRL_SO8

1
@0.01U_0402_25V7K

2
PR99
31.6K_0402_1%

2
PJP102

+1.05VSP 1 2 +1.05VS
JUMP_43X118

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 42 of 47
5 4 3 2 1
 5 4 3 2 1

PR500
PC500 PC517 100_0402_5%
68P_0402_50V8J 470P_0402_50V8J 2 1 +APU_CORE
1 2 1 2

APU_VDD0_RUN_FB_H_001 2 1
PR518 PR519 PR517 APU_VDD0_RUN_FB_H <7>
D D
47K_0402_1% 10K_0402_1% PC518 0_0402_5%

2
1 2 1 2 @68P_0402_50V8J
+5VS COMP

2
PR520

1
PC519 PC520 0_0402_5%
@68P_0402_50V8J @68P_0402_50V8J 2 1

1
APU_VDD0_RUN_FB_L <7>

2
PR521
10K_0402_1% 2 1
FB PR522
100_0402_5%

1
RGND
CPU_B+
+5VS

@0.01U_0402_25V7K
2

2
PL501

PC521
2
PR523 PR524 HCB2012KF-121T50_0805
7.15K_0402_1% 10K_0402_1% 2 1 B+

1
ISP1_N1_ST

1
+3VS PR525 2012/7/12

2200P_0402_50V7K
ISP1_N1_ST 1_0402_5%

0.1U_0402_25V6

33U_D_25VM_R60M

33U_D_25VM_R60M
@4.7U_0805_25V6-K
+APU_CORE

33U_25V_M

100U_25V_M

33U_25V_M
10U_0805_25V6K
1 1 1 1 1

2
PR527 1

2
2

1
+ + + + +

PC523

PC524

PC525

PC527

PC528

PC531

PC550

PC551
PC522 110K_0402_1%

OCSET

AON7408L_DFN8-5
ISP0
TON

PC526
PR526 0.1U_0402_25V6 TON 1 2 TON_APU_1

PQ501
@10K_0402_1%

2
2 2 2 2 2 2

1
PC529
1

+5VS PR505 0.1U_0402_25V6

41

40

39

38

37

36

35

34

33

32

31
PU500 2.2_0603_5% 4

2
BOOT0 2 1BOOT0_1 2 1

FB

COMP
OCSET

ISP0

ISN0

ISP1
GND

TON

RGND

ISN1

BOOT1
<33> VR_ON

1
PC530 PC505
2

@0.01U_0402_25V7K PR529 0.22U_0603_10V7K

PR528 UGATE0 1 PR530 2 UGATE0_1
2_0603_5%

3
2
1
100K_0402_1% 0_0603_5% PL502
1

C 1 2 RBIAS 1 30 PHASE0 1 2 +APU_CORE C

2
RBIAS UGATE1

1
PR531 2 29 PR506 0.47UH_PCMB063T-R47MS_18A_20%
@51_0402_1% EN PHASE1 4.7_1206_5%

PVCC
PQ502

1SNUB_CPU
1 2 APU_SVC_001 3 28 PC532
SVC PGND1 1U_0603_10V6K AON7212L_DFN8-5
PR532 @51_0402_1%

680P_0603_50V7K
+1.5V 1 2 APU_SVD_001 4 27

2
SVD LGATE1 LGATE0 4
1

0.1U_0402_10V7K APU_CORE_PWORK 5 26 PR534

PC785 1
PR533
2 PWORK RT8870AZQW_WQFN40_5X5 PVCC 2.43K_0402_1%
+APU_CORE
0_0402_5% PR535 VGATE 6 25 LGATE0 1 2 Imax=7.7A
2

<7> APU_SVC PGOOD LGATE0

PC506
1 2 PR537

3
2
1

2
<7> APU_SVD
0_0402_5% VFIX/DRPSEL 7
VFIX/DRPSEL PGND0
24 2.43K_0402_1% Ipeak=11A
1 2 1 2
1 2 8 23 PHASE0 Iocp(minimum)=13.2A
<7,22> APU_PWRGD PR536 0_0402_5% OCSET_NB
OCSET_NB PHASE0 ISP0 PC533
VCC 9 22 UGATE0 0.1U_0402_25V6 DCR=4.2mohm
VCC UGATE0
<33> VGATE 10 21 BOOT0 +APU_CORE
Rdson = 7mohm
FB_NB BOOT0
UGATE_NB
PHASE_NB
LGATE_NB
2

+5VS
COMP_NB

RGND_NB

PGND_NB

BOOT_NB

2
TON_NB

PR540
ISN_NB
ISP_NB
FB_NB

10K_0402_1% PC534
0.1U_0402_25V6

1
+5VS
1

11

12

13

+APU_VDDNB 14

15

16

17

18

19

20
2

PR541 PR542 +3VS

UGATE_NB
PHASE_NB

6.49K_0402_1% 33K_0402_1% PR543

LGATE_NB
COMP_NB

RGND_NB

BOOT_NB

2_0603_5%
TON_NB

ISP_NB

CPU_B+
1

VFIX/DRPSEL
1

PC535
OCSET_NB 1U_0603_10V6K

2200P_0402_50V7K
10U_0805_25V6K
PR544

0.1U_0402_25V6
4.7U_0805_25V6-K
2

1_0402_5% 2012/07/11
@0.01U_0402_25V7K

@0.01U_0402_25V7K

1
10K_0402_1%
2

1
B B

PC538

PC539

PC540

PC541
PR547
22K_0402_1%

5
PC536

PC537

TON_NB 2 1 TON_NB1
PR545

PR546

1 2
130K_0402_1%

2
2
1

PC542
1

PR515 0.1U_0402_25V6

2
BOOT_NB 2 1 BOOT_NB1 2 1 4
2.2_0603_5% PQ503
PC515
0.22U_0603_10V7K AON7408L_DFN8-5
UGATE_NB 1 2UGATE_NB_1

3
2
1
PR548
0_0603_5% PL503
PR549 PC543 PC544 PHASE_NB 1 2 +APU_VDDNB

1
100_0402_5% 470P_0402_50V8J 68P_0402_50V8J

4.7_1206_5%
1UH_PCMB063T-1R0MS_12A_20%

FDMC7692S_DFN8-5

PR516
1 2 1 2 1 2 COMP_NB
+APU_VDDNB +APU_VDDNB
2

PQ504
PR550 PR551 PR552 PC545 1 Imax=7A
0_0402_5% 10K_0402_1% 47K_0402_1% @68P_0402_50V8J

1SNUB_NB
1

2
<7> APU_VDDNB_RUN_FB_H
1 2 APU_VDDNB_RUN_FB_H_001 1 2 1 2 + PC502
330U_D2_2V_Y
Ipeak=10A
LGATE_NB 4
Iocp(minimum)=12A
2

680P_0603_50V7K
FB_NB PR553
2

PC547 2K_0402_1% 2
DCR=10mohm

PC516
PC546 @68P_0402_50V8J 2 1
1

PR554 @68P_0402_50V8J PR555

Rdson = 7mohm
1

3
2
1
0_0402_5% 8.2K_0402_1% PC548

2
1 2 RGND_NB 1 2 1 2
<7> APU_VDDNB_RUN_FB_L
PR556 ISP_NB
1 2 0.1U_0402_25V6

100_0402_5%
+APU_VDDNB
2

PC549
0.1U_0402_25V6
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019K4 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

+APU_CORE +APU_CORE_NB
+APU_VDDNB
+APU_CORE
10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V7K
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1 1 1 1 1 1 1
1 1 1 1 1 1 1
D PC822 PC823 PC824 PC825 PC826 PC827 PC828 D
PC801 PC802 PC803 PC804 PC805 PC806 PC807 10U_0603_6.3V6M
10U_0603_6.3V6M 2 2 2 2 2 2 2
2 2 2 2 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V7K
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M

+APU_CORE +APU_VDDNB

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0402_16V7K

1 1 1 1 1 1 1 1 1 1 1
PC808 PC809 PC810 PC811 PC829 PC830 PC831 PC832 PC833 PC834 PC835
1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0402_16V7K

+APU_VDDNB +APU_VDDNB
+APU_CORE

0.1U_0402_16V7K 0.1U_0402_16V7K 1
1 1 1 1 1 1
1 + PC836
PC812 PC813 PC814 PC815 PC816 PC838
PC837
0.1U_0402_16V7K 180P_0402_50V8J 330U_SX_2VY~D
2 2 2 2 2 180P_0402_50V8J 2 2
2
0.1U_0402_16V7K 0.1U_0402_16V7K

C C
+APU_CORE

1 1
PC817 PC818
2
180P_0402_50V8J
2
180P_0402_50V8J +VGA_CORE
+VGA_CORE

+APU_CORE +VGA_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@330U_SX_2VY

1U_0402_6.3V6K
1

1
1 1 1

D@ PC901

D@ PC902

D@ PC903

D@ PC904

D@ PC905

D@ PC906

D@ PC907

D@ PC908
2012/07/11
PC819 + PC820 + PC821 +

330U_D2_2V_Y

D@ 330U_D2_2V_Y
1 1 1

330U_D2_2V_Y
2

2
+ + +

D@ PC940

PC941

PC942
330U_SX_2VY
2 2 2

2 2 2

D@
330U_SX_2VY

B B
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VGA_CORE
1

1
D@ PC909

D@ PC910

D@ PC911

D@ PC912

D@ PC913

D@ PC914

D@ PC915

D@ PC916
2

10U_0603_6.3V6M

4.7U_0603_6.3V6K
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 1

2
D@ PC930

D@ PC931

D@ PC932

PC935

PC936
D@ PC933

D@ PC934
1

1
1 2

D@

D@
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1
PC917

PC918

PC919

PC920

PC921

PC922

PC923

PC924
2 2 2 2 2 2 2 2
D@

D@

D@

D@

D@

D@

D@

D@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 LA-8712P B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, September 07, 2013 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

D@ PL701

1 +VGA_CORE
HCB2012KF-121T50_0805
1 2
D@ PL702
HCB2012KF-121T50_0805
VGA_CORE_B+ 1 2
B+

10_0402_5%
D@ PR707
2012/07/11

82K_0402_1%

1
D@ 4700P_0402_25V7K

@ 10K_0402_5%
D@ PR708

2200P_0402_50V7K
PR718

0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D@ PC704

2
10P_0402_25V8J

2
D D

1
PC721

D@ PC717

D@ PC718

D@ PC719

D@ PC720
10P_0402_25V8J
2 1 D@ PR723

2
0_0603_5% PQ701 D@

20 TPS51518_VSNS

TPS51518_SLEW 1

2
2
D@ PC701
1 2UG_VGA_CORE1 4 TPCA8065-H_PPAK56-8-5

TPS51518_TRIP1
D@ PR715
0_0402_5%

1
D@ PR701 1 2
0_0402_5%

3
2
1
1 2 TPS51518_GSNS D@ PL703
0.36UH_MMD-10CZ-R36M-M1_23A_20%

21

19

18

17

16

2
2 1 TPS51518_V3 PU700 1U_0603_10V6K 3 2
PC722 D@ +VGA_CORE
11.3K_0402_1%

SLEW
PAD

VSNS

TRIP

GND

MODE
2

D@ PR702 4 1

1
D@ PR703

100K_0402_1% PQ704
1 15 PQ702
GSNS V5IN +5VALW

1
TPCA8059-H_PPAK56-8-5

330U_D2_2V_Y
1 +VGA_CORE

D@ TPCA8059-H_PPAK56-8-5
1

D@ PC796
+
TPS51518_V2 2
V3 DRVL
14 LG_VGA_CORE D@ PR706 TDC 15.6A
5.62K_0402_1%

4.7_1206_5%
2

Peak Current 21.6A

2
2
D@ PR704

4 4
3 13 UG_VGA_CORE OCP current 26A

SNUB_VGA_CORE
V2 D@ TPS51518RUKR_QFN20_3X3 DRVH
FSW=350kHz
1

TPS51518_V1 4 12 SW_VGA_CORE
DCR 1.33mohm +/-5%

3
2
1

3
2
1
V1 SW
10.5K_0402_1%
2

@
D@ PR709

5 11 BST_VGA_CORE 2 1BST_VGA_CORE11 2
V0 BST
PGOOD

D@ PR705 D@ PC705
C C
VREF

2.2_0603_5% 0.1U_0603_25V7K
VID0

VID1
1

TPS51518_V0
EN

1
D@ PC716
1
93.1K_0402_1%

1TPS51518_VID0 8

1TPS51518_VID1 9

10

680P_0603_50V8J
D@ PR710

2
0_0402_5%

0_0402_5%

EN_VGA_CORE
2

TPS51518_VREF
D@ 0.1U_0402_10V7K
1
PC702

+3VS
D@ PR714
2

0_0402_5%
1
D@ 10K_0402_5%

1 2 SUSP# <33,36,40,41,42>
PR711

D@ PR712 2

D@ PR713 2

PC703
@ .1U_0402_16V7K
2

<22> VGA_PWRGD
1K_0402_5%
2

2
1K_0402_5%
PR716

PR717

B +1.5V +5VALW B
1

1U_0603_6.3V6M
@

1
<12>

<12>
VGA_PWRSEL0

VGA_PWRSEL1

D@ PC780
D@ PJP780

1
JUMP_43X79

2
2
4.7U_0805_6.3V6K

2
PU780 D@ APL5930KAI-TRG_SO8
PD781
6
VCNTL

1
D@ PC781
Seymour XTX 1 2 +1.0VSP_VIN 5 3 +1.0VSP
9 VIN VOUT 4
VIN VOUT

1
@ RB751V-40_SOD323-2

22U_0805_6.3V6M
0.01U_0402_25V7K
VGA_PWRSEL1 VGA_PWRSEL0 Core Voltage Level 8 D@ PR781
EN

D@ PC783

D@ PC782
D@ PR780 7 2 1.82K_0402_1%

GND
2K_0402_1% POK FB

2
1 1 0.90V 1 2 +1.0VSP_EN
<33,36,40,41,42> SUSP#

2
+1.0VSP_FB

1
1

1
1 0 1.00V D@ PC784
0.1U_0402_10V7K D@ PR782

2
7.32K_0402_1%
0 1 1.05V

2
0 0 1.15V
PJP782
1 2
A
+1.0VSP +1.0VS A
D@
PAD-OPEN 3x3m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/30 Deciphered Date 2013/10/05 Title

SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019K4
Date: Saturday, September 07, 2013 Sheet 45 of 47
5 4 3 2 1
 NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1. 2012/04/24 P37-PWR-DCIN/BATT CONN/OTP Change PR12 from 6.49k to 24k Change source
2. 2012/04/24 P37-PWR-DCIN/BATT CONN/OTP Add PR13 1k Change source

3. 2012/04/24 P38-PWR_PWR-CHARGER Change PQ209 from SI1304BDL-T1-GE3_SC70-3 to SSM3K7002FU_SC70-3 Change source

4. 2012/04/24 P38-PWR_PWR-CHARGER Change PC244 from 0.1u to 0.22u Change source
5. 2012/04/24 P38-PWR_PWR-CHARGER Change PR241 from 100k to 150k Adjust current limit point

6. 2012/04/24 P41-PWR-3.3VALWP/5VALWP Change PR330 from 13k to 13.7k Adjust 3v voltage for HW request
7. 2012/04/24 P41-PWR-3.3VALWP/5VALWP Change PR351 from 19.1K to 20k Adjust 5v voltage for HW request
8. 2012/04/24 P41-PWR+1.1VALWP/+1.8VSP Change PU180 from SY8032ABC_SOT23-6 to SY8033BDBC_DFN10_3X3 Change IC solution for cost down

9. 2012/04/24 P43-PWR-CPU_CORE Add PC531 33u For acoustic noise

10. 2012/04/24 P43-PWR-CPU_CORE Add PC550 33u For acoustic noise
11. 2012/04/24 P43-PWR-CPU_CORE Add PC551 33u For acoustic noise

12. 2012/05/17 P38-PWR_PWR-CHARGER Un-mount PC123 10U and PC124 10U For acoustic noise

13. 2012/05/17 P39-PWR-3.3VALWP/5VALWP Add PR336 4.7 and PC336 680P EMI demand
14. 2012/05/17 P39-PWR-3.3VALWP/5VALWP Add PR356 4.7 and PC356 680P EMI demand

15. 2012/05/17 P40-PWR_1.5VP/0.75VSP Add PR156 4.7 and PC156 680P EMI demand
16. 2012/05/17 P40-PWR_1.5VP/0.75VSP PL152 Change partnumber SH00000PJ00 to SH00000QD00 lake of material

17. 2012/05/17 P43-PWR-CPU_CORE Change PC538 from 10U to 4.7U For acoustic noise
18. 2012/05/17 P43-PWR-CPU_CORE Add PC539 4.7U For acoustic noise
19. 2012/05/17 P43-PWR-CPU_CORE Add PC785 0.1U For acoustic noise

20. 2012/05/18 P44-PWR-PROCESSOR-DECOUPLING Un-mount 1U:PC901,PC902,PC903,PC904,PC905,PC906,PC907,PC908,PC909, EVT:uma load bom時把vga_core mlcc多Load的部分

PC910,PC911, PC912,PC913,PC914,PC915,PC916,PC933,PC934 DVT:設變數把多餘mlcc拿掉
21. 2012/05/18 P44-PWR-PROCESSOR-DECOUPLING Un-mount 10U:PC921,PC922,PC923,PC924,PC935
22. 2012/05/18 P44-PWR-PROCESSOR-DECOUPLING Un-mount 0.1U:PC930,PC931,PC932
23. 2012/05/18 P44-PWR-PROCESSOR-DECOUPLING Un-mount 330U:PC940,PC941
24. 2012/05/18 P44-PWR-PROCESSOR-DECOUPLING Un-mount 4.7U:PC917,PC918,PC919,PC920,PC936

25. 2012/06/18 P41-PWR-3.3VALWP/5VALWP Change part number PC331 and PC351 from MATSUKI to S.Elcon forbid:MATSUKI
26. 2012/06/18 P41-PWR-3.3VALWP/5VALWP Change part number PQ333 from TOSHIBA to TOSHIBA EOL

27. 2012/06/18 P43-PWR-CPU_CORE Change part number PC531 and PC550 from Panasonic to KEMET shortage

28. 2012/07/16 P37-PWR-DCIN/BATT CONN/OTP Add PR2 1OK and PC11 Change to unmount For support 60w adapter
29. 2012/07/16 P38-PWR_PWR-CHARGER Change vendor PQ205 and PQ207 from DII to NIKO-SEM Custmoer forbid DII
30. 2012/07/16 P40-P40-PWR_1.5VP / 0.75VSP Change PR154 from 10.2k to 10k For HW request
31. 2012/07/16 P43-PWR-CPU_CORE Change vendor PC531 and PC550 from Kemet to Sayno For acoustic noise
32. 2012/07/16 P43-PWR-CPU_CORE Change PC538 and Pc539 from 4.7u to 10u For acoustic noise
33. 2012/07/16 P45-PWR-VGA_CORE/1.0VSP Change PR708 from 130K to 82k Adjust over current protection point
34. 2012/07/16 P45-PWR-VGA_CORE/1.0VSP Add PR718 and PR715 For vga transient test

35. 2012/07/16 P37-PWR-DCIN/BATT CONN/OTP Change PC6,PC157,PC211,PC212,PC222,PC223,PC358,

P38-PWR_CHARGER PC524,PC539,PC538 from TAIYO(10U_25V_0805_H1.25) to Murata For acoustic noise
P39-PWR-3.3VALWP/5VALWP
P40-PWR_1.5VP / 0.75VSP
P43-PWR-APU_CORE

36. 2012/08/07 P41-PWR-3.3VALWP/5VALWP Change PR351 from 20k to 19.1k Adjust 5v voltage for HW request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A8868
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 46 of 47
 5 4 3 2 1

HW PIR (Product Improve Record)

VBLE4/5 LA-8866P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2012/02/14
Item Date Page Solution Request
--------------------------------------------------------------------------------------------------------------------------
1. 2/1 P28 Change JUSBB.1 from +USB_VCCB to +USB_VCCC For USB power
2. 2/1 P18 Change RV141,RV138,RV138,RV137 to DIS@ For VGA int. sensor
3. 2/1 P12 Remove RV29, change RV28 to 0 ohm For VGA 27MHz
4. 2/1 P22 Change R339 to UMA@ , Change R340 to DIS@ For board ID
D 5. 2/1 P29 Change +1.8VGS to +1.8VS For Green CLK D
6. 2/2 P30 Change CL36 from SE120102K80 to SE120102K90 For shortage
7. 2/6 P32 Update JCRIO pin definition Change int. MIC to MB
8. 2/6 P31 Add RA36,RA37 and delete CA64 Move sense resistors to MB
9. 2/6 P35 Change JTP from SP010015H00 to SP01001BF10 For ME request
10. 2/6 P31 Add JMIC connector SP02000RO00 For customer request
11. 2/6 P29 Change JWLAN from SP07000JP00 to SP07000TB00 For ME request
12. 2/8 P30 Add PJ31 For saving power consumption
13. 2/8 P29 Add PJ33, WLAN power circuit and reset pin For customer request
14. 2/8 P29 Change CM7,CM8,CM9 to @ For cost down
15. 2/8 P29 Add WLAN_PWR# and WLAN_RST# For customer request
16. 2/8 P30 Add test point TL1 for pin37 For vendor request
17. 2/8 P27 Delete SW4 For layout request
18. 2/8 P11 Change UV1 from SA000047G70 to SA000047G60 For PJE request
19. 2/8 P18 Change RV118, RV119 to DIS@ For HDMI issue
20. 2/8 P35 Add screw H17, H20 and H21 For ME request
21. 2/9 P21 Reserve ESD D94~D96 for HDMI For ESD request
22. 2/9 P9 Change C218 from 390U to 330U (SF000002080) For cost down
23. 2/9 P20 Remove D3~D5 and add D97 and D98 For ESD request
24. 2/9 P30 Reserve ESD D99 and D100 for LAN For ESD request
25. 2/9 P27 Add resistors R87,R89,R164,R158 Improve SATA signal quality
26. 2/10 P27 Add JODDC For HW experiment on DVT
27. 2/10 P8 Add C95,C102,C105 For EMI request
28. 2/10 P34 Change C457,R393 to mount For EMI request
29. 2/10 P29 Change CCL10 to mount For EMI request
30. 2/10 P24 Change ODD_DA#_FCH connect to U2.P6 For Module Design
31. 2/10 P24 Change ODD_PLUGIN# connect to P2.W7 For Module Design
C 32. 2/10 P21 Change Q6 from SB00000M700 to SB570020020 For BOM reduce C
--------------------------------------------------------------------------------------------------------------------------
33. 4/23 P19 Change R117 +3VS to +3VALW For LVDS power down sequence
34. 4/23 P19 Change R110,R133,C265,C261 For LVDS power down sequence
35. 4/23 P19 Change R388 +3VS to +5VS,R388 +3VS_LVDS_CAM to +5VS_LVDS_CAM
36. 4/23 P21 Add C202 and C216 For EMI request
37. 4/23 P22 Change R241 from GCLK@ to @ For USB30 wake issue
38. 4/23 P22 Change C294,C293,Y1,R242 to mount For USB30 wake issue
39. 4/23 P22 Change R271 and add R277,R268,C305,+RTCBATT_D
40. 4/23 P29 Change R156,R155,C907,C908,Q210 to @
41. 4/23 P29 Add RM20 and change UM5,RM21 to @
42. 4/23 P29 Change UCL1.2 to +3VALW, UCL1.14 to +RTCVCC_D and add RCL10 For USB30 wake issue
,RCL11
43. 4/23 P30 Mount QL53 and RL24 and change RL28,RL26 to @ For LAN disable
44. 4/23 P31 Add CA6,CA7 For EMI request
45. 4/23 P31 Add CA64,CA67,CA68,CA77 For EMI request
--------------------------------------------------------------------------------------------------------------------------
46. 5/16 P27 Delete R90~R93,R166,R168~R170,C379~C382,R87,R89,R96,R97,R158 For ODD 14" and 15" common PCBA issue
R164,R171,R172
47. 5/16 P27 Add U4 For ODD 14" and 15" common PCBA issue
48. 5/16 P23 Reserve R174 For ODD 14" and 15" common PCBA issue
49. 5/16 P27 Change C364 to 220p For ESD request

REVISION CHANGE: 0.2 TO 0.3

GERBER-OUT DATE: 2012/06/18
Item Date Page Solution Request
B
-------------------------------------------------------------------------------------------------------------------------- B
1. 6/11 P27 Add JODDC circuit and remove U4 circuit SATA ODD
2. 6/11 P33 Reserve RB8,RB9 Due to TP module for win8 feature
3. 6/15 P7 Change R846,R847,R848,R849,R851,R852 to Reserve For Debug only

REVISION CHANGE: 0.3 TO 1.0

GERBER-OUT DATE: 2012/07/18
Item Date Page Solution Request
--------------------------------------------------------------------------------------------------------------------------
1. 7/12 P19 Add D85 For avoid LVDS_CLK damage issue
2. 7/17 P6 Add C78 For EMI request
3. 7/18 P27 Un-stuff SW5 For debug only
4. 7/25 P30 Stuff D92 For ESD request
5. 8/27 P32 Stuff CT7 and RT4 on TPM SKU For EMI request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/05/18 Deciphered Date 2013/10/05 Title
SCHEMATIC, MB A8868

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K4
Date: Saturday, September 07, 2013 Sheet 47 of 47
5 4 3 2 1