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RFP70N06 Datasheet PDF
RFP70N06 Datasheet PDF
S E M I C O N D U C T O R RF1S70N06, RF1S70N06SM
70A, 60V, Avalanche Rated, N-Channel
December 1995 Enhancement-Mode Power MOSFETs
Features Packages
JEDEC STYLE TO-247
• 70A, 60V SOURCE
• rDS(on) = 0.014Ω DRAIN
GATE
• Temperature Compensated PSPICE Model DRAIN
(BOTTOM
• Peak Current vs Pulse Width Curve SIDE METAL)
• UIS Rating Curve (Single Pulse)
• +175oC Operating Temperature
Description
The RFG70N06, RFP70N06, RF1S70N06 and RF1S70N06SM
are N-channel power MOSFETs manufactured using the MegaFET JEDEC TO-220AB
process. This process, which uses feature sizes approaching SOURCE
DRAIN
those of LSI circuits, gives optimum utilization of silicon, resulting GATE
DRAIN
in outstanding performance. They were designed for use in appli- (FLANGE)
cations such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
PACKAGE AVAILABILITY
PART NUMBER PACKAGE BRAND
RFG70N06 TO-247 RFG70N06
JEDEC TO-262AA
RFP70N06 TO-220AB RFP70N06 SOURCE
DRAIN
RF1S70N06 TO-262AA F1S70N06 DRAIN GATE
(FLANGE)
RF1S70N06SM TO-263AB F1S70N06 A
NOTE: When ordering use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.
M A
A
DRAIN
G (FLANGE)
GATE
SOURCE
S
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD handling procedures. File Number 3206.3
Copyright © Harris Corporation 1995
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Specifications RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Rise Time tR - 50 - ns
Fall Time tF - 15 - ns
Total Gate Charge QG(TOT) VGS = 0V to 20V VDD = 48V, - 185 215 nC
ID = 70A,
Gate Charge at 10V QG(10) VGS = 0V to 10V RL = 0.68Ω - 100 115 nC
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RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
TC = +25oC 2
500
1
ID, DRAIN CURRENT (A)
THERMAL RESPONSE
0.5
ZθJC, NORMALIZED
100
100µs
0.2
1ms 0.1 PDM
0.1
10 0.05
10ms
0.02 t1
OPERATION IN THIS 100ms 0.01 t2
AREA MAY BE VDSS DC NOTES:
LIMITED BY rDS(ON) SINGLE PULSE DUTY FACTOR: D = t1/t2
MAX = 60V
PEAK TJ = PDM x ZθJC + TC
1 0.01
1 10 100 10-5 10-4 10-3 10-2 10-1 100 101
VDS, DRAIN-TO-SOURCE VOLTAGE (V) t, RECTANGULAR PULSE DURATION (s)
FIGURE 1. SAFE OPERATING AREA CURVE FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL
IMPEDANCE
80 TC = +25oC
1000
FOR TEMPERATURES
70 IDM, PEAK CURRENT CAPABILITY (A) ABOVE +25oC DERATE PEAK
CURRENT AS FOLLOWS:
ID, DRAIN CURRENT (A)
60
175 – T
I = I C
50 25 ----------------------
150
-
40
30 VGS = 10V
20
100 TRANSCONDUCTANCE
10 MAY LIMIT CURRENT
IN THIS REGION
0 50
25 50 75 100125 150 175 10-5 10-4 10-3 10-2 10-1 100 101
TC, CASE TEMPERATURE (oC) t, PULSE WIDTH (s)
160 160
+175oC
120 120
VGS = 6V
80 80
40 VGS = 5V 40
VGS = 4.5V
0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10.0
VDS, DRAIN-TO-SOURCE VOLTAGE (V) VGS, GATE-TO-SOURCE VOLTAGE (V)
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RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
THRESHOLD VOLTAGE
1.5
1.5
1.0
1.0
0.5 0.5
0.0 0.0
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)
ID = 250µA 1.2
BVDSS, NORMALIZED DRAIN-TO-SOURCE
1.0
BREAKDOWN VOLTAGE
1.5
0.8
0.6
1.0
0.4
0.5
0.2
0.0 0.0
-80 -40 0 40 80 120 160 200 0 25 50 75 100 125 150 175
TJ , JUNCTION TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN-SOURCE BREAKDOWN FIGURE 10. NORMALIZED POWER DISSIPATION vs TEMPERA-
VOLTAGE vs JUNCTION TEMPERATURE TURE DERATING CURVE
CISS
3000
30 5.0
0.75 BVDSS
2000 0.50 BVDSS
0.25 BVDSS
15 2.5
COSS RL = 0.86Ω
1000 IG(REF) = 2.2mA
CRSS VGS = 10V
0 0
I I
0 G ( REF ) G ( REF )
0 5 10 15 20 25 20 --------------------- t, TIME (µs) 80 ---------------------
I I
VDS, DRAIN-TO-SOURCE VOLTAGE (V) G ( ACT ) G ( ACT )
FIGURE 11. TYPICAL CAPACITANCE vs VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT. REFER TO HARRIS
APPLICATION NOTES AN7254 AND AN7260
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RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
300
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
100
STARTING TJ = +25oC
STARTING TJ = +150oC
10
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
tP
L VDS
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IL
0.01Ω tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tD(ON) tD(OFF)
RL
tR tF
VDS
90% 90%
VDS
VGS
10% 10%
0V
90%
DUT
RGS
VGS 50% 50%
PULSE WIDTH
10%
FIGURE 16. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
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RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.605
.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)
.MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6)
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
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