Problem 01: EEE 1: Essentials of Electrical & Electronics Engineering

EEE 1 Problem 01
Essentials of Electrical and

Electronics Engineering •  A load requires about 6V to operate but a
9-V battery is all that is available.
Problem Set 03
+ +
Variable
9V 6V
Load
- -
EEE 1: Essentials of Electrical & Electronics Engineering
Problem 01 Problem 01
•  To satisfy the load s requirements, you •  By voltage division:
constructed a voltage divider shown
below. Suppose the internal resistance of & 1000 #
6 = 9$ !, R = 500Ω
the load is equal to 1000Ω, what is R? % 1000 + R "
+ R +
9V 6V 1000Ω
- -
EEE 1: Essentials of Electrical & Electronics Engineering EEE 1: Essentials of Electrical & Electronics Engineering
1
•  Say the internal resistance of the load •  With the load s resistance at 600Ω, the
changed to 600Ω. Using your divider, load voltage will no longer be at 6V:
what is the voltage across the load? Is it
still 6V? ' 600 $
VL = 9% "
& 600 + R #
R
+ + ' 600 $
600Ω
VL = 9% "
9V VL? & 600 + 500 #
- - VL ≈ 4.9091V
•  Let us eliminate the sensitivity of the •  To do that, design a network (connecting
voltage source to changes in the load s the 9-V battery and the load) consisting
resistance. only of Si diodes (VT = 0.7V) such that the
voltage across the load will be around 6V.
+ + + +
Variable Variable
9V 6V 9V 6V
Load Load
- - - -
2
•  If we put four diodes in series (as shown •  Shown in the
below), we will have a voltage across the diagram on the left
variable load that s close to 6V. is a simple diode-
based
implementation of
a two-input OR
+ +
Variable logic gate.
9V 6.2V
Load
- -
•  It takes in two •  For this circuit,
inputs: low or logic 0
–  Va (A) corresponds to a
–  Vb (B) value of 0V and
•  And outputs: high or logic 1
–  Vout (A OR B). corresponds to any
non-zero voltage.
3
•  Using diode analysis, complete the state Va = 0V Va = 3V
table on the next slide to verify that it Vout = 0V
indeed works as an OR gate. Show all Vb = 0V D1 is ON
solutions. Two of the cells are already D2 is OFF
filled in for you. Vout = 2V
Vb = 3V D1 is OFF
D2 is ON
•  0V ! logic 0
•  Nonzero voltage ! logic 1
•  At Va = 3V and •  At Va = 0V and
Vb = 0V: Vb = 3V:
–  D1 is OFF –  D1 is ON
–  D2 is ON –  D2 is ON
–  Vout = 1V –  Vout = 1V
4
Vcc 18V
•  A student is trying •  For this circuit, he
to design a single chooses a supply
R1 IC RC transistor AC signal R1 IC 2.2kΩ voltage of 18V, and
amplifier with a a collector resistor
VC VC
IB voltage divider IB of 2200 ohms.
β β
biasing circuit, as What is the
VE VE
shown on the left. collector current if
R2 RE R2 RE he desires to have
a value for VC
that s half of the
supply voltage?
18V 18V
•  Finding the •  Here, he will place
collector current, the input AC signal
R1 IC 2.2kΩ IC: R1 IC 2.2kΩ at the base
V 18 terminal of the
VC VC = CC = V = 9V VC
IB 2 2 IB transistor, and
β β
VCC − VC take the output at
VE Ic = VE
the collector.
RC
R2 RE R2 RE
18 − 9
Ic = A
2200
IC = 4.0909mA
5
18V 18V
•  The magnitude of •  RE = 220Ω
the gain of the •  After obtaining the
circuit in this case
R1 IC 2.2kΩ R1 IC 2.2kΩ value for RE, he
is given by RC/RE.
VC With this VC
computes the
IB IB
β information in β
values of the two
mind, compute the divider resistors, R1
VE VE
value of the and R2.
R2 RE R2 RE
emitter resistor,
RE, if the
magnitude of the
gain is 10.
18V 18V
•  He wants to design •  How small is the
the divider such base current
R1 IC 2.2kΩ that the base R1 IC 2.2kΩ compared to that
current is small of the R1 current?
VC VC
IB compared to that IB
•  With the current
β ß = 200
of IR1. His gain of the
VE VE
technique is to set transistor given to
R2 RE R1 to be 100 times R2 RE
be 200, and
greater than RC. VBE,ON = 0.6V, what
•  R1 = 220kΩ is R2?
6
18V 18V
•  Finding the base •  The current
current, IB: through R1 may be
R1 IC 2.2kΩ R1 IC 2.2kΩ computed by doing
with IC = 4.0909mA,
a KVL:
IB VC IC 4.0909m IB VC
IB = = A
ß = 200 β 200 ß = 200
VE IB = 20.4545µA VE
R2 RE R2 RE 18 = I R1 + VBE,ON + IER E
R1
18 - (0.6 + (201)(20.4545µ)(220 ))
IR1 =
220k
IR1 = 74.9796µA
18V
•  Comparing IB and •  Solve for the range
IR1: of values for Vin,
R1 IC 2.2kΩ IR1 74.9796 and the
= = 3.666 corresponding Vout,
VC
IB 20.4545
IB such that the
ß = 200 •  Finding R2:
transistor operates
VE R = VB
2 at:
R2 RE IR2
–  Cut-off region
0.6 + (201)(20.4545µ)(220 )
R2 = –  Forward-Active
74.9796µ − 20.4545µ Region
R 2 = 27.593kΩ –  Saturation Region
7
•  Cut-off •  Forward-Active
–  since VBE,ON = 0.7V, –  VCE > VCE,SAT = 0.2V
any Vin value less –  An equation
than that will put involving VCE can be
the transistor in obtained by doing a
cut-off mode KVL at the C-E loop
–  in cut-off mode, all
VCE > VCE,SAT
the currents are
zero, thus Vout = 5 − IC (1000) − IE (100) > VCE,SAT
5V 5 − βIB (1000) − (β + 1)IB (100) > 0.2
–  Vin < 0.7V IB < 43.5967µA
Vout = 5V
•  Forward-Active •  Forward-Active
–  We can relate the –  We can relate the
expression obtained expression obtained
to Vin by doing a to Vin by doing a
KVL at the B-E loop KVL at the B-E loop
IB < 43.5967µA
Vin − IB (1000 ) − VBE,ON − (β + 1)IB (100 ) = 0 Vin − VBE,ON
< 43.5967µA
1000 + (101)(100 )
Vin < 1.1839V
8
•  Forward-Active •  Forward-Active
–  We can compute for –  Finally, we have:
Vout at this point: 0.7V < Vin < 1.1839V
0.64033V < Vout < 5V
at IB = 43.5967µA, Vin = 1.1839V

Vout = 5 − βIB (1000)
Vout = 0.64033V
•  Saturation •  A farmer took a fox, a chicken, and a bag
–  Vin > 1.1839V of grains to market. On the way he came
–  Vout = 0.64033V to a river. There was a boat, but this was
only large enough for him to cross with
one item (the fox, the chicken, or the bag
of grains) at a time.
9
•  If he leaves the fox with the chicken on •  Create a truth table showing all possible
either side of the river, the fox will eat the scenarios, and indicate whether they are
chicken. Similarly, if he leaves the chicken valid or not.
alone with the bag of grains, the chicken •  From the truth table, generate a Boolean
will eat the bag of grains. expression describing the problem.
•  How can the farmer safely cross the river •  Simplify the expression you obtained. You
may use a K-map or the theorems we
and proceed to the market without
discussed.
anything being eaten? The fox, chicken
•  How can the farmer safely cross the river
and bag of grains are unable to row the
and proceed to the market without
boat and thus the farmer must be on the anything being eaten? Show the steps.
boat on every journey.
Use these conventions F X C G V
•  Inputs
1 0 1 0 1
–  F = farmer, X = fox, C = chicken, and G = bag
of grains
–  0 = river side 1 (origin) •  Example case, interpretation
–  1 = river side 2 (destination) –  (F,X,C,G): The fox and the corn are on one
•  Output side of the river, while the farmer and the
–  V = valid/invalid case chicken are on the other side of the river.
–  (V): This case doesn t violate any of the
–  0 = invalid case (farmer leaves fox with
chicken…) restrictions stated in the problem earlier.
–  1 = valid case
10
F X C G V F X C G V
0 0 0 0 1 1 0 0 0 0
0 0 0 1 1 1 0 0 1 0
0 0 1 0 1 1 0 1 0 1
0 0 1 1 0 1 0 1 1 1
0 1 0 0 1 1 1 0 0 0
0 1 0 1 1 1 1 0 1 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 1 1 1 1
•  The Boolean expression based from the •  Let s use a K-map to simplify the
truth table is: expression:
V = F X C G + F X C G + F X CG +
F XC G + F XC G + FX CG + FX CG + FX
CG 00 01 11 10
FXC G + FXCG + FXCG
00 1 1 0 0
01 1 1 1 0
11 0 0 1 1
10 1 0 1 1
11
•  Let s use a K-map to simplify the •  Let s solve the farmer s problem. Here
expression: are the steps:
–  Farmer takes the chicken to the other side of
FX the river.
CG 00 01 11 10 –  Farmer goes back alone.
V = F C + FC +
00 1 1 0 0 FXG + F X G –  Farmer takes the fox (grain) to the other side.
–  Farmer goes back with the chicken.
01 1 1 1 0
–  Farmer takes the grain (fox) to the other side.
11 0 0 1 1 –  Farmer goes back alone.
10 1 0 1 1 –  Farmer takes the chicken to the other side.
•  Given the logical statement: Y = (A+B)(C +D )(A BC+AB D
Y = (A + B)(C’ + D’ )(A’BC + AB’ D + ACD’ + BC’ D) +ACD +BC D)
Y = (A+B)(C (A BC+AB D+ACD +BC D)
–  Expand Y into the canonical form suitable for
use with a K-Map. +D (A BC+AB D+ACD +BC D))
–  Solve for the output logic values of the Y = (A+B)(AB C D+BC D+A BCD +ACD )
canonical form of Y using a truth table.
–  Simplify Y using a K-Map. Y = (A(AB C D+BC D+A BCD +ACD ) +B
–  Get output logic values of the result of the K- (AB C D+BC D+A BCD +ACD ))
Map using a truth table to verify if it has the
same output values as what we got from part Y = AB C D+ABC D+ACD +BC D
b.) +A BCD +ABCD
–  Construct a digital circuit that demonstrates
the simplified expression of Y.
12
Problem 05 BONUS
•  Let s use a K-map to simplify the •  Visit:
expression: http://www.e4.com/game/river-iq/play.e4
•  There is another crossing-the-river game
AB
CD 00 01 11 10 in the site, this time involving a family of
6, a cop, and a criminal. Read the
00 0 0 0 0 Y = BC D + ACD description below the game window.
01 0 1 1 1 + BCD + AC D •  Submit the steps that you took to finish
11 0 0 0 0 the game (that is, everyone crosses the
river). No need to give the truth table.
10 0 1 1 1
13

Problem 01: EEE 1: Essentials of Electrical & Electronics Engineering

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EEE 1 Problem 01

Essentials of Electrical and

EEE 1: Essentials of Electrical & Electronics Engineering

at IB = 43.5967µA, Vin = 1.1839V

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