EENG 212 Digital System Design June 21, 2020

Phoenicia University, Spring 2019–2020 Handout #9

Due: Sunday, June 28, 2020

Problem Set 5

Reminder on Collaboration Policy

The following is an acceptable form of collaboration: discuss with your classmates possible
approaches to solving the problems, and then have each one fill in the details and hand-
write her/his own solutions independently.
An unacceptable form of dealing with homework is to copy a solution that someone else
has written.
At the top of each homework you turn in, list all sources of information you used. A brief
note such as “did problem 2 with Samer in study group” would be sufficient.
In general, we expect students to adhere to basic, common sense concepts of academic
honesty. Presenting another’s work as if it were your own, or cheating in exams will not
be tolerated.

Problem 5.1

Consider the boolean function

F = ΣA,B,C,D (1, 3, 4, 11, 12, 13, 14, 15)

(a) Implement F using a 4-input multiplexer and external gates. Connect A and B to
the select lines.
(b) Implement F using two 3-to-8 decoders with enables, an inverter and two OR gates
with maximum inputs of 4.

Problem 5.2
Implement the function
F = AB 0 + BC 0
using a 3-to-8 decoder (with additional gates). Implement it also using an 8-input mul-
tiplexer. Assume A is the most significant bit.

Problem 5.3
Consider the 1-bit full adder gate (FA) shown below. It takes as inputs A and B and a
carry input Cin, and generates the sum S of A, B, and Cin, and a carry output Cout.
Implement each of the following functions using one FA gate. Label all your inputs
and outputs clearly according to the function to be implemented. Any unused outputs
should be connected to ground.

1
 (a) F1 = X.Y

(b) F2 = X XNOR Y

(c) F3 = X 0

Hint: You can find the equations of Cout and S in lecture 10, slide 2

Example: Solution for F1 :

Connect Cin to 0;
Connect X to A, and Y to B;
Connect S to the ground;
Connect Cout to F1 .

Problem 5.4
Design a combinational logic circuit with 4 data inputs A1 , A2 , A3 , A4 , two control inputs
S1 , S0 , and 4 outputs O1 , O2 , O3 , O4 .The output word is equal to the input word, rotated
to the right circularly by a number of bit positions specified by the control inputs. For
example, if the input word is 1011 and the control inputs are 11, then the output word
is 0111. Label your inputs and outputs clearly.
Hint: You may use 4 multiplexers

Problem 5.5
Write an entity, “MyXOR”, that has two inputs A and B of type std logic, and an out-
put C of type std logic. Write a testench to test this entity and experiment with several
values:
A = 0, B = 0
A = 0, B = 1
A = 1, B = 0
A = 1, B = 1

You should submit your VHDL codes and a snapshot of the output.