ECN-104 Digital Logic Design

Tutorial-4
Instructions:
 Please attempt all the questions before coming to the tutorial class.
 Do not copy from others. We will check your answers using a plagiarism checker. If we found
that you have copied, you will be awarded ZERO marks in Tutorial part of CWS.
 Submission of this tutorial will be announced during the Tutorial class.

1. Draw the Boolean circuit for the following situation. “If the room is not locked and the
lights are ON and the safety latch is open, then open the door and go inside the house.”
A= room locked; B= lights are on; C= safety latch is open and Y= go inside the room.

2. A Boolean function ‘f’ of two variable x and y is defined as follows:

f(0,0) = f(0,1) = f(1,1) = 1; f(1,0) = 0
Assume complement of x and y are not available, what will be a minimum cost solution
for realizing ‘f’ using only 2-input NOR gates and 2-input OR gates, if each gate having
unit cost.

3. Obtain the simplified Boolean expression for output F and G in terms of the input
variables in the circuit shown in the figure below:

If NOT, AND, NAND and OR gates have 1ns, 2ns, 3ns and 2ns propagation delays
respectively, then find the minimum delay to obtain stable output at F and G for a stable
input combination.

4. Design a full adder combinational circuit using half adders. If the initial carry is 1, then
add: A=1011 and B=1101 using full adders. How many full adders are required for this
operation? Show the complete addition process assuming each full adder as a block.

5. An 8X1 multiplexer has inputs A, B and C connected to the selection inputs S2, S1, and S0
respectively. The data inputs I0 through I7 are as follows:
a) I1 = I2 = I7 =0; I3 = I5 = 1; I0 = I4 = D; and I6 = D’.
b) I1 = I2 = 0; I3 = I7 = 1; I4 = I5 = D; and I0 = I6 = D’.
Determine the Boolean function that the multiplexer implements.

6. A combinational circuit is specified by the following three Boolean functions:

F1(A,B,C)=Σ(1,4,6)
F2(A,B,C)=Σ(3,5)
F3(A,B,C)=Σ(2,4,6,7)
Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates
 connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number
of inputs in the external gates.

7. Design a four-input priority encoder with inputs D0, D1, D2 and D3, with input D0 having the
highest priority and input D3 the lowest priority.

8. Implement the following Boolean function with a 4X1 multiplexer and external gates:
a) F1(A,B,C,D) = Σ(1,3,4,11,12,13,14,15)
b) F2(A,B,C,D) = Σ(1,2,5,7,8,10,11,13,15)
Connect inputs A and B to the selection lines. The input requirements for the four data lines
will be a function of variables C and D. These values are obtained by expressing F as a
function of C and D for each of the four cases when AB = 00, 01, 10, and 11. These functions
may have to be implemented with external gates.

9. A combinational circuit is specified by the following three Boolean functions:

F1(A,B,C)=Σ(1,4,6)
F2(A,B,C)=Σ(3,5)
F3(A,B,C)=Σ(2,4,6,7)
Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates
connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number
of inputs in the external gates.

10. Assume that exclusive-OR gate has a propagation delay of 10ns and that the AND or OR gates
have a propagation delay of 5ns. What is the total propagation delay time in the four-bit adder
of carry look ahead adder as shown in the figure below?