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Pulse width modulation based on phase locked loop

Conference Paper · June 2008

DOI: 10.1109/ECTICON.2008.4600526 · Source: IEEE Xplore

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 Pulse Width Modulation
Based On Phase Locked Loop
P. Wisartpong, J. Koseeyaporn, and P.Wardkein
Department of Telecommunication Engineering, Faculty of Engineering,
King Mongkut’s Institute of Technology Ladkrabang, Bangkok, 10520 THAILAND
pramote@telecom.kmitl.ac.th

Abstract- A new circuit structure which improves performance
of a pulse width modulator is proposed in this paper. The
proposed PWM circuit is based on a phase locked loop (PLL)
system where the input signal is fed to combine with the output
of a phase detector (PD). which it achieve a high accuracy
PWM output. In addition , we also use R-S flip-flop and mono-
stable circuit as a phase detector which give rise to get a PWM
modulator that wide input range. The experimental results
agree well with analytical results.
I. INTRODUCTION
It is well-known that modulation is one of many important
processes in communication systems, for example, AM, FM,
PM, ASK, FSK, PSK, PAM, PPM, and PWM. Among
various modulation techniques whose carrier is a square
wave, PWM has played an important role, not only in
communication system but also in other fields. For example,
in power electronic field, PWM is used to be DC-to-DC
converter, and DC-to-AC converter. In control system,
PWM is employed to control motor speed. Additionally, it is
used for a class D power amplifier in acoustic system.
In literature review, most researches were focused on
PWM signal generating [1,4,5]. The methods used for
generating PWM can be categorized into two main groups.
The first group is natural sampling PWM whereas the other
group is uniform sampling PWM. In general, natural
sampling PWM is most widely used. This is because its
circuit is small and simple. Also, a S/H circuit is not
required as it must be in the uniform sampling PWM
counterpart. To generate natural sampling PWM signal, two
schemes can be accomplished. The first scheme employs a
saw-tooth signal which is either directly compared with an
information signal, or first combined with an information
signal before comparing the combined signal with a constant
signal (DC voltage). It is found that modulation index of the
method which directly compares a sawtooth signal with an
information signal is more easily controlled than that of the
other technique. It is noted that modulation index is a duty
cycle of PWM for the zero input signal.
For the second scheme, a triangular wave is used.
Similarly to the sawtooth case, it can be directly compared
with an information signal or first combined with an
information signal before comparing the combined result
with a constant signal. It should be noted that the method
which directly compares a triangular wave with an
information signal will result in a PWM signal with a
constant carrier frequency whereas the other scheme
provides a PWM signal whose carrier frequency is varied
with an information signal.
No matter what a sawtooth signal or a triangular wave is
employed for generating natural sampling PWM signal, one
major drawback of this method is, however, inevitable. It is
found that interference noise can cause error in duty cycle of
the PWM signal. To improve this advantage, various new
methods have been studied and proposed by many
researchers. For example, M. Siripruchyanun et al. proposed
a PWM signal generating circuit using CCII [1]. In 2001,
M. J. Nasila reported the patent name “Phase Locked Loop
Pulse Width Modulation System” in the US, which is the
PWM construction with phase locked loop and the constant
carrier PWM signal is obtained [2]. Later in 2005, Y. Zheng
and his colleague also proposed PWM signal generating
with phase locked loop technique but the proposed circuit
was complicated [3].
In this paper, a method for PWM signal generating based
PLL technique is proposed. Although the concept of the
proposed circuit is quite similar to that of M. J. Nasila but
these techniques are differ in the position of input signal
feeding. In the proposed circuit, the input signal is fed to the
loop filter rather than fed to the VCO as used in [2]. The
mathematical analysis of the proposed circuit will be given
to illustrate the improved performance over that of [2].
Especially, the proposed method provides less error in duty
cycle of PWM signal than that of [2].
The organization of this article is given as follows. The
brief review of PLL is discussed in section II. In section III,
the phase shifter and PWM that is proposed by [2] is
described and analyzed. Later, the proposed phase shifter
and PWM based on PLL are discussed in section IV. In
addition, the R-S flip-flop phase detector is explained in
section V. The experimental results are demonstrated in
section VI. Finally, the conclusions are given in section VI
II. PRINCIPLES OF PLL
The block diagram in Fig. 1 is a conventional phase
locked loop (PLL), which is composed a phase detector
(PD), a loop filter or a low pass filter, a VCO, and an
integrator. It is noted that the notations in Fig. 1 are
 B ωr ωi
φo (t ) = ωit + θi + − (6)
K K
Therefore,
ωi B ωr
φD (t ) = φi (t ) − φo (t ) = − ; K = ABkd ko . (7)
K K

III. ANALYTICAL PHASE SHIFTER AND PWM [2]

Figure 1. Block diagram of a conventional PLL.
A block diagram of a phase shifter and a PWM proposed
φi (s ) Laplace transform of phase input function φi (t ) in [2] is depicted in Fig. 2 where a summing amplifier used
φo (s ) Laplace transform of phase input function φo (t ) to feed the input signal (VC) is placed between a loop filter
ve (s ) Laplace transform of phase error ve (t ) and a VCO.
vL (s ) Laplace transform of loop filter output vL (t )
ωL (s ) Laplace transform of frequency output of VCO ωL (t )
F (s ) Transfer function of loop filter
ωr (s ) Laplace transform of frequency running of VCO
kd Gain of phase detector
ko Gain of VCO
A Gain of loop filter
B Gain of integrator
Figure 2. Block diagram of a phase shifter and PWM [2].
From Fig. 1, the relationship of the system can be written as
From Fig. 2, the relationship of the system can be written as
F (s )Bkdkoφo (s ) F (s )Bkdkoφi (s ) B ωr (s )
+ φo (s ) = + . (1) ABkd koφo (s ) ABkd koφi (s ) BVC ko B ωr (s )
s s s + φo (s ) = + + . (8)
s (1 + Gs ) s (1 + Gs ) s s
By substituting a transfer function of the loop filter as
A By substituting a transfer function of the loop filter as
F (s ) = , into (1), it then yields
1 + GS A
F (s ) = , let K = ABkd ko then (8) is rewritten to be
1 + GS
ABkd koφo (s ) ABkdkoφi (s ) B ωr (s )
+ φo (s ) = + . (2)
s (1 + Gs ) s (1 + Gs ) s Gs 2φo (s ) + s φo (s ) + K φo (s )

For convenience, let K = ABkd ko then (2) is rewritten to be = K φi (s ) + BVC ko + sGBVC ko + B ωr (s ) + BGs ωr (s ). (9)

Gs 2φo (s ) + s φo (s ) + K φo (s ) = K φi (s ) + B ωr (s ) + BGs ωr (s ) . (3) d 2φo (t ) d φo (t )

G + + K φo (t )
dt 2 dt
By taking inverse Laplace transform to both sides of (3), it
GBkod (VC ) d ωr (t )
thus becomes = K φi (t ) + BVC ko + B ωr (t ) + + BG .
dt dt (10)
d 2φo (t ) d φo (t ) d ω (t )
G + + K φo (t ) = K φi (t ) + B ωr (t ) + BG r . (4) But ωr (t ) is actually constant, the first and second derivative
dt 2 dt dt
of this term thus (shown in the right-side of (10)) are zero,
Since ωr (t ) is not a function of time, the first and second hence
derivative of this term (shown in the right-side of (4)) are
zero. Therefore, d 2φo (t ) d φo (t )
G + + K φo (t ) = K φi (t ) + BVC ko + B ωr (t ) . (11)
dt 2 dt
2
d φo (t ) d φo (t )
G + + K φo (t ) = K φi (t ) + B ωr (t ) . (5) In similar to the analyst of the PLL as shown in Fig. 1, the
dt 2 dt
φo (t ) and error phase voltage ( φD ) are
From (5), the solution for φo (t ) can be determined by solving
BVC ko B ωr ωi
this differential equation. In general, φo (t ) is composed of φo (t ) = ωit + θi + + − (12)
K K K
two parts which are homogeneous solution (natural
response) and particular solution (forced response). For this where
work, only steady state response is of interest, the natural
φD (t ) = φi (t ) − φo (t )
response is therefore ignored. To determine the forced
response, let φi (t ) be assumed as φi (t ) = ωit + θi where ωi is ωi BVC ko B ωr (13)
= + − ; K = ABkdko .
an input frequency. Then φo (t ) = at + b where a, b are K K K
constant. By replacing φi (t ) and φo (t ) into (5), hence From (13), it is seen that the error phase voltage ( φD ) is
directly proportional to input signal (VC ). It implies that if
VC is a time varying signal then phase difference will not
φD (t ) = φi (t ) − φo (t )
only depend on information input VC but also depend on the
ωi BVC ko B ωr (20)
first derivative of VC as shown in (10). This leads to error of = + − ; K = ABkd ko .
K K K
phase difference from the input signal. For a time varying
input signal, the relationship between VC and φD in term of Similarly, the transfer function of VC and φD is
transfer function is obtained as given by Bko
φD (ω) = (21)
Bko [1 + j ωG ] (K −G ω 2 ) + j ω 
φD (ω) =  
(K − ω 2 ) + j ω  (14)
  Where magnitude and phase respectively are
where magnitude and phase of φD (ω) are Bko
φD (ω) = 2
, (22)
φD (ω ) =
Bko 1 + ω G 2 2
(K − G ω 2 ) + ω2
2 (15)
(K − ω 2 ) + ω2
 
ω
∠φD (ω) = − tan −1   (23)
 (K − G ω 2 ) 
 
  ω 
∠φD (ω) =  tan−1(ωG ) − tan−1   . (16)
  (K − ω 2 )  By comparing (15) of [2] with (22) of the proposed
 
circuit, it is seen if K  ω , φD (ω ) of [2] shown in (15)
To alleviate problem of error phase difference, a modified
will vary with frequency of the input signal VC . But for the
circuit structure is proposed which will be analyzed in the
following section. proposed circuit, φD (ω ) shown in (22) is less sensitive to
frequency the input signal VC . As described, the proposed
IV. THE PROPOSED PHASE SHIFTER AND PWM circuit is therefore superior to the circuit in [2], especially in
error of phase difference.
The proposed circuit structure is shown in Fig. 3. When it
is compared with the circuit of [2], it is seen that summing
amplifier used to feed the input signal (VC) is instead placed V. R-S FLIP-FLOP PHASE DETECTOR
between a phase detector and a loop filter. In this section, a phase detector using an R-S F/F and a
mono-stable multi-vibrator is described. Conventionally,
phase difference is detected by using an Ex-OR gate where
output of an Ex-OR gate is a PWM signal whose a carrier
frequency is twice of a reference signal. However, it is
found that phase detector based an Ex-OR gate can detect
phase only in range 0 – 180 (or – 90 to 90) degree. To
increase range of phase detection, a new circuit structure of
phase detector by using a R-S F/F and a mono-stable multi-
vibrator is thus employed as shown in Fig. 4. As diagram
shown in Fig. 5, the wide positive pulse of ( φi ) and ( φo )
Figure 3. Block diagram of the propose phase shifter.
signal are decreased by mono-stable multi-vibrator circuit
The relationship of the system shown in Fig. 3 is given by and then fed to S and R position of the R-S flip flop,
respectively.
ABkdkoφo (s ) ABkdkoφi (s ) BVC ko B ωr (s )
+ φo (s ) = + + . (17)
s (1 + Gs ) s (1 + Gs ) s (1 + Gs ) s

Let K = ABkd ko then,

d 2φo (t ) d φo (t )
G + + K φo (t )
dt 2 dt
(18)
d ωr (t )
= K φi (t ) + BVC ko + B ωr (t ) + BG .
dt
In similar to the analyst of the PLL as shown in Fig. 1, the
φo (t ) and phase difference voltage ( φD ) are

BVC ko B ωr ωi Figure 4. R-S flip-flop phase detector.

φo (t ) = ωit + θi + + − (19)
K K K
where

Figure 5. Timing diagram of a phase detector.
VI. EXPERIMENTAL RESUTLS
Firstly, the phase-detector circuit based R-S F/F is
examined with various DC voltage values where output
signal represents phase shifting. As can be seen in Fig. 6, -
the phase detector using R-S F/F is able to detect phase from
350 to 10 degree for 0.5 to 3 input DC voltage, respectively.
It is obvious that this circuit provides wider range of phase
shift than that of using an EX-OR gate.
Later, the proposed circuit is tested with a triangular wave
whose frequency is 15 kHz where the PWM’s carrier
frequency (the output signal of phase detector) is set at 200
kHz. The generated PWM signal is demonstrated in Fig. 7.
Moreover, to compare the performance of the proposed
circuit in term of phase distortion with the circuit proposed
in [2], the following circuit structures are employed :
(a) The circuit proposed by [2] (see Fig. 2) where a phase
detector used is based on an EX-OR gate.
(b) The proposed circuit (see Fig. 3) where a phase
detector used is based on an EX-OR gate.
(c) The proposed circuit (see Fig. 3) where a phase
detector used is based on an R-S F/F.
Figure 6. Phase shifting versus input DC voltage.
Figure 7. Input signal and PWM signal of the proposed circuit.
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In this experiment, the input signal is a 1Vp-p sinusoidal
signal whose frequency is varied from 7 kHz to 12 kHz. The
results of total harmonics distortion obtained from those
described circuits (a) – (c) are illustrated in Fig. 8. It is
obviously seen that the proposed circuit is superior to the
circuit of [2]. In addition, the results obtained from (b) and
(c) in Fig. 8 imply that the phase detector using an R-S F/F
and a multi-vibrator provides more improvement in
performance of the proposed circuit than that of using an
EX-OR gate.
Figure 8. Compared results of total harmonics distortion.
VII. CONCLUSIONS
In this paper, a new structure of the PWM circuit based on
PLL is presented. The mathematical analysis and
experimental results of the proposed circuit shows that this
circuit provides superior performance than the compared
circuit. In addition, a phase detector based an R-S F/F and a
multi-vibrator is employed in the proposed circuit. It
provides wider range of phase detection compared to that of
using an EX-OR gate. The compared results of total
harmonic distortion clearly confirm the improved
performance of the proposed circuit over the compared
circuit structures.
ACKNOWLEDGMENT
The authors would like to thank Telecommunication
Engineering Department, MUT, for encouragement.
REFERENCES
[1] M. Siripruchyanun, P. Wardkein, W. Sangpisit, “A simple pulse width
modulator using current conveyor,” TENCON 2000. Proceedings, vol.
1, pp. 452-457, 2000.
[2] M. J. Nasila, “Phase-Locked Loop Pulse-Width Modulation System,”
United States Patent, Patent No. US6208216B1, 27 Mar. 2001.
[3] Y. Zheng; C.E. Saavedra, ”Pulse width modulator using a phase-locked
loop variable phase shifter,” IEEE International Symposium on
Circuits and Systems (ISCAS2005), Page 3639 - 3642 Vol. 4, 23-26
May 2005.
[4] J.M. Goldberg and M.B. Sandler, “New High Accuracy Pulse Width
Modulation Based Digital-to-Analog Convertor/Power Amplifier”,
IEE.Proc.-Circuits Devices Syst., Vol.141, No.4, pp.315-324. August
1994.
[5] Mehran Mirkazemi-Moud, Barry W. Williams, and Tim C. Green, A
Novel Simulation Technique for the Analysis of Digital Asynchronous
Pulse Width Modulation”, IEEE Transactions on Industry
Applications, Vol.30, No.5, September/October 1994.