4.

Active Loads and IC MOS Amplifiers

Reading: Sedra & Smith: Chapter 7 (MOS portions)

ECE 102, Winter 2011, F. Najmabadi

Progress towards an IC relevant amplifier
 Resistors and capacitors take a lot of space on ICs:
o Minimize (i.e., very few) R & C and small sizes (e.g., nF or smaller)

o Get rid of coupling capacitors by o Replace Rs with a current source

direct coupling between stages o Still need to get rid of Cs!
(makes biasing design complicated) o What to do about RD?
Current mirrors are the principle method
for biasing in ICs

(W / L) 2
Io = I ref
(W / L)1

 Identical MOS: Same k’n and Vt

 Q1 is always in saturation
VDS1 = VGS > VGS – Vt
 Q2 has to be in saturation for
current mirror to work
VDS2 > VGS – Vt
 Small signal model of Current Mirrors
 Small signal response of an ideal current source is an open circuit!
 However, Current mirrors are NOT ideal current sources as we used
λvDS << 1 in our “bias” analysis

Real Circuit

Bias Model Small Signal Model

(W / L) 2
Io = I ref
(W / L)1
 Small signal model of Current Mirrors

Real Circuit Small Signal Model

Current source
becomes open circuit

KCL at D1 : g m1v gs flows in ro1

vD1 = v gs = − g m1v gs ro1 ⇒ v gs = 0
v gs = 0 ⇒ g m 2 v gs current source is open circuit R = ro 2
 But what happens if we replace Iref
current source with “practical” elements?

Not a Practical Circuit Practical Circuit

 Would practical elements that fix Iref change the

small signal response?
 Small signal response of a practical
current mirror
Practical Circuit

KCL at D1 : g m1v gs flows in ro1 || RD

vD1 = v gs = − g m1v gs (ro1 || RD ) ⇒ v gs = 0
v gs = 0 ⇒ g m 2 v gs current source is open circuit R = ro 2
Generalized Small signal Model of
Current Mirrors
Any circuit that
“fixes Iref”

Small Signal Model

iD1 = iref = const.

vDS1 = vGS1 ⇒ Q1 in saturation
1
iD1 = k 'n (W / L)1 (vGS1 − Vtn ) 2 (1 + λvDS1 )
2
⇒ vGS1 = vGS = const. ⇒ vG = const. ⇒ vG → VG
 Summary of Current Mirrors
Bias Model Small Signal Model

(W / L) 2
Io = I ref
(W / L)1

Signal current Bias current

goes through goes through
this leg this leg
(∞ capacitor)
It is sufficient to consider
only Q2 in circuit calculations
 Summary of Current Mirrors
It is sufficient to consider
only Q2 in circuit calculations

“Intuitive” Model

NMOS Version:

PMOS Version:
 Biasing a CS Stage: Can we place a current
mirror in the source circuit?
Typical bias of a
discrete CS amplifier Bias Small Signal

Current mirror Bias works fine!

o A large R in the source circuit for small signal

reducing the gain by (1+ gm1 rO2)

 Placing a current mirror in the source circuit will not Work!

 We need to Bias a CS Stage by placing a
current mirror in the drain circuit!

Bias

Signal

 Current mirror sets ID = Io

Current mirror  However, a precise bias
provides RD ! voltage should be applied
to the Gate (corresponding
to the ID set by the current
source)
 Several ways to do this
 Basic gain cell in IC
NMOS Version:

Av = − g m1 (ro1 || ro 2 )
PMOS Version:
 Bias point of CS amp with current mirror

 Ignore Channel Width Modulation, VSG 2 = VDD − VG

o Fast and relatively accurate
method to find gm1 , ro1 and ro2 VOV 2 = VSG 2 − | Vtp |
o Cannot find VDS1 and VDS2 1
I D2 = k ' p (W / L) 2 V OV
2

2 2

I D1 = I D 2
1/ 2
 2 I D1 
VOV 1 =  
 k 'n (W / L)1 
g m1 = 2 I D1 / VOV 1
ro1 = V A1 / I D1
ro 2 = V A 2 / I D 2
Bias point of CS amp with current mirror
 Include Channel Width Modulation,
o Lengthy Analysis
o Gives VDS1 and VDS2
o See S&S Example 7.2 (pp500-504)
o Can gain insight with load-line analysis

iD2

vDS2
Bias point of CS amp with current mirror
Setting Vss = 0 (For simplicity), the load line (or
load curve!) equation for Q1 is (note iD1 = iD2)
VDD = vSD 2 + vDS 1
Biasing CS amp with current mirror allows
a very large RD without increasing VDD

Q2 in saturation Q2 in triode

Load line for a discrete

resistor of value ro2

Needed VDD
 Biasing a Source Follower in ICs

Current mirror Bias works fine! Small signal OK

 Common-Drain (Source Follower) stages are biased with

current mirror in the source circuit (as above)
 Common-Gate stages are biased with current mirror in the
drain circuit similar to CS amplifier.
 PMOS version of Basic gain cell in IC

NMOS CS Amp PMOS CS Amp NMOS CD Amp PMOS CD Amp

Implementation of CS and Follower
configurations on IC
Cascode Amplifiers and Current Mirrors
 Cascode amplifier is a two-stage,
CS-CG configuration
Cascode Configuration

bias
signal
CG stage

CS stage
 Cascode amplifier is a two-stage,
CS-CG configuration
Small Signal Model
Cascode Configuration

CG stage

Small Signal Model configured as two-stage amplifier

CS stage
Open-Loop gain of a Cascode amplifier

Open Loop Gain

(RL → ∞, io = 0):

By KCL around Q2

Node Voltage Method:

vo − v1
Node vo: − g m 2 ⋅ v1 = 0 ⇒ vo = (1 + g m 2 ⋅ ro 2 ) v1
ro 2
v1
Node v1: + g m1 ⋅ vi + 0 = 0 ⇒ v1 = − g m1 ⋅ ro1 vi
ro1

vo
Avo = = − g m1 ⋅ ro1 ⋅ (1 + g m 2 ⋅ ro 2 ) ≈ − g m1 ⋅ ro1 ⋅ g m 2 ⋅ ro 2
vi
Output Resistance of a Cascode amplifier

ro (1 + g m R ) + R

Ro = ro 2 (1 + g m 2 ⋅ ro1 ) + ro1

Ro = ro1 + ro 2 + g m 2 ro1 ro 2

Exercise: Compute Ro from the small signal circuit of the previous slide
(Attach a voltage source vx to the output and compute ix, see S&S pp 509-510)
 Amplifier models*
Voltage Amplifier
Ideal Amplifier
Avo : Open-Loop
voltage gain Ri → ∞
Ro = 0
vo = Avo vi for io = 0

Transconductance Amplifier

Gm : Short-circuit
transconductance Ri → ∞
io = Gm vi for vo = 0 Ro → ∞

Current Amplifier

Ais : Short-circuit
current gain Ri = 0
io = Ais ii for vo = 0 Ro → ∞

* See S&S pp 26-27

 Amplifier models
Voltage Amplifier

 From the point of view of circuit analysis:

amplifier models are identical
 (The output stages are
Thevenin/Norton Equivalent)
Transconductance Amplifier
 Avo , Ais , and Gm are related to each other
For i0 = 0 vo = Avo vi = Gm vi Ro
Avo = Gm Ro

Current Amplifier
Avo = Gm Ro
Ais = Gm Ri
Avo = ( Ro / Ri ) Ais
 Amplifier models*
Voltage Amplifier

vo = Avo vi for io = 0

Transconductance Amplifier

io = Gm vi for vo = 0 Avo = Gm Ro

Alternate method to compute Avo:

1. Set RL = 0 (short output)
2. Compute Gm = io/vi
3. Avo = Gm Ro
 Example: CS amplifier gain from Gm
Alternate method to compute Avo:
1. Set RL = 0 (short output)
CS Amplifier
2. Compute Gm = io/vi
3. Avo = Gm Ro

0
Short circuit

io = − g m ⋅ v gs

io = G m vi = G m v gs
Gm v gs = − g m v gs
Transconductance Amplifier
Gm = − g m
Ro = ro

Avo = Gm Ro = − g m ro

Gm = − gm because current source is flipped

 Cascode amplifier gain from Gm
v gs1 = vi and v gs 2 = −v1

Node equation at v1
v1 v
+ g m1v gs1 − g m 2 v gs 2 + 1 = 0
ro1 ro 2
 1 1 
 + + g m 2  v1 = − g m1vi
 ro1 ro 2 
ro1ro 2 g m1
v1 = − vi
ro1 + ro 2 + ro1ro 2 g m 2

v1 v
io = − g m1 ⋅ v gs1 − = − g m1 ⋅ vi − 1 KCL at D1
ro1 ro1

io g r (1 + g m 2 ro 2 )
Gm = = − m1 o1
vi ro1 + ro 2 + g m 2 ro1ro 2
Avo = Gm Ro = − g m1ro1 (1 + g m 2 ro 2 ) ≈ − g m1ro1 g m 2 ro 2
Ro = ro1 + ro 2 + g m 2 ro1ro 2
 Insight into operation of Cascode amplifier
For simplicity assume ro1 = ro2 = ro and gm1 = gm2 = gm

Cascode amplifier: Ro = ro1 + ro 2 + g m 2 ro1ro 2 = ro (2 + g m ro ) ≈ g m ro2

g m1ro1.(1 + g m 2 ro 2 ) g r (g r )
Gm = − ≈ − m o m2 o = − g m
ro1 + ro 2 + g m 2 ro1ro 2 g m ro

CS amplifier (1st Gm1 = − g m and Ro = ro

stage of cascode):

 CG section has kept Gm the same (i.e., since Gm = io/vi , same

current is passed through) but has increased Ro substantially
resulting in a large increase in overall open-loop voltage gain!
 CG section acted as a current buffer!
 Cascode amplifier needs a large load!
Distribution of the gain in a Cascode Amp.

CS Stage CG Stage

Av 2 = g m 2 (ro 2 || RL )
ro 2 +RL 1 RL
RL1 = Ri 2 = ≈ +
1 + g m 2 ro 2 g m 2 g m 2 ro 2
CG stages “reduces” the load seen by the
Av1 = − g m1 (ro1 || Ri 2 ) CS stage by gm2ro2

Av = Av1 Av 2
 Cascode Amplifier needs a large load

For simplicity assume ro1 = ro2 = ro and gm1 = gm2 = gm

Av1 = − g m1 (ro1 || Ri 2 ) Av 2 = g m 2 (ro 2 || RL ) ro 2 +RL 1 RL

RL1 = Ri 2 = ≈ +
1 + g m 2 ro 2 g m 2 g m 2 ro 2

RL Ri2 = RL1 Av1(CS) Av2 (CG) Av= Av1 Av2

∞ ∞ − gmro gmro − (gmro)2 Max. Gain

Practical
(gmro) ro = Ro ro − 0.5gmro gmro − 0.5(gmro)2
Gain

ro 2/gm −2 0.5 gmro − gmro Same gain

as a CS Amp.
 Cascode amplifier is a two-stage,
CS-CG configuration
Small Signal Model
Cascode Configuration

CG stage

Small Signal Model configured as two-stage amplifier

CS stage
 Cascode Amplifier needs a large load

For simplicity assume ro1 = ro2 = ro and gm1 = gm2 = gm

Av1 = − g m1 (ro1 || Ri 2 ) Av 2 = g m 2 (ro 2 || RL ) ro 2 +RL 1 RL

RL1 = Ri 2 = ≈ +
1 + g m 2 ro 2 g m 2 g m 2 ro 2

RL Ri2 = RL1 Av1(CS) Av2 (CG) Av= Av1 Av2

∞ ∞ − gmro gmro − (gmro)2 Max. Gain

Practical
(gmro) ro = Ro ro − 0.5gmro gmro − 0.5(gmro)2
Gain

ro 2/gm −2 0.5 gmro − gmro Same gain

as a CS Amp.
 Cascode amplifier needs a large load to
get a high gain

Current RL = ro3
Mirror
Av ≈ − gmro

 Gain did not increase compared to a CS

amplifier.
Cascode
 This is still a useful circuit because of its
high gain-bandwidth (we see this later).
 To get a high gain, Av = − 0.5(gmro)2 ,
we need to increase the small-signal
resistance of the current mirror to
≈ (gmro) ro
o Cascode current mirror
 Cascode Current mirror
 Identical MOS: Same k’n and Vt ,
and (W / L) 4 (W / L) 2
=
(W / L) 3 (W / L)1

 Usually: (W/L)1 = (W/L)3 and

(W/L)2 = (W/L)4

 Q1 and Q3 are always in saturation

 Q2 and Q4 have to be in saturation
for current mirror to work
 VDS2 > VGS – Vt
 VDS4 > VGS – Vt
 Straight forward to show
(W / L) 2
Io = I ref
(W / L)1

Exercise: For VSS = 0, show that a single current mirror (no cascoding) works only if
VD2 > VOV and a cascode current mirror requires VD4 > Vt + 2VOV
Small signal resistance of a cascode
current mirror is quite large

Ro = ro 4 (1 + g m 4 ⋅ ro 2 ) + ro 2
Equivalent Small-signal
circuit circuit
 Cascode amplifier with a
cascode current mirror
Bias

Cascode
current mirror

Cascode
Signal
amplifier
 Cascode amplifier with a
cascode current mirror

Cascode
current mirror

ro 3 (1 + g m 3 ⋅ ro 4 ) + ro 4

Cascode
amplifier

 A high gain, Av ≈ − 0.5(gmro)2 , high gain-bandwidth circuit.

 Draw-back: Low voltage headroom because 4 MOS should be in
active for a given VDD
 Folded Cascode increases voltage overhead

NMOS CS stage PMOS CG stage

Biased with I1 – I2

Exercise: Draw the small-signal circuit of a folded cascode and show that it is exactly
the same as a regular cascode.