ESE - 2020 Mains Test Series: Electronics & Telecommunication Engineering

1 TEST CODE: 605
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ESE - 2020 Mains Test Series

Electronics & Telecommunication Engineering
Test – 5 on Basic Electrical Engineering + Analog & Digital Circuit
(Paper – I)
Solutions
01. (a)
Sol: ‘T’ is the torque in N-m, which is defined as the turning force about an axis, than gross mechanical
power developed is
 2N   2N 
Pdev = T = T  ……. (1)    
 60   60 
Pdev = Eb Ia ……….(2)
2NT
 Eb Ia =
60
 zNP  2NT  zNP 
  Ia   E b  
 60A  60  60A 
T
1  Ia 
 z .P  
2  A  2
1
zI a P A  
T = 0.159 zIa (P/A)
Where,  = flux/pole , z = no. of conductors
P = no. of poles , A = no. of parallel paths
Ia = armature current, N = speed in rpm
Eb = back emf
 = angular speed
As z, P, A are constants
 T  Ia
(i) Shunt motor:  = constant
T Ia
 T  Ia  2  2
T1 I a1
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: 2 : ESE 2020 Mains Test Series
(ii) Series motor:    constant

2
T2 I a 2
 T  Ia 
2

T1 I a21
and also P = T  EbIa = T
EI
 T b a

01. (b)
Sol: Volume of water = 1 million cubic meter
Density of water, Pw = 893 kg/m3
 Mean head, H = 45 m
Losses = negligible
  = 100%
Energy produced by the water is,
E =  mgH =  (PV)gH
= (1) (893) (106) (9.8) (45)
= 3.938 × 1011 J
= 3.938 × 105 MJ
= 109.38 MWh
01. (c)
Sol: is +VCC
+ –
Vd Ao
– + +
–VEE
Vs +– if
Vx Vo
i1
RF
R1
–
Since the current drawn by the op-amp is zero, i1 = – if. That is,
Vx  V  Vo 
  x 
R1  RF 
R1
Vx  Vo ___(1)
R1  R F
The output voltage Vo is
Vo = Ao[Vs – Vx] = AoVd ___(2)
The input voltage at the non-inverting terminal is the sum of Vx and Vd. That ig,
Vs = Vx + Vd
R1Vo V
Vs   o  Eq (1) & (2) 
R1  R F A o
 R1 1 
Vs  Vo   
 R1  R F A o 
: 3 : Electronics & Telecommunication Engineering
The closed-loop voltage gain Af is given by
V A o R1  R F  1  R F / R1 1  R F / R1
Af  o    ___(3).
VS A o R1  R1  R F 1  1  R F / R1  / A o 1 x
1  RF 
Where x  1  
A o  R1 
For a small value of x which is usually the case, (1+x)–1  1–x and eq.(3) can be approximated
by
 R 
Af  1  F 1  x 
 R1 
Therefore, the error introduced for a finite value of gain Ao is x.
395k
1
(i) x  5k  40  105  40  103%
2  105 k
1  395 / 5
Af   79.968
1  40 10 5
(ii) The output voltage Vo is
Vo = AfVs = 79.96810010–3 = 7.9968V
(iii) The error in the output voltage Vo is
 R 
Vo  x 1  F   40 105  80  32mV
 R1 
01. (d)
Sol: In BCD, 0-9 are used codes and 10-15 are unused codes.
BCD 9’s Complement of BCD
A B C D D3 D2 D1 D0
0 0 0 0 1 0 0 1
0 0 0 1 1 0 0 0
0 0 1 0 0 1 1 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 0 0
0 1 1 0 0 0 1 1
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 x x x x
0 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
(D3) = f(A,B,C,D) = m (0,1) + d (10,11,12,13,14,15)

(D2) = f(A,B,C,D) = m (2,3,4,5) + d (10,11,12,13,14,15)
(D1) = f(A,B,C,D) = m (2,3,6,7) + d (10,11,12,13,14,15)
(D0) = f(A,B,C,D) = m (0,2,4,6,8) + d (10,11,12,13,14,15)
Truth tables for output bits:-
D3 D2
CD CD
AB AB
1 1 1 1
D3 = ABC 1 1
x x x x D2 = BC + BC x x x x
x x = BC x x
D1
CD CD
AB AB
1 1 1 1
1 1 D1 = C 1 1
x x x x D0 = D x x x x
x x 1 x x
A
D3
B D2
C D1
D D0
01. (e)
Sol:
(i) Fan out:
The fan-out of a gate specifies the number of standard loads that can be connected to the output of
the gate without degrading its normal operation. A standard load is usually defined as the amount
of current needed by an input of another gate in the same logic family. Exceeding the specified
maximum load may cause a malfunction because the circuit can’t supply the power demanded
from it. The fan out of the gate is calculated from the ratio I0H / IIH or I0L / IIL, which is smaller.
(ii) Power dissipation:
Every electronic circuit requires a certain amount of power to operate. The power dissipation is a
parameter expressed in milliwatts (mW) and represents amount of power needed by the gate.
The amount of power that is dissipated in a gate is calculated from the supply voltage VCC and
current ICC is drawn by the circuit. The current drain from the power supply is depends on the logic
state of the gate. The current drawn from the power supply when the output of the gate in the high
voltage level is termed ICCH . When the output is in the low voltage level, the current is ICCL.
I I
The average current is ICC avg   CCH CCL
2
and is calculated by using PD(avg) = VCC  ICC(avg)
(iii) Propagation delay:
The propagation delay of a gate is the average transition-delay time for the signal to propagate
from input to output when the binary signal changes in value.
The signal through a gate takes a certain amount of time to propagate from inputs to the output.
This interval of time is defined as the propagation delay of the gate. Propagation delay is measured
in nano seconds (ns). The signal delay time between the input and output when the output changes
from the high to the low is referred to as tPHL. Similarly, when the output goes from the low to the
high level, the delay is tPLH. The average propagation delay time calculated as average of the two
delays.
t t
The average propagation delay = PLH PHL
2
Input
time
Output
tPHL tPLH
(iv) Noise margin:
Noise margin is the maximum noise voltage added to an input signal of a digital circuit that does
not cause an undesirable change in the circuit output. The ability of circuits to operate reliably in
noise environment is important in many applications. Noise margin is expressed in volts and
represents the maximum noise signal that can be tolerated by the gate.
VCC VCC
VOH
VIH
VIL
V0L
0 0
Output voltage range Input voltage range
Any voltage in the gate output between VCC and V0H is considered as the high-level state and any
voltage between 0 and VOL in the gate output is considered as low-level state.
Voltage between V0L and V0H are indeterminate and do not appear under normal operating
conditions except during transition. In order to compensate for any noise signal, the circuit must be
designed so that VIL is greater than VOL and VIH is less than V0H.
The noise margin is the difference V0H – VIH or VIL – V0L, whichever is smaller.
02. (a)
Sol:
Power Transformer Distributed Transformer
1. Used in transmission network 1. Used in distribution network
2. The voltage level > 33 kV 2. The voltage level < 33 kV
3. Rating of transformer > 1 MVA 3. Rating of transformer  1 MVA
4. Load fluctuations are minimum. 4. Load fluctuations are high
5. Loaded fully throughout 24 hours 5. Loaded based on the load cycle of
consumer.
6. Both Cu & Iron losses take place throughout 6. Iron losses take place 24 hours but Cu.
24 hours losses take place based on load cycle of
consumer.
7. Cu. Losses kept min while designing 7. Iron losses kept minimum while designing
transformer transformer
8. High flux density Bmax 8. low flux density Bmax
9. Specific weight is less 9. Specific weight is high
Iron weight Iron weight
10. is less 10. is more
Cu weight Cu. weight
11. Average load is nearer to F.L 11. Average load is 70 – 75% of F.L
12. These are designed to give max at F.L (or) 12. Designed to give max at 70 – 75% of F.L
near to F.L
13. F.L. Cu loss  Iron loss 13. F.L. Cu loss  2 × Iron loss
14. Power basis 14. Energy basis
15. Power efficiency is defined 15. Energy  is defined
02. (b)
Sol:
(i) Given, Vt1  1V, Vt 2  1.5V, k n1  150A / V2 , and k n 2  100A / V2 .
The two possible transfer characteristics that can result from the variations in the parameters are
shown below. iD
VG
R SR
I D1
I D1 , VGS1  slope 
1
R SR
I D2 (I D 2 , VGS2 )
VGS
0 Vt1 VGS1 Vt 2 VGS2

ID1  k n1 VGS1  Vt1   150 10  V
2 6
GS1 1 2
ID 2  k n 2 VGS2  V   100 10  V

t2
2 6
GS2  1.5 2
 For a drain current variation of I D1  5mA  20%

= 5mA(1 + 0.2) = 6mA
We have, 6mA = 150A  (VGS1 – 1)2
Which gives an operating value of VGS1 = 7.32V
 For a drain current variation of I D2  5mA  20% = 5mA (1–0.2) = 4mA.
We have, 4mA  100A  VGS2  1.5   2
Which gives an operating value of VGS2 = 7.825V

The slope of the biasing load line gives the value of RSR:
VGS2  VGS1 7.825  7.32
R SR   103 = 252.5 
ID1  ID 2 64
Now, VG  VGS2  I D2 R SR  7.825  4  103  252.5 = 8.835V.
The value of R1 and R2 can be found from,
R V R 15
VG  2 DD  2  8.835V
R1  R 2 R1  R 2
R
Which gives 1  1  1.7
R2
Choosing a suitable value of R2, usually larger than 500k. Assuming R2 = 500k, R1 = 350k
(ii) A complementary push-pull amplifier is shown below.
QN
+
+
vI . QP RL vO
–
–
–VCC
For vI > 0, transistor QP remains off and transistor QN operates as an emitter follower. For a
sufficiently large value of vI, QN saturates and the maximum positive output voltage becomes
VCE(max) = VCC – VCE1(sat)
For vI < 0, transistor QN remains off and transistor QP operates as an emitter follower. For a
sufficiently large negative value of vI, Qp saturates and the maximum negative output voltage
becomes –VCE(max) = – (VCC – VCE2(sat)) = – VCC + VCE2(sat)
Assuming identical transistors of VBE1 = VBE2 = VBE, the output voltage is given by
v0 = vI – VBE for –0.7 V  vI  0.7 V
which gives the transfer characteristics of v0 versus v1 shown below.

V0
QN saturates
VCC – VCE(sat)
QN on
–0.7 V QP off
QN off
QP on
–VCC + VCE(sat)
QP saturates
Transfer characteristic
However, during the interval –0.7 V  v1  0.7 V, both QP and QN remain off, and v0 = 0. This
causes a dead zone and crossover distortion on the output voltage, as illustrated in figure below
v0
V0
VCC – VCE1(sat)
Slope = 1
VBE2 0 t3 t4
0
Slope = 1 VBE1 vI t1 t2 t5 t
– VCC – VCE2(sat)
t1 vI
t2
t3
t4
t
Fig :Crossover distortion on input and output waveforms

Let us assume that VCE1(sat) = VCE2(sat) = VCE(sat) = 0 and IC(min) = 0. Assuming a sinusoidal variation
of the collector current iC1 = Ip sin(t), the average collector current of a transistor can be found
from
1  1  Ip
   
2 0 2 0
I C1  i dt  I sin t d t 

c1 p
The average current drawn from the DC supply source by transistors QN and Qp is
2I p
I dc  2 I C1 

Thus the average input power supplied from the DC source is
2I V
PS  I dc VCC  P CC

The output power is given by
I2 R I V
PL  P L  P P
2 2
Thus, the power efficiency becomes
P I V /2  V 
 L  P P   P 
PS 2I P VCC /  4  VCC 
Which given  = 50% at VP = 2VCC/ and  = 78.5% at VP = VCC.
At VP = VCC, the maximum output power is given by
I 2P R L I P VP  P VCC VCC 2
PLmax     
2 2 2 2R L
Thus, the maximum power efficiency is
P I V /2 
max  Lmax   P CC   78.5%
PS 2I P VCC /  4
Therefore, the maximum efficiency of a complementary push-pull class B amplifier is much
higher than that of a class A amplifier.
02. (c)
Sol:
(i) Universal shift register has the following capabilities:
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift-right control to enable the shift right operation and the serial input and output lines
associated with the shift right.
4. A shift-left control to enable the shift-left operation and the serial input and output lines
associated with the shift left.
5. A parallel load control to enable a parallel transfer and then input lines associated with the
parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in response to the clock.
A register capable of shifting in one direction only is a unidirectional shift register one that can
shift in both directions is a bidirectional shift register. If the register has both shifts and parallel
load capabilities is referred to as a universal shift register.
The block diagram and circuit diagram of a three bit universal shift register that has all the
capabilities as listed. The circuit contains of three D flipflops and three multiplexers. These
multiplexers have two common selection inputs s1 and s0. Input 0 in each multiplexer is selected
when s1s0 = 00. Input 1 is selected if s1s0 = 01, and similarly for the others two inputs. The
selection inputs control the mode of operation of the shift register according to the function. When
s1s0 = 00, the present value of the register is applied to the D flipflop. This condition forms a path
from the output of each flipflop into the input of the same flipflops, so that the output re-circulates
to the input in this mode of operation. The next clock edge transfers into each flipflop the binary
value it held previously and no change of state occurs.
Apar
s1 3
s0
Shift LSBin
MSBin register
CLK 3
CLR Ipar
 When s1s0 = 01, terminal 1 of multiplexer inputs has a path to the D inputs of the flipflops.
This cause shift-right operation with several input transferred to A2.
 When s1s0 = 10, a shift left operation results, with the other serial input going into flipflop A0.
 When s1s0 = 11, the binary information on the parallel input lives is transferred to the register
MODE Register
s1 s0 operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
Simultaneously during next clock edge. Note that data enters MSB in for a shift right operation and
enters LSB in for a shift left operation clear is an active-low signal that clears all of the flipflops.
Parallel outputs
A2 A1 A0
Q Q Q
CLR FF FF FF
C D C C
D D
CLK
s1 y y y
MUX MUX MUX
s0
32 1 0 32 1 0 32 1 0
Serial input Serial input

for shift right for shift left
I2 I1 I0
Parallel inputs
(ii) (1) (digital value)  (resolution)  VA + VT
(digital value)  (40mV)  6.001V
(digital value)  (40mV)  6001mV
digital value  150.025
The digital output is 100101112 =(151)10
(2) (Digital value)  40mV  6.036V
(digital value)  40mV  6036mV
digital value  150.9
(3) Maximum conversion time = (2n – 1)T
= (2n – 1)/f = 102s
102s
Average conversion time =  51s
2
03. (a)
Sol:
EV V 2  1 1 
(i) P = sin    sin 2
Xd 2  X q X d 
1.4 1 12  1 1 
= sin      sin 2
0.8 2  0.5 0.8 
= 1.75sin + 0.375sin2
dP
For maximum power  =0
d
dP d
  1.75 sin   0.375 sin 2  = 0
d d
= 1.75cos + 0.75cos2 = 0
= 1.75cos + 0.75(2cos2  1) = 0
= cos2 + 1.167cos 0.5 = 0
  = 70.73
 Pmax = 1.75sin70.73 + 0.375sin2  70.73
= 1.88 pu
(ii) No. of parallel paths, A = P = 4
E  60 A 262  60 4
Flux/pole,  =  =  = 0.0603 Wb
Nz P 400  652 4
 60
Pole shoe arc = D  =   0.42  = 0.07
360 360
Pole shoe length = 20 cm = 0.2 m
Pole shoe area, A = Pole shoe arc  pole shoe length
= 0.07   0.2 = 0.044 m2
 0.0603
Flux density in the airgap, B = =
A 0.044
= 1.37 T
03. (b).
Sol:
(i) A n-bit ripple counter counts 2n states. For example, 10-bit ripple counter 1024 states from 0 to
1023.Similarly this given counter counts upto 16,38310.
So,2n ≥ 16,383
n = 14,
So, it is a 14-bit ripple counter it uses 14 flipflops to count upto 16,38310.
fc
 f at MSB =
2N
fc = f at MSB  2N
The output frequency at MSB id 0.5kHz, then,
Clock frequency = 0.5kHz  214 = 8.192 MHz
1
(ii) In N-bit Asynchronous (Ripple) counter, the frequency of equation is f 
N t pdFF
1
Here minimum value of propagation delay is asked, then f 
N t pdFF
1
10  10 6   t pdFF  10ns
10  t pdFF
(iii) Mod-6 counter means it counts from 0 to 5. Here, counter counts 000,001,011,010,110 and 111.
It requires n = 3FF’s (N ≤ 2n) 3 Flipflop will have 8 states and remaining 2 states (101 and 100)
are invalid.
000
001
111 011
110 010
State diagram
Excitation table
Present States Next States Required
excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
1 0 1 x x x x x x
1 0 0 x x x x x x
K-maps for excitations T3:- K-maps for excitations T2:-
Q2Q1 Q2Q1
Q3 Q3
 1
x x 1 x x 1
T3  Q 3Q1  Q 3Q 2 Q1 T2  Q3Q1  Q 2 Q1
K-maps for excitations T1:-
Q2Q1
Q3
1 1
x x 1 1
T1  Q3  Q2 Q1  Q 2 Q1
Q3Q1 Q 2 Q1 Q3 Q1
Q 3 Q 2 Q1
Q3
Q2Q1
Q 2 Q1
T1 Q1 T2 Q2 T3 Q3
FF1 FF2 FF3
Q1 Q2 Q3
CLK
Logic diagram of mod-6 gray counter
03. (c)
Sol:
(i) For Z = 1 M, employing Miller’s theorem results in the equivalent circuit shown below
Rsig 1 2
+ +
Vsig + Vi + Z2 Vo
 Z1 –
– –100Vi –
Z 1000k
Where Z1    9.9k
1  K 1  100
Z 1M
Z2    0.99M
1 1
1 1
K 100
The voltage gain can be found as follows:

V0 Vo Vi Z1 9.9
  100   100   49.7 V / V
Vsig Vi Vsig Z1  R sig 9.9  10
1
(ii) For Z as a 1-pF capacitance that is, Z = = 1/s  1  10–12
sc
Applying Miller’s theorem allows us to replace Z by Z1 and Z2, where
Z 1 / sC 1
Z1   
1  K 1  100 s101C
Z 1 1 1
Z2   
1 1.01 sC s1.01C 
1
K
It follows that Z1 is a capacitance 101C = 101 pF and that Z2 is a capacitance 1.01C = 1.01 pF.
The resulting equivalent circuit is shown below, from which the voltage gain can be found as
follows:
Rsig 1
+ +
+ Vi + Vo
Vsig
 Z1 – Z2
– 100Vi –
Vo Vo Vi 1 / sC1   100
  100 
Vsig Vi Vsig 1 / sC1   R sig 1  sC1R sig
 100  100
 12

1  s  101  1  10  10  10 3
1  s  1.01  10 6
This is the transfer function of a first-order low-pass network with a dc gain of –100 and a 3-dB
frequency f3dB of
1
f 3dB   157.6 kHz
2  1.01  10 6
04. (a)
Sol: Transformer is a static device. The induced emf is statically induced emf.
If N1 and N2 are the number of turns on the primary and secondary respectively, and if m is the
maximum value of the flux in weber, having a frequency of ‘f’ Hz, then
2 m
The average rate of change of flux =
1 / 2.f 
= 4 m f wb/sec
(Here, the flux changes from +m to –m in half a cycle (or) in 1/2f sec)
 Average induced emf/turn = 4f m Volt
 Sinusoidal waveform, RMS value = 1.11 × Average value
 RMS value of induced emf/turn = 1.11 ×4f m Volts/turn
 Total induced RMF = 4.44 N mf, Volt
 Induced EMF in primary winding,
E1 = 4.44 N1 mf, Volts
Induced RMF in secondary winding
E2 = 4.44 N2 mf, Volts
E1
 Induced EMF/turn on primary winding = = 4.44 m f
N1
E
Induced EMF/turn on secondary winding = 2 = 4.44 m f
N2

 EMF
turn

prim

 EMF
turn
sec
04. (b)
Sol: VL1 = 220V, f = 50 Hz, R2 = 0.1 Ω, X2 = 0.9 Ω
N1
= 1.75; SF.L = 5% = 0.05
N2
V 220
Vph  L  = 127 Volts = V1
3 3
N V 1
 2  2  V2   127 = 72.6 V
N1 V1 1.75
R
Z2 = 2  jx 2
s
0. 1
(at 5% slip) =  j0.9 = 2+ j0.9
0.05
= 2.19 Ω
V 72.6
 The rotor current, I2 = 2  = 33.14 A
Z 2 2.19
Rotor Cu losses = 3 I 22 R 2
= 3 × (33.14)2 × 0.1
= 329.47 W
rotor . Cu loss
 Rotor input =
Slip
329.47
=
0.05
= 6589 W
120  50
 Ns = synchronous speed = = 1500 rpm
4
2N s
s = = 157 rad/sec
60
6589
 Torque = = 42 N-m
157
 Rotor output = (1 – s) rotor input
= (1 – 0.05) 6589 = 6259 W
6259
 HP = = 8.4 hp
746
3  72.6 
2
3E 22 8785
Tmax =   = 56 N-m
s 2X 2 157  2  0.9 157
R 1
 Slip at Tm  2  = a
x2 9
 1
N rT max  N s 1  a   15001   = 1333 rpm
 9
04. (c)
Sol:
(i) Given Rs = 2k, Vs = 100mV and Vo = –8V. The source resistance is in series with R1
 R1 = R1 + Rs
R1 = R1 + 2k ___(1)
V 8
Af  o   80 ___(2)
Vs 100  103
 RF
A f  80   R F  80R1 ___(3)
R1
The maximum input resistance is
Is(max) = 10A
V 100mV
R inmin   s   10k
is max  10A
R1 = R1 + Rs = Rin(min) = 10k
Thus, RF = 80(R1 + Rs) = 8010k = 800k
R1 = R1 – Rs = 10k – 2k = 8k
Rx = R1||RF = 10k||800k
Rx = 9.876k
(ii) Load resistance RL = 80 
N1
Turns ratio 5
N2
Load on the primary side of transformer:
2
N 
Turns ratio R L   1  R L = (5)280 = 2000 
 N2 
Imax = 2IC and Imin = 0
1  I max  I min 
So, rms value of current, I rms 
2  2 

1
  2I C
2 2
I
 C
2
I
Maximum power output, Pout(ac)  I 2 rms R L  C R L
2

120  10 
3
 2000  14.4 W

2
04. (d)
Sol:
(i)
Accumulator Flag register

B C
D E
H L
Stack pointer
Program counter
Data bus Address bus
bidirectional
unidirectional
S Z X AC X P X CY
D7 D6 D5 D4 D3 D2 D1 D0
The programming model consists of some segments of the ALU and the registers. This model
includes six registers, one accumulator, and one flag register. In addition, it has two 16-bit
registers i.e., stack pointer and program counter.
Registers:
The 8085 has six-general purpose registers to store 8-bit data; these are identified as B,C,D,E,H
and L. They can be combined as register pairs – BC, DE, HL to perform 16-bit operations. The
programmer can use these registers to store or copy data into the registers by using copy
instructions.
Accumulator:
The accumulator is an 8-bit register that is part of the ALU. This register is used to store 8-bit data
and to perform arithmetic and logic operations. The result of an operation is stored in the
accumulator.
Flags:
The ALU includes five flip flops, which are set or reset after an operation according to data
conditions of the result in accumulator and other registers. They are called zero (Z), carry (CY),
sign (S), parity (P), and auxiliary carry (AC) flags. The most commonly used flags are zero, carry
and sign. The microprocessor uses these flags to test data conditions.
These flags have critical importance in the decision making process of the microprocessor. The
conditions (set or reset) of the flags are tested through software instructions. For example, the
instruction JC (Jump on carry) is implemented to change the sequence of a program when the CY
flag is set. The thorough understanding of flags is essential in writing assembly language
programs.
Z – zero: the zero flag is set to 1, when the result is zero; otherwise it is reset.
CY-carry: If an arithmetic operation results in a carry, the CY flag is set; otherwise it is reset.
S – sign: The sign flag is set if bit D7 of the result = 1; otherwise it is reset.
P – parity: If the result has an even number of 1’s, the flag is set; otherwise for an odd number of
1’s, the flag is reset.
AC – Auxiliary carry: In an arithmetic operation, when a carry is generated by digit D3 and passed
to digit D4, then flag is set. This flag is used internally for BCD operations; there is no jump
instruction associated with this flag.
Program counter (PC) and stack pointer (SP)
There are two 16-bit registers used to hold memory addresses. The size of these registers is 16 bits
because the memory addresses are 16-bit.
The microprocessor uses the PC register to sequence the execution of the instruction. The function
of the program counter is to point to the memory address from which the next byte is to be
fetched. When a byte is being fetched, the program counter is incremented by one to point to the
next memory location.
The stack pointer is also a 16-bit register and used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading a
16-bit address in the stack pointer.
(ii) In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode:-
In immediate addressing mode the source operand is always data. If the data is 8-bit, then the
instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B 45(move the data 45H immediately to register B),
LXI H 3050 (load the H-L pair with the operand 3050H immediately),
JMP address (jump to the operand address immediately).
2. Register Addressing Mode:-
In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is (are) operands. Therefore the operation is performed within various registers of the
microprocessor.
Examples:
MOV A,B (move the contents of register B to register A),
ADD B(add contents of registers A and B and store the result in register A),
INR A(increment the contents of register A by one).
3. Direct Addressing Mode:-
In direct addressing mode, the data to be operated is available inside a memory location and that
memory location is directly specified as an operand. The operand is directly available in the
instruction itself.
Examples:-
LDA 2050 (load the contents of memory location into accumulator A),
LHLD address (load contents of 16-bit memory location into H-L register pair),
IN 35(read the data from port whose address is 01).
4. Register Indirect Addressing Mode:-
In register indirect addressing mode, the data to be operated is available inside a memory location
and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contains of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
5. Implied / Implicit Addressing Mode:-
In implied / implicit addressing mode the operand is hidden and the data to be operated is available
in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
(iii) XRA A
MOV B, A
Loop: INR B
ADD B
MOV C, A
MOV A, B
CPI 0AH
MOV A, C
JNZ Loop
MOV A, C
STA 2500H
HLT
05. (a)
Sol: Rating = 50 kVA; V1 = 11000 V; V2 = 440 V, f = 50 Hz, R1 = 7.8 Ω, R2 = 0.0085 Ω
R01 = ? R02 = ? WFL = ?
V 440 V
K 2  = 0.04
V1 11000 V
Equivalent resistances refer to primary, R01 = R1 + R 2
R
= R1 + 22
K
0.0085
= 13.1125 Ω
= 7.8 +
(0.04) 2
Equivalent resistance reference to secondary, R02 = R2 + R1
= R2 + K2R1
= 0.0085 + (0.04)2 (7.8)
= 0.02098 Ω
50  10 3
F. L. primary current, I1  = 4.545 A
11  103
 F.L.Cu loss = I12 R 01
= (4.545)2 × 13.11
= 270.87 W
50  103
F.L. secondary current, I 2  = 113.64 A
440
 F.L Cu. Loss = I 22 R 02
= (113.64)2 × 0.02098
= 270.87 W
05. (b)
Sol: V = 440 V, f = 50 Hz, P = 6, Power = 80 kW, I2 = 65 A,
100
f2 = 100 cycles/min = cycles/sec = 1.67 Hz
60
f 1.67
(i) s = r  = 0.0333 = 3.33%
f 50
120  50
(ii) Nr = Ns(1 – s) = 1  0.0333 = 966.7 rpm
6
(iii) Pmech = rotor input × (1 – s) = 80 × 103 (1 – 0.033) = 77.33 kW
(iv) Rotor Cu. Loss = s × rotor input = 0.0333 × 80 = 2.666 kW
2.66 kW
 Rotor copper Loss/ph = = 0.8886 kW
3
(v) Rotor current, I2 = 65 A
I 22 R 2 = 888.6 W
888.6 W
R2 = = 0.21 Ω
65
R2/ph = 0.21 Ω
05. (c)
Sol:
(i) The application of a positive supply voltage results in a conventional current that matches the
arrow of the green diode and turns it on.
The polarity of the voltage across the green diode is such that it reverse biases the red diode by the
same amount. The result is the equivalent network given below.
+8V
20mA
+
2V
–
Applying ohm’s law, we obtain

8V  2 V
I = 20mA =
R
6V
R  300
20mA
Comment: If the green diode were to be replaced by a blue diode, problem would develop as
shown below +8V
+ +
5V > Vrmax 5V
–
–
Note that the reverse bias voltage of the red LED is 5V, but the reverse breakdown voltage of the
diode is only 3V. The result is the voltage across the red LED would lock in at 3V as shown
below.
+8V
+
3V
–
8V  3V
R  250
20mA
Therefore, the voltage across the resistor would be 5V and the current limited to 20mA but neither
LED would be ON.
(ii) The offset due to VIO is

R1  R f  5k  500k 
Vo(offset due to VIO)  VIO  4mV   = 404mV
R1  5k 
Vo(offset due to IIO) = IIORf = (150nA)(500k) = 75mV
Vo(total offset) = Vo(offset due to VIO)+Vo(offset due to IIO)
= 404mV + 75mV = 479mV
05. (d)
Sol: P = 6, wave winding, A = 2, z = 87 × 6 = 522
 = 20 mWb, Ra = 0.13 Ω, V = 240 V, Ia = 80A ,N = ? T = ?
Eb = V – IaRa = 240 – 80(0.13) = 229. 6 V
3
zNP 20  10  522  N  6
Eb =  229.6 
60A 60  2
 N = 439.8 rpm  440 rpm
 P = T
 2N 
EbIa = T 
 60 
E I (60) 229.6  80  60
 T b a  398.63 N-m
2N 2    440
05. (e)
Sol:
(i) Self complementary codes are the codes have the property that 9’s complement of a decimal digit
is obtained directly by replacing 1’s by 0’s and 0’s by 1’s i.e., by complementing each bit pattern.
If a code word is formed by complementing each bit individually (changing 1’s to 0’s and 0’s to
1’s), then this new code word represents the 9’s complements of a digit to which the original code
word corresponds.
Ex: 2421 code, excess-3 code, 84-2-1 code etc.
Decimal digit 2421 code Excess-3 code 84-2-1 code
0 0000 0011 0000
1 0001 0100 0111
2 0010 0101 0110
3 0011 0110 0101
4 0100 0111 0100
5 1011 1000 1011
6 1100 1001 1010
7 1101 1010 1001
8 1110 1011 1000
9 1111 1100 1111
Example: Decimal 395 is represented in the excess-3 code as 0110 1100 1000. The 9’s
complement of 604 is represented as 1001 0011 0111. Which is obtained simply by
complementing each bit of the code (as with 1’s complement of binary numbers).

(ii) FA, B, C, D  AB  AB CD  CD  
 
F  F  AB  AB CD  C D  AB  AB  CD  C D     
 
= AB. A.B  CD.C D  AB. A  B . CD .C D 
 
 
As per statement given i.e., only input variables are available. So,
AB C D
AB AB.A  B
F
A+B
CD
 
 CD.CD 
 
CD
05. (f)
Sol: 3-bit Even parity generator:
An even parity generator outputs a 1, when the number of 1’s in the data bits are add, so that the
total numbers of 1’s in the data bits and the parity bit together is even.
3-bit Data Input Output
B3 B2 B1 Fe
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Fe = (B2,B1,B0) = m(1,2,4,7)
B1B0
B2
1 1
1 1
Fe = B2B1B0
B2
B1 Fe
B0
4-bit Even parity checker:

In the received data (data bits + parity bit) bits, if the number of 1’s even, there is no error, else
there is an error.
B2 B1 B0 Pe Error (ferror)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
ferror = (B2 , B1 , B0 , Pe) = m (1,2,4,7,8,11,13,14)
B0Pe
B2B1
1 1
1 1
1 1
1 1
ferror = B3B2B1Pe
B2
B1
ferror
B0 =1 error
=0 No error
Pe
06. (a)
Sol:
(i) Selection of Site:
(1) Hydro power plant:
 Sufficient quantity of water at a reasonable head should be available.
 More area is required for reservoir and dam
 It should allow strong foundation with low cost
 There should not be any leakage of water in future
 The selected site should have large catchment area, to maintain a certain water level
 Distance of power station site from load centres must not be longer. This is to minimize the
transmission cost
 Construction materials shall be available very near
 submergence area shall be minimum
(2) Thermal power plant:
 The site should be nearest to the coal mines so that transport cost of fuel is minimum.
 Large quantity of cooling (for the condenser) water should be available
 The land should not be rocky and marshy
 The chimney of the plant, do not obstruct the flying aero planes i.e., the site should be away
from the airport
 The site should not be surrounded by residential building to avoid nuisance of smoke, noise
etc
 If the station is located, near the load center, the distribution cost reduces
 Facility for the disposal of ash
(3) Nuclear power plant:
 Sufficient availability of water for cooling purpose
 The waste produced by fission in a nuclear power station is generally radio active which
must be disposed off properly to avoid health hazards
 The site selected for a nuclear power plant should be quite away from the populated areas as
there is a danger of presence of radio activity in atmosphere near the plant
(ii) Advantages and Dis-advantages:

(1) Hydro power plant:
Advantages:
 No cost of fuel
 Low maintenance cost
 High plant 
 Free from pollution
 Used as multipurpose projects
 Cost per unit is less
 Suitable for variable heads
Disadvantages:
 High initial cost
 Located in remote area and require more cost on transmission lines
(2) Thermal power plant:

Advantages:
 Can be located near the load centers
 requires less space compared to hydro power plant
 requires less transmission & distribution
Dis-advantages:
 Pollution due to smoke
 Running cost is more than hydro power plant
(3) Nuclear Power Plant:
Advantages:
 Amount of fuel required is quite small
 requires less space
 low running cost
 reliable & economic for bulk generation
Dis-advantages:
 not suitable for varying loads
 difficult to make casing of the reactor
 disposal radio active product is a major problem.
06. (b)
Sol:
(i)
VCC
R1
R2 5k Q1
+
C 2VCC 1
–
3
S Q
5k
R Q output
VCC
+
3 2
–
TR144ER
5k
Fig. Astable multivibrator.

Operation
Let initially Output is HIGH Q  1
Q  1  Q  0  switch open  current through the transistor Q1 is 0.
Thus, the equivalent network is as below,
VCC
+
R1 R2 C VC
–
VC (initial) = 0
VC (final) = VCC
Thus, VC has to get charged from 0 to VCC, while VC is getting charged from 0, it has to reach
VCC
first.
3
V
At VC  CC ,
3
VCC
VC  o/p = low
3 +
2VCC 1 S=0
–
3 S Q
VCC Q
o/p = low R
3 +
2 R=0
VC 
VCC –
3
 Q will not charge (∵ S = 0, R = 0)

2V
At VC  CC ,
3
2VCC o/p = high
VC 
3 +
2VCC 1 S=1
–
3 S Q
VCC o/p = low
R Q
3 +
2 R=0
2VCC –
VC 
3
Q = 1 Q  0  output = 0
i.e., output has changed from HIGH to LOW.
Now, Q  0 Q  0  Q  1  switch is closed.
Therefore, the equivalent network is as below.
VCC
R1
 +
R2 R2 C VC
–
2VCC
VC (initial) 
3
VC (final) = 0
VCC
Thus, capacitor will get discharged from to 0.
3
VCC
 At VC 
3
VCC o/p = low
VC 
3 +
2VCC 1 S=0
–
3 S Q 0
VCC o/p = High
+
R Q 1
3
2 R=1
VC 
VCC –
3
Q  1  output  high
Thus, output is getting changed from low to high. Hence, the circuit is behaving as a
astable multivibrator. The output wave form and voltage across capacitor are shown below.
output
VC
2VCC
2
VCC
3
TH TL
Calculating TH and TL :
2VCC V
TH : Time taken for VC to reach from CC
3 3
VCC  
T1
 R1  R2 C

  VCC 1  e 
3  
 2
 T1   n R 1  R 2 C
 3
2VCC   T2 
  VCC 1  e
3  R1  R 2 C 
 1
 T2   n R 1  R 2 C
 3
TH = T2 – T1 = n 2R1  R 2 C
TH  0.693R1  R 2 C
2VCC VCC
TL : Time taken for VC to reach from to .
3 3
Similarly, we will get, TL = 0.693C
TL = 0.693R2C
TH 0.693R 1  R 2 C
Duty cycle  
TH  TL 0.693R 1  R 2 C  0.693R 2 C
R  R2
% Duty cycle  1  100
R 1  2R 2
(ii)
+VCC
IR VCE 2
R1
I C1 I C2  I 0
I B1 I B2
Q1 Q2
+ +
VBE1 VBE 2
– –
The simplest current source consists of a resistor and two transistors as shown in above circuit.
Transistor Q1 is diode connected, and its C-B voltage is forced to zero; vCB = 0. Thus, the C-B
junction is off, and Q1 will operate in the active region. Transistor Q2 can be in the active region as
well as in the saturation region. Let us assume that Q1 and Q2 are identical transistors whose
leakage currents are negligible and whose output resistances are infinite. Since the two transistors
have the same B-E voltages (i.e., VBE1 = VBE2), the collector and base currents are equal: IC1 = IC2
and IB1 = IB2. Applying KCL at the collector of Q1 gives the reference current:
IR = IC1 + IB1 + IB2 = IC1 + 2IB1
Since IC1 = FIB1,
2I C1
I R  I C1  2I B1  I C1 
F
Given, VBE1 = VBE2 = VCE1 = 0.7V and VA = 150V
IR
I 0  I C 2  I C1 
2
1
F
5A
Which, for I0 = 5µA gives I R   5.1A
2
1
F
VCC  VBE1 30 V  0.7 V
R1  =  5.75M
IR 5.1A
06. (c)
Sol:
(i) Reasons for Segmented Memory:-
 8086 has a 20-bit address bus. So it can address a maximum of 1MB of memory and each memory
location is addressed by a 20 bit address.
 To hold a 20-bit address there must be a 20-bit address register available within processor but
8086 only has 16-bit registers. So, 20-bit address can’t be stored inside the 16-bit register.
To avoid this problem segmented memory is used in 8086.
Total 1MB memory can be divided into some equal size segments each of having capacity 64KB.
So, max no. of segments is 16. (1MB/64 KB = 16).8086 can work with only four 64KB segments
at a time within this 1MB range.
Each location in a particular segment can be expressed by two addresses.
(i) Segment Address (16 bit): It refers the starting address of a segment and it is fixed for whole of
the segment.
(ii) Offset or Displacement Address (16 bit): It refers the individual location in that segment and it
is varied location wise.
By using these two addresses the 20 bit physical address can be calculated as below:
Physical address (20 bit) = [Segment Address (16 bit)* 10]H + Offset Address (16 bit)
According to this formula segment address is multiplied by 10 and is added to offset. This is
equivalent to shifting of segment register content towards left 4 times so that four zero are added
to right side (MSB) of the segment address and added with the offset address to get the physical
address which is 20bit.
Offset Address (16 bit)
Segment Register (16 bit) 0000
Adder
Physical Address (20 bit)
Ex:
Given Segment Address = 3578H, Offset Address = 6676H
So Physical address = [Segment Address * 10]H + Offset Address
= [3578 * 10]H + 6676H
= 35780 + 6676
= 3BDF6H
(ii) Whenever an interrupt occurs the processor completes the execution of the current instruction and
starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program
that tells the processor what to do when the interrupt occurs. After the execution of ISR, control
returns back to the main routine where it was interrupted.
In 8086 microprocessor, following tasks are performed when microprocessor encounters an
interrupt:
1. The value of flag register is pushed into the stack. It means that first the value of SP (Stack
Pointer) is decremented by 2 then the value of flag register is pushed to the memory address of
stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type)*04.
5. CS is loaded from the next word location.
6. Interrupt and Trap flag are reset to 0.
The different types of interrupts present in 8086 microprocessor are given by:
1. Hardware Interrupts:-
Hardware interrupts are those interrupts which are caused by any peripheral device by sending a
signal through a specified pin to the microprocessor.
There are two hardware interrupts in 8086 microprocessor. They are:
(A) NMI (Non Maskable Interrupt) – It is a single pin non-maskable hardware interrupt which
cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its execution,
this interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008 H and CS is
loaded from the word location 0000A H.
(B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by Input port.
This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive any
interrupt type, so the value of IP and CS will change on the interrupt type received.
2. Software Interrupts – These are instructions that are inserted within the program to generate
interrupts. There are 256 software interrupts in 8086 microprocessor. The instructions are of the
format INT type where type ranges from 00 to FF. The starting address ranges from 00000H to
003FFH. These are 2 byte instructions. IP is loaded from type * 04H and CS is loaded from the
next address give by (type*04) + 02H. Some important software interrupts are:
(A) TYPE 0 corresponds to division by zero(0).
(B) TYPE 1 is used for single step execution for debugging of program.
(C) TYPE 2 represents NMI and is used in power failure conditions.
(D) TYPE 3 represents a break-point interrupt.
(E) TYPE 4 is the overflow interrupt.
(iii) In minimum mode, 8086 microprocessors MN / MX pin set to logic 1. In this mode, all the control
signals are given out by the microprocessor chip itself. There is a single microprocessor in the
minimum mode system. The remaining components in the system are latches, Transreceivers
clock generator, memory and I/O devices. Latches are generally buffered output D-type flipflops.
They are used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They
are required to separate the valid data from the time multiplexed address/data signals. These are
controlled by DEN and DT / R .
The DEN signal indicates the direction of data i.e., from or to the processor. The system contains
memory for the monitor and users program storage.
M / IO - Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is
low. It indicate the CPU is having an I/O operation, and when it is high, it indicates that CPU is
having memory operation.
INTA - interrupt acknowledge:- This signal is used as a read strobe for interrupt acknowledge
cycles. i.e., when it goes low, the processor has accepted the interrupt.
ALE – Address Latch Enable: This output signal indicates the availability of the valid address on
the address/data lines, and is connected to latch enable input of latches. This signal is active high
and is never tristated.
DT / R - data transmit/receive:- This output is used to decide the direction of data flow through the
transreceiver. When the processor sends out data, the signal is high and when the processor is
receiving the data, this signal is low.
DEN – data enable:- this signal indicates the availability of valid data over the address/data lines.
HOLD, HLDA:- when the HOLD line goes high, it indicates to the processor, after that another
master is requesting the bus access. The processor, after receiving the HOLD request, issues the
hold acknowledge signal an HLDA pin in the middle of the next clock cycle after completing the
current bus cycle. At some time, the processor floats the local bus and control lines when the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous
input, and is should be externally synchronized.
07. (a)
Sol: No. of slots per pole per phase, SPP, m = 4
 Total no. of slots, S = 4  4  3 = 48
P  180 4  180
Slot angle,  = = = 15
S 48
Coil span,  = 10 slots = 10  15 = 150
Short pitch angle = 180   = 180  150 = 30
 30
Therefore, pitch factor Kp = cos = cos = 0.9659
2 2
m 4  15
sin sin
Distribution factor, Kd = 2 = 2 = 0.957
 15
m sin 4  sin
2 2
 Double layer winding no. of coils = no. of slots = 48
 Total no. of turns = 48  20 ; since, 20 turns/coil
48 20
Turns per phase = = 320
3
Eph = 4.44 Kp Kd  f Tph
15  103 = 4.44  0.9659  0.957   × 50  320
  = 0.2284 Wb
 The flux/pole,  = 0.2284 Wb
07. (b)
Sol: Given Stator Input power Psi = 47.4 kW, No of poles, P = 4, Supply Frequency, f = 50 Hz
Armature winding resistance (stator winding resistance R1 = 0.056 
Operating Speed or the rotor speed Nr = 1448 rpm, Stator current, I1 = 76.2 A
120f 120  50
Ns = = = 1500 rpm
P 4
Stator output power (or) Air gap power (or) Rotor Input power
I2R 76.2 2  0.056
Pso = Pri = Psi  Stator ohmic loss = 47.4  3 1 1 = 47.4  3  = 46.42 kW
1000 1000
Rotor power dissipation or the rotor loss Pr1 = sPri = sPso
N  N r 1500  1448
s= s  = 0.03467
Ns 1500
Pr1 = sPri = 0.03467  46.424 = 1.6 kW
Rotor Power Dissipation =1.6kW
Rotor output power or the gross mechanical power developed Pro = Pri(1  s)
Pro = Pgmd = Pri(1  s) = 46.424(1  0.03467) = 44.81 kW
Given the total friction, windage, and core losses =2250 Watt =2.25 kW
Therefore, the net mechanical power
Pnet = Pgmd = constant losses = 44.81  2.25 = 42.56 kW
P 42.56
Motor efficiency motot = net   100 = 89.8%
Psi 47.4
07. (c)
Sol:
(i) In BCD addition, the output of addition is invalid if the result is greater than 910 (or) carry occurs.
To correct this result a value of 610 is added to it.
629.8  0110 0010 1001. 1000

(+) 746.7 (+) 0111 0100 0110. 0111
1 3 7 6.5 1101 0110 1111. 1111
0110 0110. 0110
0001 0011 0111 0110. 0101
1 3 7 6 . 5
(ii) In BCD subtraction, the output of subtraction is invalid if borrow occurs (or) results greater than
910. To correct this result a value of 610 is subtracted from it.
379.6  0011 0111 1001. 0110
– 885.9  1000 1000 0101. 1001
– 506.7 1010 1111 0011. 1101
0110 0110 0110
0100 1001 0011. 0111
If minuend is greater than subtrahend the obtained result will be 10’s complement form.
 –(10’s complement of result) = 0100 1001 0011. 0111

4 9 3 . 7
= –(9’s complement + 1) = – (999.9 – 493.7 + 1 added to LSD)
= –506.3
07. (d)
Sol:
(i) Initially it might appear that the applied voltage will turn both diodes “ON” because the applied
voltage is trying to establish a conventional current through each diode that would suggest the
“ON” state. However, it both were ON, there would be more than one voltage across the parallel
diodes, violating one of the basic rules of network analysis:
The voltage must be the same across parallel elements. The resulting action can best explained by
remembering that there is a period of build-up of the supply voltage from 0V to 12V even though
it may take milliseconds or microseconds. At the instant the increasing supply voltage reaches
0.7V. The silicon diode will turn “ON” and maintain the level of 0.7V. Since the characteristic is
vertical at this voltage. The current of the silicon diode will simply rise to the defined level.
The result is that the voltage across the green LED will never rise above 0.7V and will remain in
the equivalent open-circuit state as shown below.
12V
+
0.7V
–
Vo
2.2k
 Vo = 12V – 0.7V = 11.3V
(ii)
800k
Rf
10k
– –
R1 Vd Ao
+ + +
+
100mV Vo
– Rx
Vo
From the figure, Vo = AoVd  Vd  ___(1)
Ao
The input current is through R1 can be found from
V  Vd Vs  Vo / A o
is  s  __(2)
R1 R1
From the figure, Vo = –Vd – ifRF
= –Vd – isRF (∵ if  is)
V V  Vo / A o
 o  s .R F (∵ (1) & (2))
Ao R1
V R F / R1  RF
Af  o    ___(3)
Vs 1  1  R F / R1  / A o  R1 1  x 
1  RF 
Where x  1  
A o  R1 
For a small value of x, which is usually the case, (1+x)–1  1–x
Thus, equation (3) can be approximated by
R
A f   F 1  x 
R1
Therefore, the error introduced for a finite value of gain Ao is x.
 1  80 
x  5 
 40.5  10 5  40.5  10 3%
 2  10 
 80
From eq (3), A f   79.9676

1  40.5  10 5 
08. (a)
Sol:
(i) No load armature current, I a 0  I L 0  I sh
=2–1
=1A
N.L input to the motor = 250 × 2 = 500 W
N.L Cu loss = I a20 R a  12 1 = 1W
 Total const. Losses on N.L, Wconst = 500 – 1

= 499 W
If Ia is current corresponding to max, then
Ia2 R a  Wconst
= 499
499
 Ia  = 22.34 A
1
 IL corr. to max, IL = Ia + Ish = 22.34 + 1 = 23.34 A
 Input to the motor = 250 × 23.34
= 5835 W
Armature Cu loss = (22.34)2 × 1 = 499 W
At max  armature Cu loss = const. loss = 499
 total losses = 499 + 499
= 998 W
 output of the motor, output = Input – total losses
= 5835 – 998
= 4837 W
output 4837
 max =  100 = 82.9%
input 5835
(ii) Applications of DC motors:

(1) Shunt motor: For driving constant speed equipment such as lather, centrifugal pumps,
machine tools, blowers, fans, reciprocating pumps and constant speed line shafting.
(2) Series motor: Used when high starting torque required.
For traction work, lifts, cranes, electric railways, conveyors, hoists and trolley cars.
(3) Compound motors: These are used for applications involving intermittent high torque loads,
such as hoists, punches, shears, stamping processes, rolling mills conveyors, elevators.
08. (b)
Sol:
(i) The voltage-controlled current source representation is shown below
+
Vi Ri GmVi R0
–
R3
C L R
where trans-conductance Gm = A/R0. Ri is in parallel with R, and we let R1 = Ri || R. Also, R0 is in
series with R3, and we let RF = R0 + R3. The equivalent circuit is shown below
+ +
Vi AVi
– –
RF = R 0 + R3
+ +
Vf C L R1 = R||R0 V0
– –
which represents the amplifier as an ideal voltage amplifier. The feedback transfer function  of
the feedback circuit is given by
 j
jL ||   || R1
Vf  c 
  j    j  
V0  j
jL ||   || R1  R F
 c 
which can be simplified to give the loop gain as
jLA
A  j  
R F 1   LC   jL1  R F / R1 
2
This will provide a 0 phase shift at the resonant frequency 0 given by

1
0  in rad / s 
LC
At this frequency, the magnitude of A(j) becomes
A
A j 
1  R F / R1
RF
Which must be equal to 1 and gives the condition for oscillation as  A 1
R1
That is, for A = 50, RF / R1 = 49. Let R1 = Ri || R = 5kΩ; then, for Ri = 10kΩ, R = 10kΩ.
Therefore, RF = R0 + R3 = 49R1 = 245kΩ
Thus, for R0 = 200Ω, R3 = 244.8kΩ
ox 3.45  10 11

(ii) (1) Cox   9
 4.32  10 3 F / m 2  4.32 fF / m 2
t ox 8  10
 
k n   n C ox  450 cm 2 / V .s  4.32 fF / m 2  
   
 450  108 m 2 / V.s  4.32  1015 F / m 2  194  106 F / V.s   194 A / V 2
(2) For operation in the saturation region,

1 W 2
i D  k n V0 V
2 L
1 8 2
Thus, 100   194  V0 V
2 0.8
Which results in V0V = 0.32 V
Thus, VGS = Vt + V0V = 1.02 V
and VDSmin = V0V = 0.32 V
(3) For the MOSFET in the triode region with vDS very small,
1
rDS 
W
k n V0 V
L
1
Thus 1000  6
194  10  10  V0 V
Which yields V0V = 0.52 V
Thus VGS = 1.22 V
08. (c)
Sol:
(i)
Inputs Outputs
A B bi D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
D = f(A,B,bi) = m(1,2,4,7)
B = f(A,B,bi) = m (1,2,3,7)
A 3 to 8
B
bi Decoder
(ii) From the truth table of full subtractor
D = f(A,B,bi) = m (1,2,4,7)
B = f(A,B,bi) = m (1,2,3,7)
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Here, 1  8 demux is choosen, so that it requires 3 selection lines i.e., A,B,bi and input is always
high(1)
Y0
Y1
Y2 D
I=1 Y3
18
DeMUX Y4
Y5
Y6 B
Y7
S2 S1 S0
A B bin
(iii) From the truth table of full subtractor

D = m (1,2,4,7)
B = m (1,2,3,7)
Let us consider 4:1 MUX, so it has 2 selection lines and 4 input lines. Here A,B are choosen as
input lines
For D:
A BI 0  ABI1  A BI 2  AB I 3 
C 0   6
C  3 5 
I0 = C ; I1 = C ; I2 = C ; I3 = C
For B:
A BI 0  ABI1  A BI 2  AB I 3 
C 0  4 6
C   5 
I0 = C ; I1 = 1 ; I2 = 0 ; I3 = C
C I0
C I1
C I2 MUX Y0 D
C I3
S2 S1
A B
C I0
1 I1
0 I2 MUX Y1 B
C I3

ESE - 2020 Mains Test Series: Electronics & Telecommunication Engineering

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1 TEST CODE: 605

ESE - 2020 Mains Test Series

(ii) Series motor:    constant

(D3) = f(A,B,C,D) = m (0,1) + d (10,11,12,13,14,15)

ID 2  k n 2 VGS2  V   100 10  V

 For a drain current variation of I D1  5mA  20%

Which gives an operating value of VGS2 = 7.825V

(ii) A complementary push-pull amplifier is shown below.

which gives the transfer characteristics of v0 versus v1 shown below.

Fig :Crossover distortion on input and output waveforms

Serial input Serial input

The voltage gain can be found as follows:

Accumulator Flag register

(ii) In 8085 microprocessor there are 5 types of addressing modes:

Applying ohm’s law, we obtain

(ii) The offset due to VIO is

4-bit Even parity checker:

ferror = (B2 , B1 , B0 , Pe) = m (1,2,4,7,8,11,13,14)

(ii) Advantages and Dis-advantages:

(2) Thermal power plant:

Fig. Astable multivibrator.

 Q will not charge (∵ S = 0, R = 0)

Offset Address (16 bit)

Segment Register (16 bit) 0000

Physical Address (20 bit)

629.8  0110 0010 1001. 1000

 –(10’s complement of result) = 0100 1001 0011. 0111

 Vo = 12V – 0.7V = 11.3V

 Total const. Losses on N.L, Wconst = 500 – 1

(ii) Applications of DC motors:

This will provide a 0 phase shift at the resonant frequency 0 given by

ox 3.45  10 11

(2) For operation in the saturation region,

(iii) From the truth table of full subtractor

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