EE479

Class Final Project

High-Speed CMOS Operational Amplifier
(Due Date: Monday, December 14, 2009, 6pm)
1. Introduction
This purpose of the EE479 final project is to design a state-of-the-art Low-Voltage, Low-
Power, High-Speed, High-Gain CMOS operational amplifier in the TSMC 180nm CMOS
technology process that can be used in the Image Sensor Product.

2. Required Performance
The following table summarizes the required performance for your designed final
operational amplifier.

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Table 1: Final Operational Amplifier Target Performance

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 Table 2: DC Operating Point of the Operational amplifier Devices

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Table 3: Hand-Analysis Parameters for TSMC 180nm process

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 a. Input common-mode range of the project opamp is 1 V. The supply Vdd is 2V. If we
have each current source and its cascade device stacked at the output, then the output
swing is: Vss + 2 x Vds < Vout < Vdd - 2 x Vds.

b. We design the Vdsat for each device to be equal to 150mV.

c. To be in saturation, we have to have: Vds > Vdsat. Suppose we choose

Vds=Vdsat+100mV. This way we have a good margin of 100mV into the saturation
regions. In that case Vds=250mV

d. If we assume the Maximum Vds is Vds(max)=250mV, then the output swing is:
0+2 x 250mV < Vout < 2 - 2 x 250mV, which is 0.5V< Vout < 1.5V

e. We choose 25uA as a unit reference dc bias current. And for Vdsat=150mV, the aspect
ratios for nMOS and pMOS devices becomes: W/L=5 for nMOS and W/L=20 for pMOS.

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f. To make the transistor fast, we have to make L (channel length) as small as possible. To

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make the transistor high gain, we have to increase L. But aspect ratio must remain the

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same.

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Table 4: Selection of Device Sizes for the Design Target

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g. Use the Project Phase II to generate the four levels of bias voltages for opamp. The total
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dc current consumption of the four-level low-voltage bias generator is only 6 x 25uA =

150uA = 0.15mA. This is negligible in comparison to the total amplifier current
consumption which is 25mA.
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h. Because the open-loop gain of the opamp is 90dB, we may or may not have to have two-
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stage op-amp. Usually each stage must give you about 40-50 dB gain.

i. The power consumption of the operational amplifier must be less that 50mW. This means
that the current consumption of the opamp is less than 25mA. Because of stability issues
(will be covered in the class) the second stage of the operational amplifier usually
consumes twice as much current as the first stage.

First stage Current consumption = 5 to 10 mA

Second stage Current consumption = 10 to 20 mA

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 3. Deliverable in your report
(A) Write a professional report. Hand writing reports will NOT be accepted.

(B) Put each graph, each table, and each schematic in one page by itself.

(C) All the pMOS body terminals are connected to Vdd and all the nMOS body
terminals are connected to Vss.

(D) Your report must explain the hand analysis of your circuit: (1) analysis of the first
stage, (2) analysis of the second stage, (3) compensation circuit (4) Slew-Rate,
and (5) open loop DC gain, (6) Unity Gain Frequency, (7) First-Pole frequency,
(8) Second-Pole Frequency, (9) Zero Frequency. Use the Table 3 for hand-
analysis parameters. For all the DC bias (quiescent) hand analysis, assume λ=0

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(E) The report must have only and only the following 10 items (each item is in one

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page): 1 schematic, 7 graphs, and 2 tables.

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(F) Schematic: Show your complete circuit schematic (Bias + First Stage + Second

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Stage) very clearly. Be sure that your schematic is readable.
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(G) Graph 1: Item # 5, 6, and 7: Shows the Frequency Response, Show the unity-gain-
bandwidth frequency, and phase margin measurement
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(H) Graph 2: Item # 8: Shows the Transient Response of your amplifier using one-volt
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step input. Show input and output signals and settling behavior super imposed..
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(I) Graph 3: Item # 9: Shows the common-mode input range, use 100Hz (low-
frequency triangular waveform representing DC) input signal. Show input and
output signals super-imposed.
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(J) Graph 4: Item # 12 and 13: Shows positive and negative slew-rates with input and
output signals super-imposed.

(K) Graph 5: Item # 14: Shows the Common-Mode-Reject Ratio Frequency

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Response.
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(L) Graph 6: Item # 15: Shows the positive power supply rejection ratio.

(M) Graph 7: Item # 16: Shows the negative power supply rejection ratio.

(N) Complete Table 1, final operational amplifier target performance.

(O) Complete Table 2, DC operating point for the devices in the operational amplifier.

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