EE479

Class Project Phase II : Opamp First Stage

1. Introduction
This purpose of the final project is to design a state-of-the-art Low-Voltage, Low-Power,
High-Speed, High-Gain CMOS operational amplifier in the TSMC 180nm CMOS technology
process.

2. Required Performance
Table 1 summarizes the required performance for your designed final CMOS operational
amplifier. It also indicates the priorities of performance parameters.

Parameter Description Required Achieved Value Priority

m
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Power Supply Voltage (Vdd) 2 2 V --------

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Temperature (Room) 25 25 °C --------

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TSMC 0.18um Process Corner Typical Typical ----- --------

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Output Load Capacitor
rs e 1 1 pF --------
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Opamp Open Loop DC Gain (Avo) > 100 dB 1
Opamp Unity Gain-Bandwidth Product (UGBW) >1 GHz 1
Phase Margin > 60 Degree 1
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Settling Time (0.01% for 1V output step) < 10 ns 1

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Common-Mode Input Range >1 V 2

Supply Current Consumption (Idd) < 25 mA 2
Power Consumption (Vdd X Idd) < 50 mW 2
ed d

Positive Slew Rate (SR+) >5 V/ns 3

ar stu

Negative Slew Rate (SR-) >5 V/ns 3

Common Mode Rejection Ratio (at 100Hz) > 80 dB 3
sh is

Positive Power Supply Rejection Ratio (at 100Hz) > 60 dB 3

Th

Negative Power Supply Rejection Ratio (at 100Hz) > 60 dB 3

Table 1: CMOS Operational Amplifier Performance and Priorities.

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 3. Phase I of the Project
a. Input common mode range of the project opamp is 1 V. The supply Vdd is 2V.

b. We design the Vdsat for each device to be 150mV.

c. To be in saturation, we have to have: Vds > Vdsat. Suppose. Vds=Vdsat+100mV.

This way we have a good margin of 100mV into the saturation regions.

d. If we have 4 Vds at the output, the maximum Vds is: Vds(Max) = 250mV=
Vdsat+100mV

e. We select to have 25uA as a unit reference current source. We select the channel
length (L) for the unit reference MOS device to be 0.5um. Therefore, for

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Vdsat=150mV, the aspect ratios for nMOS and pMOS devices are:

co
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W / L for nMOS = 2.5um / 0.5um
W / L for pMOS = 10um / 0.5um

o.
rs e
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f. Use Figure 1 to generate the four levels of bias voltages for your operational
amplifier. The total dc current consumption of the four-level low-voltage bias
generator is only 6 x 25uA = 150uA = 0.15mA. This is negligible in comparison
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to the total amplifier current consumption requirement that is 25mA.

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g. Because the open-loop gain of the opamp is 100dB, we have to have two-stage
operational amplifier. Usually each stage must give you about 40 to 60 dB gain.

h. The power consumption of the operational amplifier must be less that 50mW.
ed d

This means that the current consumption of the opamp is less than 25mA.
ar stu

Because of stability issues (will be covered in the class) the second stage of the
operational amplifier usually consumes twice as much current as the first stage of
the opamp.
sh is

Current consumption First stage = 5 to 10 mA

Th

Current consumption Second stage = 10 to 20 mA

4. Project Phase II Assignment

a. Use Table 2 values for all your hand analysis.

b. One or two people can work on the same project. If two people work in the
same project, they will both receive the same grade.

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 c. We want the CMOS operational amplifier to be compatible to P-Well, N-
Well, or twin-Well processes, all the pMOS body (substrate) terminals must
be connected to Vdd and all the nMOS body (substrate) terminals must be
connected to Vss (ground).

d. Use either Telescopic or Folded-Cascode topology to design the first stage of

your operational amplifier. Be sure that you use the current consumption
accordingly. Include the bias generator with your operational amplifier first
stage.

e. Use 1pF capacitor output load. Be sure that all your devices are in saturation
region. Include a table similar to the Table 3 in your report.

f. Plot open-loop frequency response. Show how much is your Open-loop DC

gain, Phase margin, and Unity Gain Bandwidth Frequency

m
er as
g. Plot common-mode input range plot with input and output signal using your

co
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first stage as a unity gain buffer configuartion.

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h. Show the PSRR+ and PSRR- plots
rs e
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.INCLUDE TSMC018.txt
.tran 0 10m 0
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Vdd Vdd
Vdd
aC s

Vdd C1
2pF
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SINE(2 0.2 1k 1u 1u)

Vdd
Vss

l=2u w=20u l=2u w=20u

PMOS PMOS
MP9 MP12
Vpcs
Vss l=2u w=20u
0V l=0.5u w=10u
PMOS MP5
ed d

MP8 PMOS

MP7 Vdd
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PMOS PMOS
l=2u w=20u MP6
l=2.5u w=10u
PMOS Vpcas
MP11
l=10u w=2u
sh is

MN7 Vncas
l=2u w=5u
NMOS MN4
l=1u w=5u
NMOS Vss
NMOS l=2.5u w=2.5u
Th

MN12

l=2u w=5u Vncs

l=2u w=5u
MN8 MN9 MN13
NMOS NMOS NMOS
l=2u w=5u m=4 MN6 Vss
NMOS
C2 l=0.5u w=2.5u
l=1u w=5u 2pF
NMOS Off-Chip (External)
MN11 Precision Resistor
Rext1
4.8k
Vss
Vss

Figure 1. Four-Level Low-Voltage Bias Generator

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 Process Parameters Symbols nMOS pMOS Units
Minimum Drawn Channel Length Lmin 0.2 0.2 mm

Intrinsic Carrier Concenteration ni 1.45E+10 1.45E+10 cm-3

Permitivity of Silicon eSi 1.045E-12 1.045E-12 F/cm

Permitivity of Oxide eOX 3.5E-13 3.5E-13 F/cm

Electron Charge q 1.6E-19 1.6E-19 C

Thermal Voltage (@ Room Temp) Vth 25.85 25.85 mV

Substrate Doping Concentration NA, ND 8E+16 8E+16 cm-3

Gate Oxide thickness Tox 42 42 AO
Channel Mobility µN, µP 300 80 cm2 / V-s
Drain or Source Junction Depth XJ 0.16 0.16 mm

Drain or Source Lateral Diffusion Ld 0.01 0.015 mm

Drain Depletion-Layer Width Xd 0.00 0.00 mm

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Overlap Capacitance per unit Gate Width Cov 0.36 0.33 fF/um

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Nominal Threshold Voltage Vtn0, Vtp0 0.5 0.45 V

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Channel Length Modulation Parameters | d Xd / dVds | 0.028 0.023 um / V

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2
Drain or Source-Body bottom-side junction Capacitance Cjb0 1.0 1.1 f F/ um

rs e
Drain or Source-Body bottom-side junction Capacitance Grading Coefficient mjb 0.36 0.45
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Drain or Source-Body side-wall junction Capacitance Cjsw0 0.2 0.25 f F/ um

Drain or Source-Body side-wall junction Capacitance Grading Coefficient mjsw 0.2 0.24

Drain or Source Junction Build-in potential y0 0.68 0.74 V

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Table 2: Hand-Calculation Parameters for 180nm TSMC CMOS Process.

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W L m Ids Gm Ro Vgs Vds Vdsat Vdsat-Margin

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Device Type (um) (um) (#) (uA) (uA/V) (KW) (mV) (mV) (mV) (mV)
M1 nMOS
M2 pMOS
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M3 nMOS
M4 nMOS
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M5 pMOS
M6 nMOS
M7 nMOS
M8 pMOS
M9 nMOS

Table 3: DC Bias and Operating condition of all transistors

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