Electronics II

ECEN332

MULTISTAGE AMPLIFIERS

Credit: Dr. Adnan Kabbani

Outline
 Introduction
 A Two‐Stage CMOS Op Amp
 Introduction
 Practical transistor amplifiers usually consist of a
number of stages connected in cascade
 The first stage is to provide
 gain
 a high input resistance (to avoid signal level loss)
 large common‐mode rejection (differential amplifier )
 The middle stage amplifiers are to provide
 voltage gain
 signal conversion from differential mode to single‐ended
mode (unless, of course, the amplifier output also is
differential)
 shifting of the dc level of the signal in order to allow the
output signal to swing both positive and negative
 The last (or output) stage is to provide
 a low output resistance in order to avoid loss of gain
 the current required by the load

A Two-Stage CMOS Op Amp

 The figure shows a
popular structure for
CMOS op amps known
as the two‐stage
configuration
 The circuit utilizes two
power supplies, which
can range from ±2.5 V to
±0.5 V
 A reference bias current
IREF is generated either
externally or on‐chip
 A Two-Stage CMOS Op Amp
 The current mirror formed by
Q8 and Q5 supplies the
differential pair Q1 −Q2 with
bias current
 The W/L ratio of Q5 is
selected to yield the desired
value for the input‐stage bias
current I (or I/2 for each of Q1
and Q2)
 Q3 and Q4 are the active loads
for the input differential stage
Q1 and Q2
 The second stage consists of
Q6, which is a common‐
source amplifier loaded with
the current‐source transistor
Q7

A Two-Stage CMOS Op Amp

 A capacitor CC is
included in the
negative‐feedback
path of the second
stage
 The major drawback
is that it does not
have a low‐output‐
resistance stage
 the output resistance
of the circuit is equal
to (ro6//ro7) which is
high
 A Two-Stage CMOS Op Amp
 Voltage Gain: The voltage
gain of the first stage can be
given by
A1=−gm1(ro2 // ro4)
 Where gm1 is the
transconductance of Q1 and
Q2
 The second stage is a
current‐source‐loaded,
common‐source amplifier
whose voltage gain is given
by
A2=−gm6(ro6 // ro7)

A Two-Stage CMOS Op Amp

 Example 9.6: for the circuit shown assume that

 Let
IREF = 90 μA, Vtn = 0.7 V,
Vtp = −0.8 V,
μnCox = 160 μA/V2,
μpCox = 40 μA/V2,
|VA| (for all devices) = 10 V,
VDD = VSS = 2.5 V.
 Find for all devices, ID,
|VOV|, |VGS|, gm, and ro

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A Two-Stage CMOS Op Amp

 Example 9.6 continued

 Find
 A1, A2,
 the dc open-loop voltage
gain
 the input common-mode
range
 the output voltage range
 Neglect the effect of VA on
bias current

A Two-Stage CMOS Op Amp

Solution
 Q8 and Q5 are matched, so I
=IREF
 Q1, Q2, Q3, and Q4 each
conducts a current equal to
I/2=45 μA
 Q7 is matched to Q5 and Q8, the
current in Q7 is equal to
IREF =90 μA
 Q6 conducts an equal current of
90 μA
 ID of each device is known use
1
ID   Cox W / L VOV
2
2

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A Two-Stage CMOS Op Amp

 To determine |VOV| for each
transistor.
 We find |VGS| from
|VGS|=|Vt|+ |VOV|
 The transconductance of
each device is determined
from
gm=2ID/|VOV|
 The value of ro is determined
from VA/ID
 The resulting values of gm
and ro are given the table

A Two-Stage CMOS Op Amp

 The voltage gain of the first stage is determined from

A1   g m1 ro 2 || ro 4   0.3222 || 222  33.3 V/V

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A Two-Stage CMOS Op Amp

 The voltage gain of the second stage is
determined from

A2   g m6 ro 6 || ro 7   0.6111 || 111  33.3 V/V

 Thus the overall dc open‐loop gain is

Ao  A1 A2   33.3   33.3  1109 V/V
20 log 1109  61 dB

A Two-Stage CMOS Op Amp

 The lower limit of the input
common‐mode range is the
value of input voltage at
which Q1 and Q2 leave the
saturation region
 This occurs when the input
voltage falls below the
voltage at the drain of Q1 by
|Vtp| volts
 Since the drain of Q1 is at
−2.5+1=−1.5 V, then the lower
limit of the input common‐
mode range is −2.3 V

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A Two-Stage CMOS Op Amp

 The upper limit of the input
common‐mode range is the
value of input voltage at which
Q5 leaves the saturation region
 For Q5 to operate in saturation
VSD5 should at least be equal to
the overdrive voltage at which it
is operating (i.e., 0.3 V), the
highest voltage permitted at the
drain of Q5 should be +2.2 V
 Thus the highest value of vICM
should be vICMmax = 2.2−1.1 = 1.1V

A Two-Stage CMOS Op Amp

 The highest allowable
output voltage is the value
at which Q7 leaves the
saturation region, which
is VDD −|VOV7| = 2.5−0.3 =
2.2 V
 The lowest allowable
output voltage is the value
at which Q6 leaves
saturation, which is −VSS +
VOV6 = −2.5 + 0.3 = −2.2 V
 Thus, the output voltage
range is −2.2 V to +2.2 V

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