Reg.

No. PSNA COLLEGE OF ENGINEERING AND TECHNOLOGY, DINDIGUL-624622

DEPARTMENT OF ECE
Series Test-I
Subject : LOW POWER VLSI DESIGN Max. Marks :50
Sub Code : VL5202 Year : I Sem: II Duration : 90 Min.
Staff : Dr.M.Revathy Date :
Course Outcome Covered Part A Part B Part C

CO.1 To identify sources of power in an 1,2,3,4,5,6,7 10(a), 10(b), 12(a)

IC. 11(a)
CO.2 To identify the power reduction 8,9 11(b) 12(b)
techniques based on technology
independent and technology
dependent.

PART – A (Answer all) (9 x 2 = 18)

1. What is body effect?
2. Realise a full adder using half adders.
3. Give the need for low power VLSI chips.
4. Comment on the impact of scaling devices in low power design.
5. Name some multiple Vth techniques.
6. What are the sources of power consumption?
7. Realise a XOR gate using pass transistor logic.
8. What does architecture level power estimation approach require?
9. Mention the different types of adders used in low power design.

PART- B (Answer all) (2 x 10= 20)

10. (a) Describe the sources of static and dynamic power dissipation in CMOS circuits. (10)
(OR)
(b) Elaborate the Circuit techniques for leakage power reduction. (10)

11. (a) Discuss the basic principles behind low power VLSI design . (10)
(OR)
(b) Explain the various logic level power optimization techniques for low power design. (10)

PART- C (Answer all) (1 x 12= 12)

12. (a) With the help of energy band diagram analyze the physics of power dissipation in MOSFETs
by deriving expression for space charge region and threshold voltage. (12)
(OR)
12. (b) Explain the various CMOS Adders architectures. (12)

Faculty HOD-ECE