A B C D E

1 1

Compal Confidential
2 2

IAKAA LA-3401P Schematics Document

Intel Yonah/Merom with 945PM/GM + DDRII + ICH7M
(+VGA/B NVidia NB7P-GS&NB7M-SE)

3 2006-10-03 3

REV: 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 1 of 38
A B C D E
 A B C D E

Compal confidential
Model : IAKAA Fan Control
page 4
Yonah/Merom Thermal Sensor Clock Generator
File Name : LA-3401P uFCPGA-479 CPU ICS9LPRS325AKLFT
ADM1032ARM
NAPA Platform page 4,5,6 page 4 page 14
1 1
H_A#(3..31)
FSB
H_D#(0..63)
LCD Conn. CRT & TV-out 533/667MHz
page 16 page 15

Intel Calistoga GMCH DDR2-533/667 DDR2-SO-DIMM X2

BANK 0, 1, 2, 3 page 12, 13

NVIDIA NB7P-GS 945PM/GM

NB7M-SE Dual Channel
VGA/B Conn. PCBGA 1466
page 7,8,9,10,11
with 64/128/256/512 page 16 PCI-Express
MB VRAM x16
PCI-E BUS 2.5GHz USB1.1 USB x 1 USB/B conn USB2.0
Finger Printer
page 29
connpage 28 page 25
Bluetooth Conn
page 31
DMI x 4
(port 3) (port 2)

2 USB 3.3V 48MHz USB port 6 USB port 1, 4 USB port 0, 2 USB port 5 2
Mini Express Card USB 3.3V 480MHz
10/100/1000 LAN
RTL8111B/RTL8101E page 25 USB port 7
3.3V 33 MHz Azalia
page 22 PCI BUS 3.3V 24.576MHz/48Mhz
MDC1.5
page 25
Intel ICH7-M SATA 1.5GHz
RJ45/11 CONN mBGA-652 Audio Codec AMP & Audio Jack & Int-MIC
page 22 CardBus Controller PATA 3.3V ATA-100 ALC861 VD SPK/JP-AMP: APA2056
page 23
page 17,18,19 page 24
TI PCI7412
page 20,21

SATA HDD Connector

SATA 0
page 17

LED Slot 0 1394 port 5in1 Slot

page 21 page 20 page 20
page 28
3 LPC BUS SATA HDD Connector 3

3.3V 33 MHz SATA 1

page 17
RTC CKT.
page 17
PATA Master
PATA ODD Connector IAKAA Sub-board
page 17
Power On/Off CKT. Finger Print /B
page 29
ENE KB910QF LS-3401P Rev0

DC/DC Interface CKT. page 26 SW/B

page 30 LS-3392P Rev0

Power Circuit DC/DC VGA/B

Page 30~36 LS-3403P Rev0
Touch Pad Int.KBD BIOS CIR
page 23 page 28 page 27 page 25
4 USB/B 4

LS-3391P Rev0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 2 of 38
A B C D E
 A B C D E

Voltage Rails Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%
Power Plane Description S1 S3 S5 Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
0 0 0 V 0 V 0 V
1
+CPU_CORE Core voltage for CPU ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1

+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VCCP 1.05V switched power rail ON OFF OFF
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+1.5VS 1.5V switched power rail ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+1.8V 1.8V power rail for DDR ON ON OFF
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+1.8VS 1.8V switched power rail ON OFF OFF
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+2.5VS 2.5V switched power rail ON OFF OFF
7 NC 2.500 V 3.300 V 3.300 V
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF Board ID PCB Revision BTO Item BOM Structure
+VSB +VSB always on power rail ON ON ON* 0 0.1 2ND HDD 2HDD@
+RTCVCC RTC power ON ON ON 1 0.2 100M@
LAN 1000M@
2 0.3
WLAN KS@
3
GM@
4 NB PM@
2 2
5 BT BT@
6 MIC MIC@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
7 CIR CIR@
FINGER PRINT
External PCI Devices SKU ID Table 5IN1 7412@
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
SKU ID SKU
1394 D0 AD20 2 A,B,C,D 0 10 (10E)
CARD BUS D4 AD20 2 A,B,C,D 1 10C
5IN1 D4 AD20 2 A,B,C,D 2 10G
3 10GC
4 10J (10EJ)
5 10CJ
6 10GJ
KB910 I2C / SMBUS ADDRESSING 7 10GCJ
DEVICE HEX ADDRESS
3 3

SM1 24C16 A0H 1010000Xb

SM1 SMART BATTERY 16H 0001011Xb
SM2 ADM0132 98H 1001100Xb
CPU THERMAL MONITOR

ICH7-M SM Bus address

DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 3 of 38
A B C D E
 5 4 3 2 1

Place close to CPU within 500mil

+VCCP
7 H_A#[3..31] H_D#[0..63] 7
JP18A

H_A#3 J4 E22 H_D#0 XDP_TDI R56 1 2 56_0402_5%

H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 XDP_TMS R55 56_0402_5%
M3 A5# D2# E26 1 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 XDP_TDO R54
M1 F23 1 2 @ 56_0402_5%
H_A#8
H_A#9
N2
J1
A7#
A8#
D4#
D5# G25
E25
H_D#5
H_D#6
Thermal Sensor ADM1032ARM XDP_BPM#5 R53 1 2 56_0402_5%
D H_A#10 A9# D6# H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8 +3VS XDP_TRST# R57 1 2 56_0402_5%
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 XDP_TCK R47 1 2 56_0402_5%
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26 1

1
H_A#17 Y2 K22 H_D#14
H_A#18 A17# D14# H_D#15 C209 R113
U5 A18# D15# H25
H_A#19 R3 N22 H_D#16 0.1U_0402_16V4Z @ 10K_0402_5%
H_A#20 A19# D16# H_D#17 2
W6 A20# D17# K25 1
H_A#21 U4 P26 H_D#18 C212

2
H_A#22 A21# D18# H_D#19 U8
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20 2200P_0402_50V7K H_THERMDA 2 1
H_A#24 A23# D20# H_D#21 2 D+ VDD1
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 H_THERMDC 3 6
H_A#26 A25# D22# H_D#23 D- ALERT#
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24 8 4
A27# D24# 16,26 EC_SMB_CK2 SCLK THERM#
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23 16,26 EC_SMB_DA2 7 SDATA GND 5
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
7 H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29 ADM1032ARM_RM8
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32 +5VS
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35
H_ADSTB#0 D35# H_D#36
7 H_ADSTB#0 L2 ADSTB0# D36# W25

1SS355_SOD323
H_ADSTB#1 V4 U23 H_D#37 PU5B LM358DT_SO8
7 H_ADSTB#1 ADSTB1# D37#

1
U25 H_D#38 26 EN_DFAN1 5 + P@ R674 C

P
D38#

1
C H_D#39 FAN1_ON 2 Q40 C
D39# U22 0 7 1 2
AB25 H_D#40 1 2 6 B D36
D40# -

G
W22 H_D#41 R594 10K_0402_5% 100_0402_5% 1 2 E FMMT619_SOT23

3
D41# H_D#42
Y23

4
CLK_CPU_BCLK A22 D42# H_D#43 C820 0.1U_0402_16V4Z
14 CLK_CPU_BCLK AA26

2
CLK_CPU_BCLK# A21 BCLK0 D43# H_D#44
14 CLK_CPU_BCLK# BCLK1 HOST CLK D44# Y26
Y22 H_D#45 1 2 +FAN1_VOUT
D45# H_D#46 R431 8.2K_0402_5%
D46# AC26

1N4148_SOT23
AA24 H_D#47
H_ADS# D47# H_D#48 D37
7 H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49
7 H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
7 H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51 JP4
7 H_BR0#

2
H_DEFER# BR0# D51# H_D#52
7 H_DEFER# H5 DEFER# D52# AB21 1
H_DRD Y# F21 AC25 H_D#53
7 H_DRDY# DRDY# D53# 2
R94 H_HIT# G6 AD20 H_D#54
7 H_HIT# HIT# D54# 3
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55 +3VS 1 2
7 H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56 R432 10K_0402_5% ACES_85205-0300
+VCCP H_LOCK# IERR# D56# H_D#57
7 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 1
7 H_RESET# RESET# D58# 26 FAN_SPEED1
AD21 H_D#59 1
D59# H_D#60 C597
7 H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61 C598 @1000P_0402_50V7K
H_RS#1 RS0# D61# H_D#62 @1000P_0402_50V7K 2
F4 RS1# D62# AF22
H_RS#2 H_D#63 2
G3 RS2# D63# AF26
H_TRDY# G2
7 H_TRDY# TRDY#
J26 H_DINV#0
DINV0# H_DINV#0 7
M26 H_DINV#1
DINV1# H_DINV#1 7
AD4 V23 H_DINV#2
BPM0# DINV2# H_DINV#2 7
AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 7
AD1 BPM2#
B B
AC4 BPM3# H_DSTBN#[0..3] 7
H23 H_DSTBN#0
DBRESET# DSTBN0# H_DSTBN#1
18 DBRESET# C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
7 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
17 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 7
H_DPRSTP# E5 G22 H_DSTBP#0 Placement near to ICH7
17,36 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
7 H_DPWR# DPWR# DSTBP1#
AC2 MISC Y25 H_DSTBP#2 H_FERR# 2 1
R95 XDP_BPM#5 AC1 PRDY# DSTBP2# H_DSTBP#3 C211 @ 180P_0402_50V8J
PREQ# DSTBP3# AE24
1 2 H_PROCHOT# D21
+VCCP 56_0402_5% PROCHOT#
17 H_PWRGOOD H_PW RGOOD D6
H_CPUSLP# PWRGOOD
7 H_CPUSLP# D7 SLP#
XDP_TCK AC5
XDP_TDI TCK H_A20M# H_SMI#
AA6 TDI A20M# A6 H_A20M# 17 2 1
XDP_TDO AB3 A5 H_FERR# C202 @ 180P_0402_50V8J
TDO FERR# H_FERR# 17
R85 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# H_INIT# 2 1
TEST1 IGNNE# H_IGNNE# 17
R84 1 2 51_0402_5% TEST2 D25 B3 H_INIT# C162 @ 180P_0402_50V8J
TEST2 INIT# H_INIT# 17
XDP_TMS AB5 C6 H_INTR H_NMI 2 1
TMS LINT0 H_INTR 17
XDP_TRST# AB6 B4 H_NMI C203 @ 180P_0402_50V8J
TRST# LINT1 H_NMI 17
LEGACY CPU H_A20M# 2 1
THERMAL C210 @ 180P_0402_50V8J
H_THERMDA A24 D5 H_STPCLK# H_INTR 2 1
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# 17
C173 @ 180P_0402_50V8J
A25 THERMDC SMI# A3 H_SMI# 17
H_THERMTRIP# C7 H_IGNNE# 2 1
7,17 H_THERMTRIP# THERMTRIP# C161 @ 180P_0402_50V8J
H_THERMDA, H_THERMDC routing together. H_STPCLK# 2 1
FOX_PZ47903-2741-42_YONAH C172 @ 180P_0402_50V8J
Trace width / Spacing = 10 / 10 mil H_PW RGOOD 2 1
C171 @ 180P_0402_50V8J
H_CPUSLP# 2 1
C169 @ 180P_0402_50V8J
A +VCCP A

+VCCP
Placement near to CPU side
1

R98
R89 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R97 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2006/10/03 2009/10/03 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# 18
C

Q12 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 4 of 38
5 4 3 2 1
 5 4 3 2 1

+VCCP +CPU_CORE
Length match within 25 mils JP18B JP18C
D D
The trace width 18 mils space

1
36 VCCSENSE VCCSENSE AF7 AB26 AE18 K1
VCCSENSE VSS VCC VSS
+CPU_CORE 7 mils 36 VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R67 R52 AD25 AB15 M2
+V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R51 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C164

C163
N6 AD22 AA13 D26
R58
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22

POWER, GROUNG, RESERVED SIGNALS AND NC

W21 VCCP VSS AA16 AE12 VCC VSS E21
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
36 H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
36 CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
36 CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
36 CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
36 CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C 36 CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
36 CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
36 CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
+V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
14 CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
1 14 CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
14 CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R68

R65
R324

R325

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 5 of 38
5 4 3 2 1
 5 4 3 2 1

D +CPU_CORE D

1 1 1 1 1 1 1 1
C533 C135 C136 C137 C138 C139 C140 C152

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
C146 C147 C544 C148 C149 C150 C151 C206

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
C207 C205 C204 C543 C546 C545 C125 C124

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2

C C
+CPU_CORE

1 1 1 1 1 1 1 1
C127 C529 C528 C548 C547 C532 C531 C530

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M Mid Frequence Decoupling
2 2 2 2 2 2 2 2
10uF X32 PCS

+CPU_CORE

@ 330U_D_2VM 330U_D_2VM @ 330U_D_2VM

South Side Secondary North Side Secondary

1 1 1 1 1 1 ESR <= 1.5m ohm
C550 + C121 + C122 + C537 + C536 + C208 +
Capacitor > 1980uF
330U_D_2VM
2 2 2 2 2 2
B B

330U_D_2VM 330U_D_2VM
330uF ESR 7m ohm X 6 PCS

+VCCP

1
330U_D2E_2.5VM_R9

1 1 1 1 1 1 Place these inside socket

C134 + C539 C534 C540 C535 C541 C538 cavity on Bottom layer (North
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
side Secondary)
2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 6 of 38
5 4 3 2 1
 5 4 3 2 1

U6B
4 H_D#[0..63] H_A#[3..31] 4
U6A 18 DMI_TXP3 DMI_TXP3 AE35 K16 MCH_CLKSEL0
DMIRXN0 CFG0 MCH_CLKSEL0 14
H_D#0 F1 H9 H_A#3 18 DMI_TXP2 DMI_TXP2 AF39 K18 MCH_CLKSEL1
HD0# HA3# DMIRXN1 CFG1 MCH_CLKSEL1 14
H_D#1 J1 C9 H_A#4 18 DMI_TXP1 DMI_TXP1 AG35 J18 MCH_CLKSEL2
HD1# HA4# DMIRXN2 CFG2 MCH_CLKSEL2 14
H_D#2 H1 E11 H_A#5 18 DMI_TXP0 DMI_TXP0 AH39 F18
H_D#3 HD2# HA5# H_A#6 DMIRXN3 CFG3
J6 HD3# HA6# G11 CFG4 E15
H_D#4 H3 F11 H_A#7 F15 CFG5
H_D#5 HD4# HA7# H_A#8 DMI_TXN3 CFG5
K2 HD5# HA8# G12 18 DMI_TXN3 AC35 DMIRXP0 CFG6 E18
H_D#6 G1 F9 H_A#9 18 DMI_TXN2 DMI_TXN2 AE39 D19 CFG7
H_D#7 HD6# HA9# H_A#10 DMI_TXN1 DMIRXP1 CFG7
G2 HD7# HA10# H11 18 DMI_TXN1 AF35 DMIRXP2 CFG8 D16

DMI
H_D#8 K9 J12 H_A#11 18 DMI_TXN0 DMI_TXN0 AG39 G16 CFG9
H_D#9 HD8# HA11# H_A#12 DMIRXP3 CFG9
K1 HD9# HA12# G14 Lane Reversal CFG10 E16
H_D#10 K7 D9 H_A#13 D15 CFG11

D
H_D#11 J8
HD10#
HD11#
HA13#
HA14# J14 H_A#14 Polarity Reversal 18 DMI_RXP3 DMI_RXP3 AE37 DMITXN0
CFG11
CFG12 G15 CFG12 Refer Strap D
H_D#12 H4 H13 H_A#15 18 DMI_RXP2 DMI_RXP2 AF41 K15 CFG13
HD12# HA15# DMITXN1 CFG13
Pin Table

CFG
H_D#13 J3 J15 H_A#16 18 DMI_RXP1 DMI_RXP1 AG37 C15
H_D#14 HD13# HA16# H_A#17 DMI_RXP0 DMITXN2 CFG14
K11 HD14# HA17# F14 18 DMI_RXP0 AH41 DMITXN3 CFG15 H16
H_D#15 G4 D12 H_A#18 G18 CFG16
H_D#16 HD15# HA18# H_A#19 CFG16
T10 HD16# HA19# A11 CFG17 H15
H_D#17 W11 C11 H_A#20 18 DMI_RXN3 DMI_RXN3 AC37 J25 CFG18
H_D#18 HD17# HA20# H_A#21 DMI_RXN2 DMITXP0 CFG18 CFG19
T3 HD18# HA21# A12 18 DMI_RXN2 AE41 DMITXP1 CFG19 K27
H_D#19 U7 A13 H_A#22 18 DMI_RXN1 DMI_RXN1 AF37 J26 CFG20
H_D#20 HD19# HA22# H_A#23 DMI_RXN0 DMITXP2 CFG20
U9 HD20# HA23# E13 18 DMI_RXN0 AG41 DMITXP3
H_D#21 U11 G13 H_A#24
H_D#22 HD21# HA24# H_A#25
T11 HD22# HA25# F12 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL 14
H_D#23 W9 B12 H_A#26 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD23# HA26# 12 M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# 14
H_D#24 T1 B14 H_A#27 M_CLK_DDR1 AR1
HD24# HA27# 12 M_CLK_DDR1 SM_CK1
H_D#25 T8 C12 H_A#28 M_CLK_DDR2 AW7 A27

CLK
HD25# HA28# 13 M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# 14
H_D#26 T4 A14 H_A#29 M_CLK_DDR3 AW40 A26
HD26# HA29# 13 M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK 14
H_D#27 W7 C14 H_A#30
H_D#28 HD27# HA30# H_A#31 M_CLK_DDR#0
U5 HD28# HA31# D14 12 M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 CLK_PCIE_GMCH# 14
H_D#29 T9 M_CLK_DDR#1 AT1 D41
HD29# 12 M_CLK_DDR#1 SM_CK1# D_REF_SSCLKP CLK_PCIE_GMCH 14
H_D#30 W6 M_CLK_DDR#2 AY7
HD30# 13 M_CLK_DDR#2 SM_CK2#
H_D#31 T5 M_CLK_DDR#3 AY40 H32 MCH_CLKREQ#

HOST
HD31# H_REQ#[0..4] 4 13 M_CLK_DDR#3 SM_CK3# CLK_REQ# MCH_CLKREQ# 14
H_D#32 AB7 D8 H_REQ#0
H_D#33 HD32# HREQ#0 H_REQ#1 DDR_CKE0_DIMMA
AA9 HD33# HREQ#1 G8 12 DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#34 W4 B8 H_REQ#2 DDR_CKE1_DIMMA AT20
HD34# HREQ#2 12 DDR_CKE1_DIMMA SM_CKE1
H_D#35 W3 F8 H_REQ#3 DDR_CKE2_DIMMB BA29 A3
HD35# HREQ#3 13 DDR_CKE2_DIMMB SM_CKE2 NC0
H_D#36 Y3 A8 H_REQ#4 DDR_CKE3_DIMMB AY29 A39
HD36# HREQ#4 13 DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#37 Y7 A4
H_D#38 HD37# DDR_CS0_DIMMA# AW13 NC2 +3VS
W5 HD38# 12 DDR_CS0_DIMMA# SM_CS0# NC3 A40
H_D#39 Y10 B9 H_ADSTB#0 DDR_CS1_DIMMA# AW12 AW1 R292
HD39# HADSTB#0 H_ADSTB#0 4 12 DDR_CS1_DIMMA# SM_CS1# NC4
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS2_DIMMB# AY21 AW41 1 2 PM_EXTTS#0
HD40# HADSTB#1 H_ADSTB#1 4 13 DDR_CS2_DIMMB# SM_CS2# NC5
H_D#41 W2 DDR_CS3_DIMMB# AW21 AY1 10K_0402_5%
HD41# 13 DDR_CS3_DIMMB# SM_CS3# NC6
H_D#42 AA4 AG1 CLK_MCH_BCLK# BA1 R288

NC
HD42# HCLKN CLK_MCH_BCLK# 14 NC7
H_D#43 AA7 AG2 CLK_MCH_BCLK AL20 BA2 1 2 PM_EXTTS#1
C HD43# HCLKP CLK_MCH_BCLK 14 SM_OCDCOMP0 NC8 C
H_D#44 AA2 AF10 BA3 10K_0402_5% @
HD44# H_DSTBN#[0..3] 4 SM_OCDCOMP1 NC9
H_D#45 AA6 K4 H_DSTBN#0 BA39
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_ODT0 NC10
AA10 HD46# HDSTBN#1 T7 12 M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#47 H_DSTBN#2 +1.8V M_ODT1
Y8 HD47# HDSTBN#2 Y5 12 M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#48 AA1 AC4 H_DSTBN#3 M_ODT2 AY20 C1
HD48# HDSTBN#3 H_DSTBP#[0..3] 4 13 M_ODT2 SM_ODT2 NC13
H_D#49 AB4 K3 H_DSTBP#0 M_ODT3 AU21 AY41
HD49# HDSTBP#0 13 M_ODT3 SM_ODT3 NC14
H_XSCOMP/H_YSCOMP trace H_D#50 AC9 T6 H_DSTBP#1 B2
L width and spacing is 5/20. H_D#51 AB11
HD50#
HD51#
HDSTBP#1
HDSTBP#2 AA5 H_DSTBP#2 R319 1 2 80.6_0402_1% SMRCOMPN AV9 SM_RCOMPN
NC15
NC16 B41
H_D#52 AC11 AC5 H_DSTBP#3 1 2 SMRCOMPP AT9 C41
H_D#53 HD52# HDSTBP#3 R318 80.6_0402_1% SM_RCOMPP NC17
AB3 HD53# NC18 D1
+VCCP H_D#54 AC2 +SM_VREF0 AK1
HD54# +SM_VREF0 SM_VREF0
H_D#55 AD1 J7 H_DINV#0 +SM_VREF1 AK41
HD55# HDINV#0 H_DINV#0 4 SM_VREF1
H_D#56 AD9 W8 H_DINV#1 T32
HD56# HDINV#1 H_DINV#1 4 RESERVED1
H_D#57 AC1 U3 H_DINV#2 R32
HD57# HDINV#2 H_DINV#2 4 RESERVED2
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 18 PM_BMBUSY# PM_BMBUSY# G28 F3

HD58# HDINV#3 H_DINV#3 4 PM_BMBUSY# RESERVED3
1

H_D#59 AC6 12,13 DDR_TS R28 1 2 0_0402_5% PM_EXTTS#0 F25 F7

HD59# PM_EXTTS0# RESERVED4
R59

R63

RESERVED
PM
H_D#60 AB5 18,36 DPRSLPVR R287 1 2 0_0402_5% PM_EXTTS#1 H26 AG11
H_D#61 HD60# H_RESET# H_THERMTRIP# PM_EXTTS1# RESERVED5
AD10 HD61# HCPURST# B7 H_RESET# 4 4,17 H_THERMTRIP# G6 PM_THERMTRIP# RESERVED6 AF11
H_D#62 AD4 E8 H_ADS# 18,26 PWROK PWROK AH33 H7
HD62# HADS# H_ADS# 4 PWROK RESERVED7
H_D#63 AC8 E7 H_TRDY# 2 1 PLTRST_R# AH34 J19
H_TRDY# 4 16,18,22,25 PLT_RST#
2

HD63# HTRDY# H_DPWR# R9 100_0402_1% RSTIN# RESERVED8

HDPWR# J9 H_DPWR# 4 RESERVED9 A41
H8 H_DRD Y# 18 MCH_ICH_SYNC# K28 A34
HDRDY# H_DRDY# 4 ICH_SYNC# RESERVED10
J13 C3 H_DEFER# D28
HVREF0 HDEFER# H_DEFER# 4 RESERVED11
H_VREF K13 D4 H_HITM# D27
HVREF1 HHITM# H_HITM# 4 RESERVED12
H_XRCOMP E1 D3 H_HIT# A35
HXRCOMP HHIT# H_HIT# 4 RESERVED13
H_XSCOMP E2 B3 H_LOCK#
HXSCOMP HLOCK# H_LOCK# 4
H_YRCOMP Y1 C7 H_BR0# CALISTOGA_FCBGA1466~D PMR3@
HYRCOMP HBREQ0# H_BR0# 4
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# 4
H_SWNG0 H_BPRI#
H_SWNG1 W1
E4 HXSWING
HYSWING
HBPRI#
HDBSY#
F6
A7 H_DBSY#
H_CPUSLP#
H_BPRI# 4
H_DBSY# 4 Layout Note: Strap Pin Table CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
HCPUSLP# E3 H_CPUSLP# 4 +SM_VREF0 & +SM_VREF1
24.9_0402_1%

24.9_0402_1%

011 = 667MT/s FSB

1

B trace width and CFG[2:0] 001 = 533MT/s FSB B

+1.8V
R64

R60

B4 H_RS#0 spacing is 20/20.

HRS0# H_RS#1
HRS1# E6 0 = DMI x 2
H_RS#2 2.2K_0402_5% @ 2 R311 CFG5 CFG5
HRS2# D6 1 *1 = DMI x 4 (Default)

1
H_RS#[0..2] 4
2

R425 0 = Reserved
CALISTOGA_FCBGA1466~D 2.2K_0402_5% @ 2 R306 CFG7 CFG7
+SM_VREF1 1K_0402_1%
1 *1 = Mobile Yonah CPU (Default)
PMR3@ 0 = Lane Reversal Enable

2
2.2K_0402_5% @ 2 R309 CFG9 CFG9
1 *1 = Normal Operation (Default)
0.1U_0402_16V4Z

15mils

1
Layout Note: 1 R426 2.2K_0402_5% @ 2 1 R312 CFG11 0 = Reserved
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / CFG11 *1 = Calistoga (Default)
C595

1K_0402_1%
H_SWNG1 trace width and spacing is 18/20. 00 = Reserved
2

2 2.2K_0402_5% @ 2 R316 CFG12

1 CFG[13:12] 01 = XOR Mode Enabled
+VCCP +VCCP
10 = All Z Mode Enabled
2.2K_0402_5% @ 2 R315 CFG13
1 *11 = Normal Operation (Default)
+VCCP +1.8V
0 = Dynamic ODT Disabled
221_0603_1%

221_0603_1%

2.2K_0402_5% @ 2 R310 CFG16 CFG16

1 *1 = Dynamic ODT Enabled (Default)
1

+3VS
100_0402_1%
1

1
R321

R69

*01 == 1.5V
1.05V (Default)
R313

R62 1K_0402_5% @ 2 1 R294 CFG18 CFG18

+SM_VREF0 1K_0402_1% 0 = Normal Operation (Default)
2

H_SWNG0 H_SWNG1 1K_0402_5% R291 CFG19 CFG19

2 1 *1 = DMI Lane Reversal Enable
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

15mils Modified *0 = (Default)

No SDVO Device Present
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1 SDVO_CTRLDATA
1

200_0402_1%

R320

R66

1 1 R61
R314

C503

C514

C128

A A
1 = SDVO Device Present
C129

1K_0402_1%
2 2
*0 = Only PCIE or SDVO is
2

2 2
CFG20 (Default)
2

1K_0402_5% @ 2 1 R290 CFG20 operational.

(PCIE/SDVO select) 1 = PCIE/SDVO are operating simu.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 7 of 38
5 4 3 2 1
 5 4 3 2 1

D D

U6D U6E
DDR_A_D[0..63] 12 DDR_B_D[0..63] 13
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
12 DDR_A_BS#0 SA_BS0 SA_DQ0 13 DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
12 DDR_A_BS#1 SA_BS1 SA_DQ1 13 DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
12 DDR_A_BS#2 SA_BS2 SA_DQ2 13 DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
12 DDR_A_DM[0..7] AK35 DDR_A_D5 13 DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
12 DDR_A_DQS[0..7] AL27 DDR_A_D17 13 DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
12 DDR_A_DQS#[0..7] AN20 DDR_A_D27 13 DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
12 DDR_A_MA[0..13] SA_DQ38 AL14 13 DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
12 DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 13 DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
12 DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 13 DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
12 DDR_A_WE# SA_WE# SA_DQ58 13 DDR_B_WE# SB_WE# SB_DQ58
AK23 AF6 DDR_A_D59 AK16 AK3 DDR_B_D59
SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENIN# SB_DQ59 DDR_B_D60
AK24 SA_RCVENOUT# SA_DQ60 AG9 AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
PMR3@
PMR3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 8 of 38
5 4 3 2 1
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
16 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
16 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
16 PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
D 16 PCIE_GTX_C_MRX_P[0..15] D

+3VS

R293 2.2K_0402_5% GMCH_LCD_CLK L PEGCOMP trace width

2 1 +1.5VS_PCIE
GM@ and spacing is 18/25 mils. R280
R295 2 1 2.2K_0402_5% GMCH_LCD_DATA U6C 24.9_0402_1%
GM@ H27 D40 PEGCOMP 1 2
R296 1 2.2K_0402_5% GMCH_CRT_CLK SDVOCTRL_DATA EXP_COMPI
2 H28 SDVOCTRL_CLK EXP_COMPO D38

R297 1 2 2.2K_0402_5% GMCH_CRT_DATA F34 PCIE_GTX_C_MRX_N0

GMCH_TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1
16 GMCH_TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38
R283 1 2 10K_0402_5% LCTLB_DATA GMCH_TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
16 GMCH_TXOUT1+ LA_DATA1 EXP_RXN2
@ GMCH_TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3
16 GMCH_TXOUT2+ LA_DATA2 EXP_RXN3
R284 1 2 10K_0402_5% LCTLA_CLK L34 PCIE_GTX_C_MRX_N4
@ GMCH_TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5
16 GMCH_TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38
GMCH_TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6
16 GMCH_TXOUT1- LA_DATA#1 EXP_RXN6
GMCH_TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7
16 GMCH_TXOUT2- LA_DATA#2 EXP_RXN7
R34 PCIE_GTX_C_MRX_N8
EXP_RXN8 PCIE_GTX_C_MRX_N9
F30 LB_DATA0 EXP_RXN9 T38
PCIE_GTX_C_MRX_N10

LVDS
D29 LB_DATA1 EXP_RXN10 V34
F28 W38 PCIE_GTX_C_MRX_N11
LB_DATA2 EXP_RXN11 PCIE_GTX_C_MRX_N12
EXP_RXN12 Y34
G30 AA38 PCIE_GTX_C_MRX_N13
LB_DATA#0 EXP_RXN13 PCIE_GTX_C_MRX_N14
D30 LB_DATA#1 EXP_RXN14 AB34
F29 AC38 PCIE_GTX_C_MRX_N15
R282 1 1.5K_0402_1% LIBG LB_DATA#2 EXP_RXN15
2
GMCH_TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
C 16 GMCH_TXCLK+ LA_CLK EXP_RXP0 C
R44 1 2 75_0402_1% GMCH_TV_COMPS GMCH_TXCLK- A33 F38 PCIE_GTX_C_MRX_P1
16 GMCH_TXCLK- LA_CLK# EXP_RXP1
E26 G34 PCIE_GTX_C_MRX_P2
R41 150_0402_1% GMCH_TV_LUMA LB_CLK EXP_RXP2 PCIE_GTX_C_MRX_P3
1 2 E27 LB_CLK# EXP_RXP3 H38
J34 PCIE_GTX_C_MRX_P4

PCI-EXPRESS GRAPHICS
R37 150_0402_1% GMCH_TV_CRMA EXP_RXP4 PCIE_GTX_C_MRX_P5
1 2 D32 LBKLT_CTL EXP_RXP5 L38
26 GMCH_ENBKL GMCH_ENBKL J30 M34 PCIE_GTX_C_MRX_P6
LCTLA_CLK LBKLT_EN EXP_RXP6 PCIE_GTX_C_MRX_P7
H30 LCTLA_CLK EXP_RXP7 N38
LCTLB_DATA H29 P34 PCIE_GTX_C_MRX_P8
GMCH_LCD_CLK LCTLB_DATA EXP_RXP8 PCIE_GTX_C_MRX_P9
16 GMCH_LCD_CLK G26 LDDC_CLK EXP_RXP9 R38
GMCH_LCD_DATA G25 T34 PCIE_GTX_C_MRX_P10
16 GMCH_LCD_DATA LDDC_DATA EXP_RXP10
GMCH_ENVDD F32 V38 PCIE_GTX_C_MRX_P11
16 GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCIE_GTX_C_MRX_P12
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38

F36 PCIE_MTX_GRX_N0 C449 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0

GMCH_TV_COMPS EXP_TXN0 PCIE_MTX_GRX_N1 C433 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
A16 TVDAC_A EXP_TXN1 G40
GMCH_TV_LUMA C18 H36 PCIE_MTX_GRX_N2 C447 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
15 GMCH_TV_LUMA TVDAC_B EXP_TXN2
GMCH_TV_CRMA A19 J40 PCIE_MTX_GRX_N3 C431 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
15 GMCH_TV_CRMA TVDAC_C EXP_TXN3

TV
L36 PCIE_MTX_GRX_N4 C445 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
TV_REFSET EXP_TXN4 PCIE_MTX_GRX_N5 C429 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
2 1 J20 TV_IREF EXP_TXN5 M40
R308 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 C443 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
EXP_TXN6 PCIE_MTX_GRX_N7 C427 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
B16 TV_IRTNA EXP_TXN7 P40
B18 R36 PCIE_MTX_GRX_N8 C441 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 C425 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
B19 TV_IRTNC EXP_TXN9 T40
V36 PCIE_MTX_GRX_N10 C439 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
EXP_TXN10 PCIE_MTX_GRX_N11 C423 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 Y36 PCIE_MTX_GRX_N12 C437 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 C421 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
EXP_TXN13 AA40
AB36 PCIE_MTX_GRX_N14 C435 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
EXP_TXN14 PCIE_MTX_GRX_N15 C419 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
EXP_TXN15 AC40
B GMCH_CRT_CLK B
15 GMCH_CRT_CLK C26 DDCCLK

CRT
GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0 C450 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
15 GMCH_CRT_DATA DDCDATA EXP_TXP0
F40 PCIE_MTX_GRX_P1 C434 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
EXP_TXP1 PCIE_MTX_GRX_P2 C448 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
15 GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36
G23 H40 PCIE_MTX_GRX_P3 C432 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
15 GMCH_CRT_HSYNC HSYNC EXP_TXP3
E23 J36 PCIE_MTX_GRX_P4 C446 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
15 GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 PCIE_MTX_GRX_P5 C430 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R299 150_0402_1% BLUE# EXP_TXP5 PCIE_MTX_GRX_P6 C444 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
15 GMCH_CRT_G C22 GREEN EXP_TXP6 M36
2 1 B22 N40 PCIE_MTX_GRX_P7 C428 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
R302 150_0402_1% GREEN# EXP_TXP7 PCIE_MTX_GRX_P8 C442 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
15 GMCH_CRT_R A21 RED EXP_TXP8 P36
2 1 B21 R40 PCIE_MTX_GRX_P9 C426 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
R36 150_0402_1% RED# EXP_TXP9 PCIE_MTX_GRX_P10 C440 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
EXP_TXP10 T36
V40 PCIE_MTX_GRX_P11 C424 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
EXP_TXP11 PCIE_MTX_GRX_P12 C438 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
1 2 J22 CRT_IREF EXP_TXP12 W36
R298 255_0402_1% Y40 PCIE_MTX_GRX_P13 C422 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
EXP_TXP13 PCIE_MTX_GRX_P14 C436 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
EXP_TXP14 AA36
AB40 PCIE_MTX_GRX_P15 C420 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
EXP_TXP15

CALISTOGA_FCBGA1466~D
PMR3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 9 of 38
5 4 3 2 1
 5 4 3 2 1

+2.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1

C454

C461

C483

C462
U6H
+VCCP H22
VCC_SYNC +2.5VS 2 2 2 2 +3VS_TVDACB +3VS +3VS_TVDACA +3VS
AC14 R304 R35
VTT0
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS 2 1 2 1

2200P_0402_50V7K

2200P_0402_50V7K
W14 C30 0_0805_5% 0_0805_5%
VTT2 VCCTX_LVDS1 +1.5VS_PCIE

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V14 A30 R281
VTT3 VCCTX_LVDS2 0_0805_5%
T14
D
R14
VTT4
VTT5 VCC3G0 AB41 W=40 mils 10U_0805_6.3V6M 2 1 +1.5VS
1 1 1 1
D

C64
C488

C481

C493
P14 VTT6 VCC3G1 AJ41
N14 VTT7 VCC3G2 L41 1 2 2 2 2

220U_D2_4VM
M14 VTT8 VCC3G3 N41 1 C455 1 C457
L14 R41 C453+
VTT9 VCC3G4
AD13 VTT10 VCC3G5 V41
AC13 Y41 10U_0805_6.3V6M
VTT11 VCC3G6 2 2 2
AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL

330U_D2E_2.5VM_R9
Y13 VTT14 VCCA_3GBG G41 +2.5VS
C523 + W13 H41
VTT15 VSSA_3GBG
V13 VTT16
U13 VTT17
2 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 L29 +2.5VS

2200P_0402_50V7K
R13 F21 2.2_0603_5%
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21
+3VS_TVBG +3VS +3VS_TVDACC +3VS

22U_0805_6.3V6M
M13 VTT21 1 1 1
L13 C498 R307 R34
VTT22

C485

C484
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA 2 1 2 1

2200P_0402_50V7K
AA12 C39 +1.5VS_DPLLB 0.5_0805_1% 0_0805_5%
VTT24 VCCA_DPLLB 2 2 2

2200P_0402_50V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0805_6.3V6M

22U_0805_6.3V6M
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
W12 VTT26 1 1 1 1 1 1
V12 VTT27

C57
C494

C491
U12 VTT28 VCCA_LVDS A38 +2.5VS

C599

C495

C600
T12 VTT29 VSSA_LVDS B39
2 2 2 2 2 2
R12 VTT30
P12 VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
4.7U_0805_10V4Z

2.2U_0805_16V4Z

L12 VTT34 VCCA_TVBG H20 +3VS_TVBG

R11 VTT35 VSSA_TVBG G20
1 1 P11 VTT36
C507

C524

C C
N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB
N10 VTT41 VCCA_TVDACB1 D20
M10 E20
P9
N9
VTT42
VTT43
VCCA_TVDACC0
VCCA_TVDACC1 F20
+3VS_TVDACC
PCI-E/MEM/FSB PLL decoupling
VTT44
M9 VTT45
R8 AH1 +1.5VS KC FBM-L11-201209-221LMAT_0805
VTT46 VCCD_HMPLL0 KC FBM-L11-201209-221LMAT_0805
P8 VTT47 VCCD_HMPLL1 AH2
N8 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
VTT48 R18 R19 R40
M8 VTT49
P7 A28 1 2 2 1 0.022U_0402_16V7K 2 1
VTT50 VCCD_LVDS0

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N7 B28 0.5_0805_1%
VTT51 VCCD_LVDS1
M7 VTT52 VCCD_LVDS2 C28
R6 VTT53 1 1 1 1 1 1
P6 D21 +1.5VS_TVDAC C40 C492 C84 C83
VTT54 VCCD_TVDAC

C458

C41
M6 VTT55 VCCDQ_TVDAC H19
MCH_A6 A6 0.022U_0402_16V7K
VTT56 +3VS_VCCHV 2 2 2 2 2 2
R5 VTT57 VCCHV0 A23 1 2 +3VS
P5 B23 L36 0_0603_5% @ 10U_0805_6.3V6M
VTT58 VCCHV1
0.1U_0402_16V4Z
1 N5 B25 @
VTT59 VCCHV2 10U_0805_6.3V6M
M5 VTT60 1 1
C513 P4 AK31
0.47U_0402_6.3V6K VTT61 VCCAUX0 C477
N4 VTT62 VCCAUX1 AF31
2
C476

M4 AE31 22U_0805_6.3V6M
VTT63 VCCAUX2 2 2
R3 VTT64 VCCAUX3 AC31
P3 VTT65 VCCAUX4 AL30
+1.5VS_MPLL KC FBM-L11-201209-221LMAT_0805 +1.5VS_HPLL KC FBM-L11-201209-221LMAT_0805
N3 VTT66 VCCAUX5 AK30
0.22U_0603_10V7K

M3 AJ30 R322 R323

VTT67 VCCAUX6 +1.5VS
B
R2 VTT68 VCCAUX7 AH30 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS B
P2 VTT69 VCCAUX8 AG30
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 M2 VTT70 VCCAUX9 AF30
C505

MCH_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1 1 1 1 1
0.22U_0603_10V7K

R1 AC30 C521 C522

2 VTT73 VCCAUX12
C463

C515

C517
1 P1 AG29
MCH_AB1

VTT74 VCCAUX13
C518

N1 AF29 10U_0805_6.3V6M 10U_0805_6.3V6M

VTT75 VCCAUX14 2 2 2 2 2
M1 VTT76 VCCAUX15 AE29
VCCAUX16 AD29
2
VCCAUX17 AC29
1 VCCAUX18 AG28
VCCAUX19 AF28
C519 AE28
0.47U_0402_6.3V6K VCCAUX20
VCCAUX21 AH22
2
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
AF13 P19 +1.5VS_DPLLB KC FBM-L11-201209-221LMAT_0805 +1.5VS_DPLLA
VCCAUX36 VCCAUX27 KC FBM-L11-201209-221LMAT_0805
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15 R279 R303
VCCAUX38 VCCAUX29
AE12 VCCAUX39 VCCAUX30 P15 40mA Max. 2 1 +1.5VS 40mA Max. 2 1 +1.5VS
AD12 VCCAUX40 VCCAUX31 AH14

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_D2E_2.5VM_R9
1 1

330U_D2E_2.5VM_R9
CALISTOGA_FCBGA1466~D 1 1

C452

C469
PMR3@ C456 + +

C472
GM@ GM@
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 10 of 38
5 4 3 2 1
 5 4 3 2 1

POWER GND

+VCCP U6F +1.5VS +VCCP U6G +1.8V

U6I U6J
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AC27 AF27 W33 AT41 VCCSM_LF4 AA41 AC34 AL21 AC10
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 VCCSM_LF5 VSS1 VSS101 VSS201 VSS281
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41 W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
D D
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34 M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9

C38

C39
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34 AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34 AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
2 2
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30 AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30 AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
C496

C460

C482

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30 AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30 AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
T26 R19 T31 AP30 AY39 AH32 W19 K8
R26
VCC_NCTF18 VCCAUX_NCTF18
AG18 R31
VCC18 VCC_SM18
AN30 AT41 & AM41 AW39
VSS18 VSS118
AG32 K19
VSS218 VSS298
C8
VCC_NCTF19 VCCAUX_NCTF19 VCC19 VCC_SM19 VSS19 VSS119 VSS219 VSS299
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AB25 AG17 M31 AL29 +1.8V AN39 AC32 AH18 AP7
VCC_NCTF22 VCCAUX_NCTF22 VCC22 VCC_SM22 VSS22 VSS122 VSS222 VSS302
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29 AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
1U_0603_10V4Z
10U_0805_6.3V6M

10U_0805_6.3V6M

T25 W17 T30 AJ27 W39 AN31 AR17 R7

P O W E R

VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1 VSS28 VSS128 VSS228 VSS308

R25 V17 R30 AH27 V39 AJ31 AP17 G7
VCC_NCTF29 VCCAUX_NCTF29 VCC29 VCC_SM29 VSS29 VSS129 VSS229 P O W E R VSS309

C480

C512

C471

C497
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 T39 VSS30 VSS130 AG31 AM17 VSS230 VSS310 D7
C487

C468

AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26 R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
2 2 2 2
C459

AB24 AG16 M30 AW26 P39 Y31 AV16 AD6

2 2 2
AA24
VCC_NCTF32
VCC_NCTF33
VCCAUX_NCTF32
VCCAUX_NCTF33 AF16 L30
VCC32
VCC33
P O W E R VCC_SM32
VCC_SM33 AV26 N39
VSS32
VSS33
VSS132
VSS133 AB30 AN16
VSS232
VSS233
VSS312
VSS313 AB6
Y24 AE16 AA29 AU26 M39 E30 AL16 Y6
W24
VCC_NCTF34
VCC_NCTF35
VCCAUX_NCTF34
VCCAUX_NCTF35 AD16 Y29
VCC34
VCC35
VCC_SM34
VCC_SM35 AT26 L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
C C
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26 J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26 H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25 D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
U23 VCC_NCTF42 VCCAUX_NCTF42 U16 L29 VCC42 VCC_SM42 AH24 AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
T23 VCC_NCTF43 VCCAUX_NCTF43 T16 AB28 VCC43 VCC_SM43 BA23 AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23 AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
330U_D2E_2.5VM_R9

AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22 AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22 AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1 C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22 AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
C473 + R22 AC15 R28 AU22 C478 AH37 AP28 AD14 U4
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49 0.47U_0402_6.3V6K VSS49 VSS149 VSS249 VSS329
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22 AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
2
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22 Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
T21 VCC_NCTF53 VCCAUX_NCTF53 W15 L28 VCC53 VCC_SM53 AK22 W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22 V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N27 VCC55 VCC_SM55 AK21 T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23 R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
U20 VCC_NCTF57 VCCAUX_NCTF57 R15 L27 VCC57 VCC_SM57 BA19 P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19 N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
R20 VCC_NCTF59 N26 VCC59 VCC_SM59 AW19 M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3

10U_0805_6.3V6M

10U_0805_6.3V6M
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
V19 VCC_NCTF61 VSS_NCTF1 AE26 N25 VCC61 VCC_SM61 AU19 1 1 J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
330U_D2E_2.5VM_R9

U19 AE25 M25 AT19 C117 C42 H37 C27 F13 AC3
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62 VSS62 VSS162 VSS262 VSS342
T19 VCC_NCTF63 VSS_NCTF3 AE24 L25 VCC63 VCC_SM63 AR19 G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19 F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
C467 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19 D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
+ AB18 AE21 M24 AJ19 AY36 K26 AC12 AR2
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66 VSS66 VSS166 VSS266 VSS346
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18 AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
B B
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17 AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17 AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16 AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
U18 VCC_NCTF71 VSS_NCTF11 Y17 N23 VCC71 VCC_SM71 AH16 AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15 AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
L23 VCC73 VCC_SM73 AY15 AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
+1.8V
AC22 VCC74 VCC_SM74 AW15 C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2

0.47U_0402_6.3V6K
M19 VCC100 AB22 VCC75 VCC_SM75 AV15 B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
L19 VCC101 VCC_SM100 AR6 Y22 VCC76 VCC_SM76 AU15 1 BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15 AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
M18 AN6 P22 AR15 C501 AR35 AL24 AL10 F2
VCC103 VCC_SM102 VCC78 VCC_SM78 VSS78 VSS178 VSS278 VSS358
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15 AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14 AB35 VSS80 VSS180 AT23 VSS360 AL1
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13 AA35 VSS81 VSS181 AN23
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC21 VCC82 VCC_SM82 AH13 Y35 VSS82 VSS182 AM23 CALISTOGA_FCBGA1466~D
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AA21 VCC83 VCC_SM83 AK12 W35 VSS83 VSS183 AH23
M16 VCC109 W21 VCC84 VCC_SM84 AJ12 V35 VSS84 VSS184 AC23 PMR3@
L16 VCC110 N21 VCC85 VCC_SM85 AH12 T35 VSS85 VSS185 W23
M21 VCC86 VCC_SM86 AG12 Place near pin BA15 R35 VSS86 VSS186 K23
L21 VCC87 VCC_SM87 AK11 P35 VSS87 VSS187 J23
CALISTOGA_FCBGA1466~D AC20 BA8 N35 F23
PMR3@ VCC88 VCC_SM88 VSS88 VSS188
AB20 VCC89 VCC_SM89 AY8 M35 VSS89 VSS189 C23
Y20 VCC90 VCC_SM90 AW8 L35 VSS90 VSS190 AA22
W20 VCC91 VCC_SM91 AV8 J35 VSS91 VSS191 K22
VCCSM_LF2 P20 AT8 H35 G22
VCCSM_LF1 VCC92 VCC_SM92 VSS92 VSS192
N20 VCC93 VCC_SM93 AR8 G35 VSS93 VSS193 F22
M20 VCC94 VCC_SM94 AP8 F35 VSS94 VSS194 E22
L20 VCC95 VCC_SM95 BA6 D35 VSS95 VSS195 D22
0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

AB19 VCC96 VCC_SM96 AY6 AN34 VSS96 VSS196 A22

1 1 AA19 VCC97 VCC_SM97 AW6 AK34 VSS97 VSS197 BA21
C516

C520

Y19 VCC98 VCC_SM98 AV6 AG34 VSS98 VSS198 AV21

N19 VCC99 VCC_SM99 AT6 AF34 VSS99 VSS199 AR21
A A
2 2 CALISTOGA_FCBGA1466~D
CALISTOGA_FCBGA1466~D
PMR3@ PMR3@

Place near pin AV1 & AJ1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 11 of 38
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V +DDR_VREF

8 DDR_A_DQS#[0..7]

8 DDR_A_D[0..63] JP15

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
DDR_A_D7 +1.8V
8 DDR_A_DM[0..7] 3 VSS DQ4 4 1 1

C36

C35
DDR_A_D0 5 6 DDR_A_D1
DDR_A_D4 DQ0 DQ5
8 DDR_A_DQS[0..7] 7 DQ1 VSS 8

1
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2 R427
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D6 1K_0402_1%
15 VSS DQ7 16
DDR_A_D2 17 18

2
D DDR_A_D3 DQ2 VSS DDR_A_D12 D
19 DQ3 DQ12 20 +DDR_VREF
21 22 DDR_A_D13
VSS DQ13

1
DDR_A_D8 23 24 15mils
DDR_A_D14 DQ8 VSS DDR_A_DM1 R428
Layout Note: 25 DQ9 DM1 26
27 VSS VSS 28
Place near JP27 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7
1K_0402_1%
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 32 M_CLK_DDR#0 7

2
DQS1 CK0#
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D9
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D21 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D16
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50 DDR_TS DDR_TS 7,13
DDR_A_DQS2 DQS2# NC DDR_A_DM2
1 1 1 1 1 1 1 1 1 51 DQS2 DM2 52
C110

C107
C62

C58

C96

C79

C73

C97

C88
53 VSS VSS 54
DDR_A_D22 55 56 DDR_A_D18
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D25 61 62 DDR_A_D29
DDR_A_D24 DQ24 DQ28 DDR_A_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D27 73 74 DDR_A_D26
DDR_A_D30 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
8 DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS 8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D35 123 124 DDR_A_D36
DDR_A_D32 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C104

C103

C114

C115

C119
C55

C56

C68

C67

C81

C80

C92

C95

133 134 DDR_A_D34

DDR_A_D39 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D33 137 138
DQ35 VSS DDR_A_D40
139 VSS DQ44 140
DDR_A_D45 141 142 DDR_A_D44
B DDR_A_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D47
DDR_A_D43 DQ42 DQ46 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D52 157 158 DDR_A_D48
DDR_A_D53 DQ48 DQ52 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9VS NC,TEST CK1 M_CLK_DDR1 7
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
RP10 RP2 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA8 1 4 4 1 DDR_A_BS#2 closely JP27,all 171 172
DDR_A_MA5 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D51 173 DQ50 DQ54 174 DDR_A_D50
DDR_A_D55 175 176 DDR_A_D54
RP12 56_0404_4P2R_5% RP9 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D57
183 VSS VSS 184
RP22 56_0404_4P2R_5% RP6 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_CS0_DIMMA# 1 DM7 DQS7#
4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_A_RAS# 2 3 3 2 DDR_A_MA12 DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA2 13,14 CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA4 CLK_SMBCLK 197 198
13,14 CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP21 56_0404_4P2R_5% RP18 56_0404_4P2R_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C133 PTI_A5652D-A0G16-P
A A
RP25 56_0404_4P2R_5% RP26 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 DDR_A_MA13
0.1U_0402_16V4Z
2 DIMM0 RVS H:5.2mm (BOT)
M_ODT1 1 4 3 2 M_ODT0

56_0404_4P2R_5% RP5 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA
3 2 DDR_A_MA11 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 12 of 38
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
8 DDR_B_DQS#[0..7] +DDR_VREF
8 DDR_B_D[0..63]

8 DDR_B_DM[0..7] JP16

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D1
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6

C37

C34
DDR_B_D5 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D2
15 VSS DQ7 16
D DDR_B_D7 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP26 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 7
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D21 43 44 DDR_B_D16
DDR_B_D17 DQ16 DQ20 DDR_B_D20
1 1 1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C59

C113

C60

C90

C109

C74

C89

C99

C70

220U_D2_4VM

220U_D2_4VM
47 VSS VSS 48
+ C126 + C43 DDR_B_DQS#2 49 50 DDR_TS
DQS2# NC DDR_TS 7,12
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
2 2 DDR_B_D22 DDR_B_D18
55 DQ18 DQ22 56
DDR_B_D23 57 58 DDR_B_D19
DQ19 DQ23
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
7 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 7
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
8 DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D37 123 124 DDR_B_D33
DDR_B_D36 DQ32 DQ36 DDR_B_D32
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C101

C111

C105

C112

C118
C53

C65

C77

C91

C54

C66

C78

C94

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D43
DDR_B_D47 DQ42 DQ46 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D49
DDR_B_D53 DQ48 DQ52 DDR_B_D52
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP26,all NC,TEST CK1 M_CLK_DDR2 7
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 7
RP13 RP4 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP16 56_0404_4P2R_5% RP3 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_MA10 1 4 4 1 DDR_CKE3_DIMMB 177 178
DDR_B_BS#0 DDR_B_MA11 DDR_B_D60 VSS VSS DDR_B_D56
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP15 56_0404_4P2R_5% RP8 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D58 189 190
RP19 56_0404_4P2R_5% RP7 56_0404_4P2R_5% DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 193 194 DDR_B_D63
DDR_CS2_DIMMB# 2 DDR_B_MA6 CLK_SMBDATA VSS DQ63
3 3 2 12,14 CLK_SMBDATA 195 SDA VSS 196
CLK_SMBCLK 197 198
12,14 CLK_SMBCLK SCL SAO
RP20 56_0404_4P2R_5% RP14 56_0404_4P2R_5% 199 200 +3VS
+3VS VDDSPD SA1
DDR_B_WE# 1 4 4 1 DDR_B_MA2
DDR_B_CAS# 2 3 3 2 DDR_B_MA4 1
A RP24 C132 P-TWO_A5692B-A0G16-P A
56_0404_4P2R_5% RP23 56_0404_4P2R_5%
M_ODT3 2 3 4 1 M_ODT2 0.1U_0402_16V4Z
DDR_CS3_DIMMB# 1 DDR_B_MA13 2
4 3 2

56_0404_4P2R_5% RP1
DIMM1 RVS H:9.2mm (BOT)
4 1 DDR_B_BS#2
3 2 DDR_CKE2_DIMMB

56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 13 of 38
5 4 3 2 1
 5 4 3 2 1

+CK_VDD_MAIN1 +CK_VDD_DP
+3VS R129 R127
+3VS 1 2 +3VS 1 2
1 1 1 1 1 1 1 1
KC FBM-L11-201209-221LMAT_0805 C227 C166 C219 C226 KC FBM-L11-201209-221LMAT_0805 C165 C213 C231 C230
2 1 PCIEC_CLKREQ#
10K_0402_5% R92 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
2 1 SATA_CLKREQ#
10K_0402_5% R333
2 1 MCH_CLKREQ#
10K_0402_5% R106
2 1 MINI_CLKREQ# +CK_VDD_MAIN2
D 10K_0402_5% R118 D
R79 R86
+3VS 1 2 1 2 +CK_VDD_REF
1 1 1 1_0805_1%
KC FBM-L11-201209-221LMAT_0805 C157 C234 C160
1 2 +CK_VDD_48
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R128
FSLC FSLB FSLA CPU SRC PCI 2 2 2 2.2_0805_1%
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
0 0 1 133 100 33.3
C170 0.1U_0402_16V4Z
+CK_VDD_DP U9 1 2
0 1 1 166 100 33.3
R82
1 7 +VDDAD 2 1 +3VS
VDDSRC VDDA KC FBM-L11-201209-221LMAT_0805
49 VDDSRC
54 8
FSA 65
VDDSRC
VDDSRC
GNDA
+CK_VDD_MAIN1

PCI_SRC_STOP# 25 H_STP_PCI# 18
FSA 2 1 1 2 30
MCH_CLKSEL0 7 VDDPCI
R133 8.2K_0402_5% 36 24
VDDPCI CPU_STOP# H_STP_CPU# 18
R137
5 CPU_BSEL0
1K_0402_5% 12 VDDCPU
2 R136 1 0.1U_0402_16V4Z
CPUCLKT1LP 11 CLK_MCH_BCLK 7
@ 1K_0402_5% C167 1 2 +CK_VDD_REF 18
VDDREF
CPUCLKC1LP 10 CLK_MCH_BCLK# 7
1 2 1 2 +CK_VDD_48 40
C197 C229 VDD48

1
22P_0402_50V8J 0.1U_0402_16V4Z 14
C +VCCP CPUCLKT0LP CLK_CPU_BCLK 4 C
CLK_XTAL_IN 20
FSB Y2 X1
CPUCLKC0LP 13 CLK_CPU_BCLK# 4
22P_0402_50V8J 14.31818MHZ_20P_6X1430004201

2
2

C168 1 2 CLK_XTAL_OUT 19
R331 X2
CPUCLKT2_ITP/SRCCLKT10LP 6
@ 18 CLK_48M_ICH CLK_48M_ICH 2 1 R132
1K_0402_5% 12_0402_5% FSA 41 5
CLK_48M_CB USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
20 CLK_48M_CB 2 1 R124
1

FSB 1 2 12_0402_5% FSB 45

MCH_CLKSEL1 7 FSLB/TEST_MODE/24Mhz
SRCCLKT9LP 3
R328 18 CLK_14M_ICH CLK_14M_ICH 2 1 R99 FSC 23
5 CPU_BSEL1 REF0/FSLC/TEST_SEL
1K_0402_5% 39_0402_5% 2
SRCCLKC9LP

20 CLK_PCI_PCM 2 1 R119 PCI_PCM 34 72 PCIEC_CLKREQ#

+VCCP 33_0402_5% PCICLK4/FCTSEL1 CLKREQ9#
FSC 26 CLK_PCI_EC 2 1 R121 PCI_EC 33 SEL_48M/PCICLK3 SRCCLKT8LP 70
39_0402_5%
(Fixed at low)
2

29 CLK_PCI_SIO2 2 1 R506 PCI_DEBUG 32

SEL_24M/PCICLK2 SRCCLKC8LP 69
R108 39_0402_5%
27 SEL_PCI6/PCICLK1 CLKREQ8# 71
R103 @ 1K_0402_5%
8.2K_0402_5% 66 CLK_PCIE_SATA 17
1

FSC REF1 SRCCLKT7LP

2 1 1 2 MCH_CLKSEL2 7 22 SEL_PCI5/REF1
SRCCLKC7LP 67 CLK_PCIE_SATA# 17
R102
5 CPU_BSEL2
1K_0402_5% 7 CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 43 38 SATA_CLKREQ# SATA_CLKREQ# 18
R125 GM@ 33_0402_5% DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1
7 CLK_MCH_DREFCLK# CLK_MCH_DREFCLK# 1 2 MCH_DREFCLK# 44 63
R126 GM@ 33_0402_5% DOTC_96MHz/27MHz_spread SRCCLKT6LP
+3VS 64
CLK_PCI_ICH PCI_ICH SRCCLKC6LP
18 CLK_PCI_ICH 2 1 37 ITP_EN/PCICLK_F0
R336 33_0402_5% 62
CLKREQ6#
1

B B
CLK_ENABLE# 39 60
10K_0402_5% 36 CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_MCH_3GPLL 7
R332 61
SRCCLKC5LP CLK_MCH_3GPLL# 7
9
2

GND MCH_CLKREQ#
CLKREQ5#/PCICLK6 29 MCH_CLKREQ# 7
CLK_ENABLE#
SRCCLKT4LP 58 CLK_PCIE_MCARD 25
1

D CLK_SMBCLK
12,13 CLK_SMBCLK 16 SMBCLK
18,26,36 VGATE 2 SRCCLKC4LP 59 CLK_PCIE_MCARD# 25
G
Q16 S 57 MINI_CLKREQ#
MINI_CLKREQ# 25
3

2N7002_SOT23 @ CLK_SMBDATA CLKREQ4#

12,13 CLK_SMBDATA 17 SMBDAT
SRCCLKT3LP 55 CLK_PCIE_ICH 18
R81
+3VS
2.2K_0402_5% 4 56
GNDSRC SRCCLKC3LP CLK_PCIE_ICH# 18
2
G

+3VS 15 28
GNDCPU CLKREQ3#/PCICLK5
18,25 ICH_SMBCLK 1 3 Q10
2N7002_SOT23 21 52
D

GNDREF SRCCLKT2LP CLK_PCIE_LAN 22

1:CPU ITP *0:SRC 10 PCI_ICH
for Pin 6,5 31 GNDPCI SRCCLKC2LP 53 CLK_PCIE_LAN# 22
R337 1 2 R80
+3VS
10K_0402_5% 2.2K_0402_5% 35 26
GNDPCI CLKREQ2#
2
G

1:24M *0:test Mode PCI_DEBUG 42 50

GND48 SRCCLKT1LP CLK_PCIE_VGA 16
for Pin 45 18,25 ICH_SMBDATA 1 3 Q9
R116 1 2 2N7002_SOT23 68 51
D

GNDSRC SRCCLKC1LP CLK_PCIE_VGA# 16

10K_0402_5%
CLKREQ1# 46 Need BIOS to disable when GM SKU
1:27M/SRC0 *0:DOT 96M/LCD100 PCI_PCM 73 THRM_PAD
for Pin 43,44/47,48 74 THRM_PAD LCD100/96/SRC0_TLP 47 CLK_PCIE_GMCH 7
A R327 1 A
2 75 THRM_PAD
10K_0402_5% 76 48
THRM_PAD LCD100/96/SRC0_CLP CLK_PCIE_GMCH# 7
1:48M *0:CLKREQ7#
for Pin 38 PCI_EC Need BIOS to disable when PM SKU
R123 1 2 ICS9LPRS325CKLFT_MLF72
10K_0402_5%
*1:PCICLK3 0:CLKREQ5#
for Pin28 REF1 R100 1 2
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 14 of 38
5 4 3 2 1
 A B C D E

Near to JP13
CRT CONNECTOR +5VS
D3
+R_CRT_VCC
F1
+CRT_VCC

1
D25 D24 D23 2 1 1 2

+3VS
CH491D_SC59 1
1A_6VDC_MINISMDC110 C13
CRT Conn.
DAN217_SC59 DAN217_SC59 DAN217_SC59 0.1U_0402_16V4Z

3
2
@ @ @
JP13
6
L3 11
1 2 CRT_R 1 2 CRT_R_L 1
1 16 VGA_CRT_R 1
R277 PM@ 0_0402_5% BK1608LL121-T_0603 7
9 GMCH_CRT_R 1 2 12
R278 GM@ 0_0402_5% CRT_G_L 2
8
L2 13
1 2 CRT_G 1 2 CRT_B_L 3
16 VGA_CRT_G
R275 PM@ 0_0402_5% BK1608LL121-T_0603 9
9 GMCH_CRT_G 1 2 14
R276 GM@ 0_0402_5% 4
L1 1 10 16
1 2 CRT_B 1 2 15 17
16 VGA_CRT_B C12
R273 PM@ 0_0402_5% BK1608LL121-T_0603 5

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
9 GMCH_CRT_B 1 2
2

150_0402_1%

150_0402_1%

150_0402_1%
R274 GM@ 0_0402_5% 1 1 1 SUYIN _070546FR015S233CR

1
C16 C19 C21 1 1 1
R6 R5 R3 C22 C20 C17 DSUB_12_DATA
GM@ GM@ GM@ 220P_0402_50V7K
2 2 2 DSUB_15_CLK
2 2 2

68P_0402_50V8K

68P_0402_50V8K
GM@ GM@ GM@ 1 1
C14 C8
+CRT_VCC
2 2
1 2 2 1
C18 0.1U_0402_16V4Z R4 10K_0402_5%

5
1
P
OE#
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
16 VGA_CRT_HSYNC A Y
R30 PM@ 0_0402_5% L26 10_0402_5%

G
1 2 U2
9 GMCH_CRT_HSYNC
R32 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
2
3 L25 10_0402_5% 2
+CRT_VCC

10P_0402_50V8J

10P_0402_50V8J
1 1
1 2 C413 C411
C15 0.1U_0402_16V4Z

5
1
2 2

P
OE#
1 2 CRT_VSYNC 2 4
16 VGA_CRT_VSYNC A Y
R29 PM@ 0_0402_5%

G
1 2 U1 +CRT_VCC
9 GMCH_CRT_VSYNC +3VS
R31 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

1
GM@
9 GMCH_CRT_DATA 1 2
0_0402_5% R266 R1 R2

2
G
4.7K_0402_5% 4.7K_0402_5%
PM@

2
1 2 3 1 DSUB_12_DATA
16 VGA_DDC_DATA
0_0402_5% R265

D
2
G
Q26
PM@ 2N7002_SOT23
1 2 3 1 DSUB_15_CLK
16 VGA_DDC_CLK
0_0402_5% R267

D
GM@ Q27
1 2 2N7002_SOT23
9 GMCH_CRT_CLK
0_0402_5% R268

3 3

D10 D9
@ DAN217_SC59 @ DAN217_SC59
1

1
2

+3VS
1 2 C145
1 2 @ 22P_0402_50V8J
16 VGA_TV_LUMA
R42 PM@ 0_0402_5%
1 2 TV_LUMA L15 1 2
9 GMCH_TV_LUMA
R43 GM@ 0_0402_5% FBM-11-160808-121T_0603

1 2 TV_CRMA L14 1 2
16 VGA_TV_CRMA
R38 PM@ 0_0402_5% FBM-11-160808-121T_0603
1 2 JP17
9 GMCH_TV_CRMA
1

R39 GM@ 0_0402_5% 1 2 C142 TV_CRMA_L 4 4

1

1 1 @ 22P_0402_50V8J TV_LUMA_L 3 6
R71 R77 3
2 5
150_0402_1% 150_0402_1% C131
100P_0402_50V8J
C143
100P_0402_50V8J
1
C141
1
C153
1
2
1
TV-OUT Conn.
2

2 2 ALLTO_C10877-104A1-L_4P 1. Y ground
2

2 2
2. C ground
100P_0402_50V8J 100P_0402_50V8J 3. Y (luminance+sync)
4 4. C (crominance) 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 15 of 38
A B C D E
 5 4 3 2 1

+LCDVDD +5VALW

LCD POWER CIRCUIT VGA BOARD Conn.

2
R272
R263 +3VS
1M_0402_5%
470_0805_5% PCIE_MTX_C_GRX_N[0..15]
9 PCIE_MTX_C_GRX_N[0..15]
W=60mils

1 2

1
PCIE_MTX_C_GRX_P[0..15]
R269 9 PCIE_MTX_C_GRX_P[0..15]

3
D S
Q28
Q29 2 1 2 2 PCIE_GTX_C_MRX_N[0..15]
9 PCIE_GTX_C_MRX_N[0..15]
2N7002_SOT23 G
S 100K_0402_5% PCIE_GTX_C_MRX_P[0..15]
9 PCIE_GTX_C_MRX_P[0..15]

1000P_0402_50V7K
+LCDVDD
G
AOS 3401_SOT23

BSS138_SOT23
D
2 W=60mils

1
1
D D D
R264 1 2 VGA_ENVDD 2 C418
9 GMCH_ENVDD

4.7U_0805_10V4Z
0_0402_5% GM@ G 1 1

2
Q30 S 1 C414 C416

3
R289
0.1U_0402_16V4Z JP14
2.2K_0402_5% 2 2
TXCLK+ 1 2 TXOUT2+

1
TXCLK- 3 4 TXOUT2-
5 6
TXOUT1+ 7 8 TXOUT0+
+3VS TXOUT1- 9 10 TXOUT0-
11 12
VGA_TV_CRMA 13 14 VGA_TV_LUMA
15 VGA_TV_CRMA 15 16 VGA_TV_LUMA 15
1

R262 PCIE_GTX_C_MRX_P0 17 18 PCIE_MTX_C_GRX_P0

PCIE_GTX_C_MRX_N0 19 20 PCIE_MTX_C_GRX_N0
D26 4.7K_0402_5% INVPWR_B+ 21 22
RB751V_SOD323 PCIE_GTX_C_MRX_P1 23 24 PCIE_MTX_C_GRX_P1
2

PCIE_GTX_C_MRX_N1 25 26 PCIE_MTX_C_GRX_N1
DISPOFF# 27 28
26 BKOFF# 1 2 1 2 B+ 29 30

0.1U_0603_25V7K
1 1 L4 PCIE_GTX_C_MRX_P2 PCIE_MTX_C_GRX_P2
C23 KC FBM-L11-201209-221LMAT_0805 PCIE_GTX_C_MRX_N2 31 32 PCIE_MTX_C_GRX_N2
C24 33 34
68P_0402_50V8K PCIE_GTX_C_MRX_P3 35 36 PCIE_MTX_C_GRX_P3
2 2 37 38
2 1 C417 +LCDVDD_LCD PCIE_GTX_C_MRX_N3
39 40
PCIE_MTX_C_GRX_N3
0.1U_0402_16V4Z
PCIE_GTX_C_MRX_P4 41 42 PCIE_MTX_C_GRX_P4
43 44
2 1 C415 +3VS_LCD PCIE_GTX_C_MRX_N4
45 46
PCIE_MTX_C_GRX_N4
0.1U_0402_16V4Z
PCIE_GTX_C_MRX_P5 47 48 PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 49 50 PCIE_MTX_C_GRX_N5
C 51 52 C
PCIE_GTX_C_MRX_P6 53 54 PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 55 56 PCIE_MTX_C_GRX_N6
LCD/PANEL BD. Conn. For EMI Request PCIE_GTX_C_MRX_P7
57
59
58
60 PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 61 62 PCIE_MTX_C_GRX_N7
JP1 LCD_CLK 63 64
1 2 65 66
C805 @ 47P_0402_50V8J PCIE_GTX_C_MRX_P8 PCIE_MTX_C_GRX_P8
2 1 TXCLK- LCD_DATA PCIE_GTX_C_MRX_N8 67 68 PCIE_MTX_C_GRX_N8
4 3 1 2 69 70
TXCLK+ C806 @ 47P_0402_50V8J
+LCDVDD_LCD 6 5 DAC_BRIG PCIE_GTX_C_MRX_P9 71 72 PCIE_MTX_C_GRX_P9
+LCDVDD 2 1 R270 8 7 1 2 73 74
FBMA-L11-321611-121LMA30T_1206 TXOUT0- C807 @ 220P_0402_50V7K PCIE_GTX_C_MRX_N9 PCIE_MTX_C_GRX_N9
10 9 75 76
+3VS 1 2 R271 +3VS_LCD
12 11
TXOUT0+ 1 1 INVT_PWM 1 2 77 78
6P_0402_50V8K

6P_0402_50V8K

FBMA-L11-201209-121LMT 0805 C667 C668 C808 @ 220P_0402_50V7K PCIE_GTX_C_MRX_P10 PCIE_MTX_C_GRX_P10

LCD_CLK 14 13 TXOUT2- DISPOFF# PCIE_GTX_C_MRX_N10 79 80 PCIE_MTX_C_GRX_N10
16 15 1 2 81 82
LCD_DATA TXOUT2+ C809 @ 220P_0402_50V7K
DAC_BRIG 18 17 2 2 PCIE_GTX_C_MRX_P11 83 84 PCIE_MTX_C_GRX_P11
26 DAC_BRIG 20 19 85 86
INVT_PWM TXOUT1- PCIE_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N11
26 INVT_PWM 22 21 87 88
DISPOFF# TXOUT1+
24 23 PCIE_GTX_C_MRX_P12 89 90 PCIE_MTX_C_GRX_P12
26 25 PCIE_GTX_C_MRX_N12 91 92 PCIE_MTX_C_GRX_N12
28 27 93 94
INVPWR_B+ 30 29 INVPWR_B+ 95 96
PCIE_GTX_C_MRX_P13 PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 97 98 PCIE_MTX_C_GRX_N13
ACES_88242-3000 99 100
PCIE_GTX_C_MRX_P14 101 102 PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_N14 103 104 PCIE_MTX_C_GRX_N14
105 106
PCIE_GTX_C_MRX_P15 107 108 PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 109 110 PCIE_MTX_C_GRX_N15
+3VALW 111 112
VGA_CRT_VSYNC 113 114 CLK_PCIE_VGA
B 15 VGA_CRT_VSYNC 115 116 CLK_PCIE_VGA 14 B
CLK_PCIE_VGA#
14

117 118 CLK_PCIE_VGA# 14

U24D VGA_CRT_HSYNC
15 VGA_CRT_HSYNC 119 120
12 VGA_LCD_DATA
P

7,18,22,25 PLT_RST# A 121 122

11 PLTRSTR# VGA_CRT_B VGA_LCD_CLK
O 15 VGA_CRT_B 123 124
13 VGA_ENVDD
B 125 126
G

VGA_CRT_G VGA_DDC_CLK
15 VGA_CRT_G 127 128 VGA_DDC_CLK 15
VGA_DDC_DATA
VGA_DDC_DATA 15
7

VGA_CRT_R 129 130 VGA_ENBKL

15 VGA_CRT_R 131 132 VGA_ENBKL 26
SUSP#
133 134 SUSP# 23,26,27,29,34,35
SN74LVC32APWLE_TSSOP14 PLTRSTR#
135 136 R542
137 138 1 2 PM@ 0_0402_5% EC_SMB_CK2 4,26
R543 1 2 PM@ 0_0402_5% EC_SMB_DA2 4,26
139 140
+1.8VS 141 142 +5VALW
143 144 +1.8VS
145 146
147 148
+B_L 149 150 +1.5VS I = 600mA
B+ 1 2 151 152
PM@ L28
FBM-L11-201209-121LMT_0805 153 154
I = 1.5 A (Max) 155 156 +2.5VS I = 460mA
1 2 157 158 +3VS
PM@ L27
FBM-L11-201209-121LMT_0805 159 160
PM@ ACES_88081-1600
LCD_CLK R608 2 1PM@ 0_0402_5% VGA_LCD_CLK
LCD_DATA R609 2 1PM@ 0_0402_5% VGA_LCD_DATA
R7 2 1GM@ 0_0402_5%
GMCH_LCD_CLK 9
R8 2 1GM@ 0_0402_5%
GMCH_LCD_DATA 9
TXOUT0- R12 1 2GM@ 0_0402_5% GMCH_TXOUT0- 9
TXOUT0+ R13 1 2GM@ 0_0402_5% GMCH_TXOUT0+ 9
A TXOUT1- R23 A
1 2GM@ 0_0402_5% GMCH_TXOUT1- 9
TXOUT1+ R22 1 2GM@ 0_0402_5% GMCH_TXOUT1+ 9
TXOUT2- R25 1 2GM@ 0_0402_5% GMCH_TXOUT2- 9
TXOUT2+ R24 1 2GM@ 0_0402_5% GMCH_TXOUT2+ 9
TXCLK- R21 1 2GM@ 0_0402_5% GMCH_TXCLK- 9
TXCLK+ R20 1 2GM@ 0_0402_5% GMCH_TXCLK+ 9 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
VGA / LCD CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 16 of 38
5 4 3 2 1
 5 4 3 2 1

JP9
1st SATA HDD CONN
SATA_TXP0_C 2 1 1 GND
C298 2 1 15P_0402_50V8J ICH_RTCX1 3900P_0402_50V7K C264 SATA_TXP0 2
SATA_TXN0_C SATA_TXN0 A+
2 1 3 A-
3900P_0402_50V7K C272 4 GND

1
Y4 SATA_RXN0_C 2 1 SATA_RXN0 5
R180 3900P_0402_50V7K C242 SATA_RXP0 B-
2 NC IN 1 6 B+
32.768KHZ_12.5P_1TJS125BJ2A251 SATA_RXP0_C 2 1 7
10M_0402_5% 3900P_0402_50V7K C244 GND
3 NC OUT 4
U16A +3VS

2
+3VS 8 V33

RTC
AB1 AA6 LPC_AD0 LPC_AD0 26,29 9
C287 RTXC1 LAD0 V33
2 1 15P_0402_50V8J ICH_RTCX2 AB2 RTCX2 LAD1 AB5 LPC_AD1 LPC_AD1 26,29 10 V33
AC4 LPC_AD2 LPC_AD2 26,29 1 1 1 1 11
D R149 1 ICH_RTCRST# AA3 LAD2 LPC_AD3 C608 C609 C610 C611 GND D
+RTCVCC 2 RTCRST# LAD3 Y6 LPC_AD3 26,29 12 GND

LPC
20K_0402_5% 13
R168 10U_0805_10V4Z GND
ICH_INTVRMEN W4 AC3 0.1U_0402_16V4Z +5VS 14
J1 INTVRMEN LDRQ0# 2 2 2 2 V5
+RTCVCC 1 2 SM_INTRUDER# Y5 AA5 LPC_DRQ#1 15
INTRUDER# LDRQ1# / GPIO23 LPC_DRQ#1 29 V5
1 2 1M_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 16
1 2 LPC_FRAME# V5
LFRAME# AB3 LPC_FRAME# 26,29 17 GND
@ W1 18
JUMP_43X79 EE_CS Reserved
Y1 EE_SHCLK 2 1 R349 10K_0402_5% +3VS 19 GND
C246 Y2 AE22 GATEA20 +5VS Place components close to SATA CONN. 20
EE_DOUT A20GATE GATEA20 26 V12

LAN
1U_0402_6.3V4Z W3 AH28 H_A20M# 21
EE_DIN A20M# H_A20M# 4 V12

CPU
1 2 22 V12
V3 LAN_CLK CPUSLP# AG27
1 1 1 1
25 ACZ_BITCLK_MDC 1 2 L41 BITCLK_MDC 1 2 R189 U3 LAN_RSTSYNC TP1 / DPRSTP# AF24 H_DPRSTP# 4,36
C274 C266 C267 C268 SUYIN_127072FR022G210ZR_RV
0_0402_5% 47_0402_5% AH25 H_DPSLP#
TP2 / DPSLP# H_DPSLP# 4 10U_0805_10V4Z
2 1 U5 R158 2 1 56_0402_5% +VCCP 0.1U_0402_16V4Z
22P_0402_50V8J C589 LAN_RXD0 H_FERR# 2 2 2 2
V4 LAN_RXD1 FERR# AG26 H_FERR# 4
T5 LAN_RXD2
2 1 AG24 H_PW RGOOD 0.1U_0402_16V4Z 0.1U_0402_16V4Z
GPIO49 / CPUPWRGD H_PWRGOOD 4
22P_0402_50V8J C590 U7
BITCLK_AUDIO1 LAN_TXD0 H_IGNNE#
23 ICH_BITCLK_AUDIO 1 2 L42 2 R183 V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# 4
0_0402_5% 47_0402_5% V7 AG21
33_0402_5% 1 LAN_TXD2 INIT3_3V# H_INIT#
25 ACZ_SYNC_MDC 2 R202 INIT# AF22 H_INIT# 4
AF25 H_INTR +3VS +VCCP
INTR H_INTR 4
23 ICH_SYNC_AUDIO 33_0402_5% 2 1 R201

AC-97/AZALIA
ACZ_BITCLK U1 R345 2 1 10K_0402_5%
33_0402_5% 1 ACZ_BCLK
2 R211 ACZ _SYNC R6 AG23 EC_KBRST#
25 ACZ_RST#_MDC ACZ_SYNC RCIN# EC_KBRST# 26
2nd SATA HDD CONN

1
23 ICH_RST_AUDIO# 33_0402_5% 2 1 R210 ACZ_RST# R5 AF23 H_SMI# R160
ACZ_RST# SMI# H_SMI# 4
AH24 H_NMI
NMI H_NMI 4
ACZ_SDIN0 T2 56_0402_5% JP31 2HDD@
23 ICH_AC_SDIN0 ACZ_SDIN0
ACZ_SDIN1 T3 AH22 H_STPCLK#
25 ACZ_SDIN1 H_STPCLK# 4

2
C ACZ_SDIN1 STPCLK# SATA_TXP1_C C
T1 ACZ_SDIN2 2 1 1 GND
AF26 THRMTRIP_ICH# 1 R159 2 3900P_0402_50V7K C712 2HDD@ SATA_TXP1 2
THERMTRIP# H_THERMTRIP# 4,7 A+
23 ICH_SDOUT_AUDIO 33_0402_5% 2 1 R197 ACZ_SDOUT T4 24.9_0402_1% SATA_TXN1_C 2 1 SATA_TXN1 3
33_0402_5% 2 ACZ_SDOUT A-
25 ACZ_SDOUT_MDC 1 R198 ***Must be placed close to AF26 pin within 2" 3900P_0402_50V7K C713 2HDD@ 4 GND
+3VS 2 1 R348 DA0 AH17 PD_A0 SATA_RXN1_C 2 1 SATA_RXN1 5 B-
26 PHDD_LED# 20K_0402_5% PHDD_LED# AF18 AE17 PD_A1 3900P_0402_50V7K C714 2HDD@ SATA_RXP1 6
SATALED# DA1 PD_A2 SATA_RXP1_C B+
DA2 AF17 2 1 7 GND
3900P_0402_50V7K C715 2HDD@
SATA_RXN0_C AF3 AE16 PD_CS#1 +3VS
SATA_RXP0_C SATA0RXN DCS1# PD_CS#3
AE3 SATA0RXP DCS3# AD16
SATA_TXN0_C AG2 +3VS 8
SATA0TXN VCC3.3

SATA
SATA_TXP0_C AH2 9
SATA0TXP PD_D0 VCC3.3
DD0 AB15 1 1 1 1 10 VCC3.3
SATA_RXN1_C AF7 AE14 PD_D1 C716 C717 C718 C719 11
SATA_RXP1_C SATA2RXN DD1 PD_D2 2HDD@ 2HDD@ GND
AE7 SATA2RXP DD2 AG13 12 GND
SATA_TXN1_C AG6 AF13 PD_D3 10U_0805_10V4Z 2HDD@ 0.1U_0402_16V4Z2HDD@ 13
+RTCVCC SATA_TXP1_C SATA2TXN DD3 PD_D4 2 2 2 2 GND
AH6 SATA2TXP DD4 AD14 +5VS 14 VCC5
AC13 PD_D5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 15
CLK_PCIE_SATA# AF1 DD5 PD_D6 VCC5
14 CLK_PCIE_SATA# SATA_CLKN DD6 AD12 16 VCC5
CLK_PCIE_SATA AE1 AC12 PD_D7 17
14 CLK_PCIE_SATA SATA_CLKP DD7 GND
1

AE12 PD_D8 18
R152 R148 DD8 PD_D9 +5VS RESERVED
AH10 SATARBIASN DD9 AF12 Place components close to SATA CONN. 19 GND
1 2 AG10 AB13 PD_D10 20
332K_0402_1% SATARBIASP DD10 PD_D11 VCC12
DD11 AC14 21 VCC12
24.9_0402_1% AF14 PD_D12 22
2

DD12 PD_D13 VCC12

DD13 AH13 1 1 1 1
ICH_INTVRMEN PD_D14 C720 C721 C722 C723
4.7K_0402_5% 2 1 R166 PD _IORDY AG16
IDE DD14 AH14
AC15 PD_D15 2HDD@ 2HDD@ SUYIN_127043FB022G208ZR_22P_RV
+3VS IORDY DD15
1

8.2K_0402_5% 2 1 R165 PD_IRQ AH16 10U_0805_10V4Z 2HDD@ 0.1U_0402_16V4Z

R150 PD_DACK# IDEIRQ 2 2HDD@ 2 2 2
AF16 DDACK#
PD_IOW# AH15 AE15 PD_DREQ
@ 0_0402_5% PD_IOR# DIOW# DDREQ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AF15 DIOR#
B B
2

ICH7_BGA652~D
ICH7R3@

ODD CONN
JP19
1 2
RTC Battery 3 4
PD_D8
1
R110
2
@ 0_0603_5%
Layout Note: 18 ODD_RST#
PD_D7
5
7
6
8 PD_D9
PD_D6 PD_D10
1. Under BATT1 battery Body, no Trace no Via +5VS PD_D5
9
11
10
12 PD_D11
PD_D4 13 14 PD_D12
2. BATT1 + - PIN keep out 80mil from other component ,trace and via PD_D3 15 16 PD_D13
PD_D2 17 18 PD_D14
1 1 1 1 PD_D1 19 20 PD_D15
C549 C159 C155 C158 PD_D0 21 22 PD_DREQ
23 24 PD_IOR#
- BATT1 + +RTCBATT
2
10U_0805_10V4Z
2 2
0.1U_0402_16V4Z
2
PD_IOW#
PD _IORDY
25
27
26
28 PD_DACK#
2 1 +RTCBATT PD_IRQ 29 30
0.1U_0402_16V4Z 0.1U_0402_16V4Z PD_A1 31 32 PDIAG# R83 1 2 +5VS
PD_A0 33 34 PD_A2 100K_0402_5%
Place components close to ODD CONN. R87 PD_CS#1 35 36 PD_CS#3
45@ RTCBATT 2 1 37 38 W=80mils
+5VS +5VS
1

100K_0402_5% +5VS 39 40 +5VS

D11 +5VS 41 42 +5VS
43 44 2 1
A BAS40-04_SOT23 A
45 46
+RTCVCC 2 1 SEC_CSEL 47 48 C156 0.1U_0402_16V4Z
R78 470_0402_5% 49 50
3

53 54

OCTEK_CDR-50JD1
+CHGRTC
1
C223
0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
2 Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 17 of 38
5 4 3 2 1
 5 4 3 2 1

+3VALW
+3VS
10K_0402_5% Place closely pin B2 Place closely pin AC1
SIRQ 2 1 R161

1
R395 R394 8.2K_0402_5% CLK_48M_ICH CLK_14M_ICH
PM_CLKRUN# 2 1 R164
2.2K_0402_5% 2.2K_0402_5% U16C

1
100K_0402_5%

2
ICH_SMBCLK C22 AF19 R145 1 2 100_0402_5% BT_DET# 1 2 R146 R224 R176
14,25 ICH_SMBCLK SMBCLK GPIO21 / SATA0GP
ICH_SMBDATA B22 AH18 R163 1 2 100_0402_5%
14,25 ICH_SMBDATA SMBDATA GPIO19 / SATA1GP

SMB
SATA
GPIO
LINKALERT# A26 AH19 R162 1 2 100_0402_5% @ 10_0402_5% @ 10_0402_5%
R226 2 ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP
1 10K_0402_5% B25 AE19 R144 1 2 100_0402_5%

2
R227 2 SMLINK0 GPIO37 / SATA3GP
+3VALW 1 10K_0402_5% ICH_SMLINK1 A25 SMLINK1
1 1
D C364 C281 D
AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH 14

Clocks
R I# A28 B2 CLK_48M_ICH @ 15P_0402_50V8J @ 15P_0402_50V8J
RI# CLK48 CLK_48M_ICH 14 2 2
SB_SPKR A19 +3VALW
23 SB_SPKR SPKR
Remove SUS_STAT# A27 C20 10K_0402_5%
DBRESET# SUS_STAT# SUSCLK LINKALERT# 2
4 DBRESET# A22 SYS_RST# 1 R225

SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# 26 +3VS
AB18 D23 SLP_S4# 10K_0402_5%
7 PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S5# DBRESET#
SLP_S5# F22 2 1 R229 RP32
OCP# B23 1 8 PCI_DEVSEL#
4 OCP# GPIO11 / SMBALERT# PWROK 7,26
AA4 PWROK 1 2 10K_0402_5% 2 7 PCI_STOP# Place closely pin A9
PWROK

POWER MGT
H_STP_PCI# AC20 R182 10K_0402_5% OCP# 2 1 R228 3 6 PCI_SERR#
14 H_STP_PCI# GPIO18 / STPPCI#

GPIO
H_STP_CPU# AF21 AC22 DPRSLPVR 4 5 PCI_TRDY#
14 H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR 7,36
2 1 8.2K_0402_5% CLK_PCI_ICH
A21 C21 R351 @ 100K_0402_5% R I# 2 1 R220 8.2K_0804_8P4R_5%
GPIO26 TP0 / BATLOW#

2
ICH_LOW_BAT# RP37
B21 C23 8.2K_0402_5% 1 8 PCI_PIRQB# R223
27 SB_INT_FLASH_SEL# GPIO27 PWRBTN# PBTN_OUT# 26
E23 ICH_LOW_BAT# 1 2 R230 2 7 PCI_PIRQA#
GPIO28 PLT_RST# PCI_PIRQC# @ 10_0402_5%
LAN_RST# C19 3 6
PM_CLKRUN# AG18 4 5 PCI_PIRQD#

1
GPIO32 / CLKRUN# 10K_0402_5% @
RSMRST# Y4 EC_RSMRST# 26
AC19 SPI_CS# 2 1 R200 8.2K_0804_8P4R_5% 1
25 MDC_RST# GPIO33 / AZ_DOCK_EN#
17 ODD_RST# U2 RP34 C365
GPIO34 / AZ_DOCK_RST# PCI_PIRQE#
1 8
F20 E20 EC_SCI# 10K_0402_5% @ 2 7 PCI_PIRQF# @15P_0402_50V8J
26 EC_SWI# WAKE# GPIO9 EC_SCI# 26 2
SIRQ AH21 A20 SPI_MOSI 2 1 R199 3 6 PCI _IRDY#
20,26,29 SIRQ SERIRQ GPIO10 ACIN 26,28,30
EC_THERM# AF20 F19 BT_DET# 4 5 PCI_PERR#
26 EC_THERM# THRM# GPIO12 BT_DET# 27
E19 EC_LID_OUT#
GPIO13 EC_LID_OUT# 26
14,26,36 VGATE VGATE AD22 R4 10K_0402_5% @ 8.2K_0804_8P4R_5%
VRMPWRGD GPIO14 SPI_MISO
GPIO15 E22 SPK_SEL_SB 26 2 1 R203 RP33
R3 2HDD_DET# 1 8 PCI_REQ3#
C GPIO24 EC_FLASH# 1K_0402_5% PCI_PIRQH# C
AC21 GPIO6 GPIO GPIO25 D20 EC_FLASH# 27 2 7
AC18 AD21 SATA_CLKREQ# EC_SWI# 2 1 R231 3 6 PCI_REQ2# +3VS
GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# 14
EC_SMI# E21 AD20 PCM_DISABLE# 21 4 5 PCI_FRAME#
26 EC_SMI# GPIO8 GPIO38
GPIO39 AE20
1K_0402_5% 100K_0402_5% 8.2K_0804_8P4R_5% R496 1 2 ICH_GPIO48
ICH7_BGA652~D 2 1 R606 2HDD_DET# 1 2 R607 RP38 8.2K_0402_5%
ICH7R3@ +3VALW 2HDD@ 1 8 PCI_PIRQG# R497 1 2 PCI_REQ4#
2 7 PCI_PLOCK# 8.2K_0402_5%
C354 2 1 FOR 2ND HDD DETECTION 1: SINGLE HDD 3 6 PCI_REQ0# R493 1 2 PCI_REQ1#
4 5 PCI_REQ5# 8.2K_0402_5%
0.1U_0402_16V4Z 0: DUAL HDD

14
U20A 8.2K_0804_8P4R_5%
SLP_S4# 1

P
A
O 3 PM_SLP_S5# 26
SLP_S5# 2 B

7G
SN74LVC08APW_TSSOP14

U16D 20 PCI_AD[0..31] U16B

F26 V26 DMI_RXN0 PCI_AD0 E18 D7 PCI_REQ0#
PERn1 DMI0RXN DMI_RXN0 7 AD0 REQ0#
F25 V25 DMI_RXP0 PCI_AD1 C18 E7
PERp1 DMI0RXP DMI_RXP0 7 AD1 GNT0#
DIRECT MEDIA INTERFACE

E28 U28 DMI_TXN0 PCI_AD2 A16 C16 PCI_REQ1#

E27
PETn1 DMI0TXN
U27 DMI_TXP0
DMI_TXN0 7
PCI_AD3 F18
AD2 PCI REQ1#
D16
PETp1 DMI0TXP DMI_TXP0 7 AD3 GNT1#
PCI_AD4 E16 C17 PCI_REQ2#
AD4 REQ2# PCI_REQ2# 20
PCIE_PTX_C_IRX_N2 H26 Y26 DMI_RXN1 PCI_AD5 A18 D17 PCI_GNT2#
25 PCIE_PTX_C_IRX_N2 PERn2 DMI1RXN DMI_RXN1 7 AD5 GNT2# PCI_GNT2# 20
KS@ PCIE_PTX_C_IRX_P2 H25 Y25 DMI_RXP1 PCI_AD6 E17 E13 PCI_REQ3#
25 PCIE_PTX_C_IRX_P2 PERp2 DMI1RXP DMI_RXP1 7 AD6 REQ3#
25 PCIE_ITX_C_PRX_N2 0.1U_0402_16V7K 2 1 C334 PCIE_ITX_PRX_N2 G28 PETn2 DMI1TXN W28 DMI_TXN1
DMI_TXN1 7
PCI_AD7 A17 AD7 GNT3# F13
25 PCIE_ITX_C_PRX_P2 0.1U_0402_16V7K 2 1 C344 PCIE_ITX_PRX_P2 G27 W27 DMI_TXP1 PCI_AD8 A15 A13 PCI_REQ4#
PETp2 DMI1TXP DMI_TXP1 7 AD8 REQ4# / GPIO22
KS@ PCI_AD9 C14 A14 ICH_GPIO48
AD9 GNT4# / GPIO48
PCI-EXPRESS

PCIE_PTX_C_IRX_N3 K26 AB26 DMI_RXN2 PCI_AD10 E14 C8 PCI_REQ5#

B 22 PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_RXN2 7 AD10 GPIO1 / REQ5# B
PCIE_PTX_C_IRX_P3 K25 AB25 DMI_RXP2 PCI_AD11 D14 D8
22 PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_RXP2 7 AD11 GPIO17 / GNT5#
22 PCIE_ITX_C_PRX_N3 0.1U_0402_16V7K 2 1 C321 PCIE_ITX_PRX_N3 J28 PETn3 DMI2TXN AA28 DMI_TXN2
DMI_TXN2 7
PCI_AD12 B12 AD12
22 PCIE_ITX_C_PRX_P3 0.1U_0402_16V7K 2 1 C329 PCIE_ITX_PRX_P3 J27 AA27 DMI_TXP2 PCI_AD13 C13 B15 PCI_CBE#0
PETp3 DMI2TXP DMI_TXP2 7 AD13 C/BE0# PCI_CBE#0 20
PCI_AD14 G15 C12 PCI_CBE#1
AD14 C/BE1# PCI_CBE#1 20
M26 AD25 DMI_RXN3 PCI_AD15 G13 D12 PCI_CBE#2
PERn4 DMI3RXN DMI_RXN3 7 AD15 C/BE2# PCI_CBE#2 20
M25 AD24 DMI_RXP3 PCI_AD16 E12 C15 PCI_CBE#3
PERp4 DMI3RXP DMI_RXP3 7 AD16 C/BE3# PCI_CBE#3 20
L28 AC28 DMI_TXN3 PCI_AD17 C11
PETn4 DMI3TXN DMI_TXN3 7 AD17
L27 AC27 DMI_TXP3 PCI_AD18 D11 A7 PCI _IRDY#
PETp4 DMI3TXP DMI_TXP3 7 AD18 IRDY# PCI_IRDY# 20
PCI_AD19 A11 E10 PCI_PAR
AD19 PAR PCI_PAR 20
P26 AE28 CLK_PCIE_ICH# PCI_AD20 A10 B18
PERn5 DMI_CLKN CLK_PCIE_ICH# 14 AD20 PCIRST# PCI_RST# 20,26,29
P25 AE27 CLK_PCIE_ICH PCI_AD21 F11 A12 PCI_DEVSEL#
PERp5 DMI_CLKP CLK_PCIE_ICH 14 AD21 DEVSEL# PCI_DEVSEL# 20
N28 PCI_AD22 F10 C9 PCI_PERR#
PETn5 AD22 PERR# PCI_PERR# 20
N27 C25 R387 24.9_0402_1% Within 500 mils PCI_AD23 E9 E11 PCI_PLOCK#
PETp5 DMI_ZCOMP DMI_IRCOMP PCI_AD24 AD23 PLOCK# PCI_SERR#
DMI_IRCOMP D25 1 2 +1.5VS D9 AD24 SERR# B10 PCI_SERR# 20
T25 PCI_AD25 B9 F15 PCI_STOP#
PERn6 AD25 STOP# PCI_STOP# 20
T24 F1 USB20_N0 PCI_AD26 A8 F14 PCI_TRDY#
PERp6 USBP0N USB20_N0 25 AD26 TRDY# PCI_TRDY# 20
R28 F2 USB20_P0 PCI_AD27 A6 F16 PCI_FRAME#
PETn6 USBP0P USB20_P0 25 AD27 FRAME# PCI_FRAME# 20
R27 G4 USB20_N1 PCI_AD28 C7
PETp6 USBP1N USB20_N1 28 AD28
G3 USB20_P1 PCI_AD29 B6 C26 PLT_RST#
USBP1P USB20_P1 28 AD29 PLTRST# PLT_RST# 7,16,22,25
R2 H1 USB20_N2 PCI_AD30 E6 A9 CLK_PCI_ICH
SPI_CLK USBP2N USB20_N2 25 AD30 PCICLK CLK_PCI_ICH 14
SPI_CS# P6 H2 USB20_P2 PCI_AD31 D6 B19
SPI_CS# USBP2P USB20_P2 25 AD31 PME#
SPI

P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 27
J3 USB20_P3
USBP3P USB20_P3 27
SPI_MOSI USB20_N4
SPI_MISO
P5
P2
SPI_MOSI USBP4N K1
K2 USB20_P4
USB20_N4 28
PCI_PIRQA# A3
Interrupt I/F G8 PCI_PIRQE#
SPI_MISO USBP4P USB20_P4 28 20 PCI_PIRQA# PIRQA# GPIO2 / PIRQE# PCI_PIRQE# 20
L4 USB20_N5 PCI_PIRQB# B4 F7 PCI_PIRQF#
USBP5N USB20_N5 25 20 PCI_PIRQB# PIRQB# GPIO3 / PIRQF# PCI_PIRQF# 20
10K_0402_5% L5 USB20_P5 PCI_PIRQC# C5 F8 PCI_PIRQG#
USBP5P USB20_P5 25 20 PCI_PIRQC# PIRQC# GPIO4 / PIRQG# PCI_PIRQG# 20
+3VALW 2 1 R610 USB_OC#0 D3 OC0# USBP6N M1 USB20_N6
USB20_N6 25 20 PCI_PIRQD#
PCI_PIRQD# B5 PIRQD# GPIO5 / PIRQH# G7 PCI_PIRQH#
PCI_PIRQH# 20
USB_OC#1 C4 M2 USB20_P6
USB_OC#2 OC1# USB USBP6P USB20_P6 25
USB_OC#3
D5
D4
OC2# USBP7N N4
N3 AE5
MISC AE9
USB_OC#4 OC3# USBP7P RSVD[1] RSVD[6]
E5 OC4# AD5 RSVD[2] RSVD[7] AG8
A USB_OC#5 R217 22.6_0402_1% A
C3 OC5# / GPIO29 AG4 RSVD[3] RSVD[8] AH8
USB_OC#6 A2 D2 USBRBIAS 1 2 AH4 F21
USB_OC#7 OC6# / GPIO30 USBRBIAS# RSVD[4] RSVD[9]
B3 OC7# / GPIO31 USBRBIAS D1 AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# 7
Within 500 mils
ICH7_BGA652~D ICH7R3@ ICH7_BGA652~D ICH7R3@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 18 of 38
5 4 3 2 1
 5 4 3 2 1

+VCCP
U16F U16E
A4 VSS[0] VSS[98] P28
+ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS +ICH_V5REF_SUS F6 L17 C257 C256 + C243 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 330U_D2E_2.5VM_R9 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
C304 + C579 C559 C574 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R147 D12 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
RB751V_SOD323 AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
220U_D2_4VM Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
+ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
C576 C561 D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C310 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VALW VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C556 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C562 G6 V28

R232 D14 Vcc1_5_B[26] Vcc3_3[5] C565 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
RB751V_SOD323 L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C286 VSS[36] VSS[133]
M22 AG12 G21 W26
2

+ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C361 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C581

C578

C362
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C580 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C260

C251
V23 A24 C577 C582 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R169 R170 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C333 C340 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C279

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C280

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C261 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS 1 2 +SATAPLL Place closely pin AG5. AD2 AC17 N6 AE24
VccSATAPLL Vcc1_5_A[20] VSS[76] VSS[173]
0.1U_0402_16V4Z

L17 N11 AE25

CHB1608U301_0603 VSS[77] VSS[174]
+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C258

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C259

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C255 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C567 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 Vcc1_5_A[17] VccSus1_05[2] C28 N26 VSS[87] VSS[184] AG11
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C347 1 2 +USBPLL C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
L30 1 J6 C363 P15 AH3
0.1U_0402_16V4Z CHB1608U301_0603 C356 Vcc1_5_A[29] VSS[93] VSS[190]
AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 0.1U_0402_16V4Z
Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3VALW W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C306
A A
ICH7R3@
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 19 of 38
5 4 3 2 1
 5 4 3 2 1

+3VS
CHB1608U301_0603 6 IN 1 LED
0.01U_0402_16V7K 1 2

L43 +5VS
1 1 1 1 1
C737 C738 C739 C740 C741
+AVDD_7412
PCI7412:6IN1 + 1394 + CardBus

1
+3VS 10U_0805_10V4Z 0.1U_0402_16V4Z
CHB1608U301_0603 2 2 2 2 2 R546
2 1 0.1U_0402_16V4Z 0.01U_0402_16V7K PCI4512:1394 + CardBus 120_0402_5%
C742 0.01U_0402_16V7K 0.1U_0402_16V4Z 7412@
L44 1 1 1 1 1 1 2 VSSPLL

2 2
C743 C744 C745 C746 C747 0.1U_0402_16V4Z
+3VS D20
D 0.1U_0402_16V4Z 10U_0805_10V4Z D
1 2
2 2 2 2 2 C748 1U_0603_10V4Z 7412@
0.1U_0402_16V4Z 0.01U_0402_16V7K HT-191NB_BLUE_0603
0.01U_0402_16V7K 1 1 1 1 2

1 1
C749 C750 C751 C752 C753

U15

U19
P13
P14

P15

K19
D

W8
1U_0603_10V4Z Q63

K1

P1
U31B 2 2 2 2 1 5IN1_LED 2
0.1U_0402_16V4Z 0.01U_0402_16V7K G

VCCP
VCCP
AVDD_33
AVDD_33
AVDD_33

VDDPLL_33
VDDPLL_15

VR_PORT
VR_PORT

2
PCI_AD[0..31] M1 PCI_AD31 7412@ S
18 PCI_AD[0..31]

3
AD31 PCI_AD30 R547 2N7002_SOT23
AD30 M2
PCI_CBE#[0..3] M3 PCI_AD29 10K_0402_5%
18 PCI_CBE#[0..3] AD29 +VCC_5IN1
M6 PCI_AD28 7412@
MC_PWRON# AD28 PCI_AD27
C8 M5

1
SM_RB MC_PWR_CTRL_0 AD27 PCI_AD26
F8 MC_PWR_CTRL_1/SM_R/B# AD26 N1
N2 PCI_AD25
AD25 PCI_AD24 7412@
AD24 N3
P3 PCI_AD23 MSBS_SDCMD_SMWE# 1 2
SD_CD# AD23 PCI_AD22 R548 100K_0402_5%
E9 SD_CD# AD22 R1
MS_CD# A8 R2 PCI_AD21 7412@
MS_CD# AD21 PCI_AD20 SMRE
B8 SM_CD# AD20 P5 1 2
R3 PCI_AD19 R549 100K_0402_5%
AD19 PCI_AD18 7412@
AD18 T1
33_0402_5% R551 T2 PCI_AD17 SDWP#_SMCE# 1 2
MSCLK_SDCLK 2 MSCLK_SDCLK_SMELWP# AD17 PCI_AD16 R550 100K_0402_5%
1 A7 MS_CLK/SD_CLK/SM_EL_WP# AD16 W4
7412@ MSBS_SDCMD_SMWE# E8 W7 PCI_AD15 7412@
MSD3_SDD3_SMD3 MS_BS/SD_CMD/SM_WE# AD15 PCI_AD14 SM_RB
B6 MS_DATA3/SD_DAT3/SM_D3 AD14 R8 1 2
7412@ R553 MSD2_SDD2_SMD2 A6 U8 PCI_AD13 R552 22K_0402_5%
SMELWP# MSD1_SDD1_SMD1 MS_DATA2/SD_DAT2/SM_D2 AD13 PCI_AD12
2 1 C7 MS_DATA1/SD_DAT1/SM_D1 AD12 V8
33_0402_5% MSD0_SDD0_SMD0 B7 W9 PCI_AD11
MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD11 PCI_AD10
AD10 V9
U9 PCI_AD9
C AD9 PCI_AD8 C
place near Chip 8412 AD8 R9
V10 PCI_AD7
SMRE AD7 PCI_AD6 CLK_PCI_PCM
A4 SD_CLK/SM_RE# AD6 U10
SDCMD_SMALE C5 R10 PCI_AD5
SD_CMD/SM_ALE AD5

1
SDD0_SMD4 C6 W11 PCI_AD4
CLK_48M_CB SDD1_SMD5 SD_DAT0/SM_D4 AD4 PCI_AD3 R554
A5 SD_DAT1/SM_D5 AD3 V11
SDD2_SMD6 B5 U11 PCI_AD2
SD_DAT2/SM_D6 AD2
1

SDD3_SMD7 E6 P11 PCI_AD1 @ 10_0402_5%

R555 SDWP#_SMCE# SD_DAT3/SM_D7 AD1 PCI_AD0
E7 R11

2
SD_WP/SM_CE# AD0
@ 10_0402_5% G5 SC_PWR_CTRL
1
C754 +3VS 6 In 1 Card Power Switch
P2 PCI_CBE#3
2

SMCLE C/BE3# PCI_CBE#2 @ 15P_0402_50V8J +VCC_5IN1

1 B4 SM_CLE C/BE2# U5
C755 XD_CD# PCI_CBE#1 2
A3 V7
XD_CD#/SM_PHYS_WP#
PCI7412 C/BE1#

2
W10 PCI_CBE#0
@ 10P_0402_50V8K C/BE0# R556 U43
2 10K_0402_5%
PAR U7 PCI_PAR 18 1 GND OUT 8
R557 1 2 1K_0402_5% P12 R6 PCI_FRAME# 18 7412@ 2 7 4.7U_0805_10V4Z
TEST0 FRAME# IN OUT
14 CLK_48M_CB F1 W5 PCI_TRDY# 18 3 6

1
R558 1 CLK_48 TRDY# IN OUT
+3VS 2 4.7K_0402_5% P17 PHY_TEST_MA IRDY# V5 PCI_IRDY# 18 MC_PWRON# 4 EN# FLG 5 1 1
V6 7412@
STOP# PCI_STOP# 18
1U_0603_10V4Z

2 U6 G528_SO8 C756 C758

DEVSEL# PCI_DEVSEL# 18
1

1
C759

R560

R561
56.2_0603_1%

56.2_0603_1%

IDSEL N5 2 R559 1 PCI_AD20 7412@ 0.1U_0402_16V4Z C757 7412@ 7412@

R562 6.34K_0402_1% 100_0402_5% 2 2
PERR# R7 PCI_PERR# 18
1 2 T18 R0 SERR# W6 PCI_SERR# 18
1 1U_0603_10V4Z
T19 R1 REQ# L3 PCI_REQ2# 18
JP20 XTPBIAS0 R13 L2 PCI_GNT2# 18
2

XTPA0+ TPBIAS0 GNT#

5 4 V14 TPA0P
XTPA0- W14 L1 CLK_PCI_PCM
6
7
3
2
XTPB0+
XTPB0-
V13
W13
TPA0N
TPB0P
PCLK
PRST# K3
K5
PCI_RST#
CLK_PCI_PCM 14
PCI_RST# 18,26,29 6 in 1 CardReader Conn.
8 1 TPB0N GRST#
220P_0402_50V7K 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

1 2 W17 L5 JP10
TPBIAS1 RI_OUT#/PME#
1

1
R563

R564

B C760 1U_0603_10V4Z R565 B

V16 TPA1P +VCC_5IN1 41 XD-VCC SD-VCC 15 +VCC_5IN1
AMP_440168-2 1K_0402_5% W16 J5 1 2 +3VS 9
R566 TPA1N SUSPEND# 43K_0402_5% MSD0_SDD0_SMD0 MS-VCC
1 2 V15 TPB1P 33 XD-D0
R567 1 2 W15 H3 MSD1_SDD1_SMD1 34 4 IN 1 CONN 16 MSCLK_SDCLK
TPB1N SPKROUT PCM_SPK 23 XD-D1 SD_CLK
1K_0402_5% CPS R12 R568 1 2 43K_0402_5% MSD2_SDD2_SMD2 35 19 MSD0_SDD0_SMD0
2

CPS PIRQA R569 2 0_0402_5% MSD3_SDD3_SMD3 XD-D2 SD-DAT0 MSD1_SDD1_SMD1

MFUNC0 G1 1 PCI_PIRQA# 18 36 XD-D3 SD-DAT1 20
X_OUT R18 H5 PIRQB R570 2 1 0_0402_5% SDD0_SMD4 37 11 MSD2_SDD2_SMD2
XO MFUNC1 PCI_PIRQB# 18 XD-D4 SD-DAT2
1
C761

1 X_IN R19 H2 PIRQC R571 2 1 0_0402_5% SDD1_SMD5 38 12 MSD3_SDD3_SMD3

XI MFUNC2 PCI_PIRQC# 18 XD-D5 SD-DAT3
R572

H1 SDD2_SMD6 39 13 MSBS_SDCMD_SMWE#
+3VS MFUNC3 SIRQ 18,26,29 XD-D6 SD-CMD
J1 PIRQD R573 2 1 0_0402_5% SDD3_SMD7 40 21 SD_CD#
MFUNC4 PCI_PIRQD# 18 XD-D7 SD-CD-SW
J2 5IN1_LED 22
2 MFUNC5 MSBS_SDCMD_SMWE# SD-CD-COM SDWP#_SMCE#
J3 2 1 +3VS 30 43
2

R575 1 MFUNC6 XD-WE SD-WP-SW

2 CPS R574 10K_0402_5% SMELWP# 31 XD-WP SD-WP-COM 44
4.7K_0402_5% G2 1 2 SDCMD_SMALE 29
SCL XD-ALE
SDA G3 1 R576 2 300_0402_5% XD_CD# 23 XD-CD MS-SCLK 8 MSCLK_SDCLK
VSSPLL

R577 300_0402_5% SM_RB MSD0_SDD0_SMD0

CLOSE TO CHIP 25 XD-R/B MS-DATA0 4
AGND
AGND
AGND

K2 SMRE 26 3 MSD1_SDD1_SMD1
VR_EN# SDWP#_SMCE# XD-RE MS-DATA1 MSD2_SDD2_SMD2
27 XD-CE MS-DATA2 5
18P_0402_50V8J C762 X_OUT SMCLE 28 7 MSD3_SDD3_SMD3
XD-CLE MS-DATA3
2

PCI7412ZHK_PBGA257 1 6 MS_CD#
R14
U13
U14

R17

MS-INS
2

C763 32 2 MSBS_SDCMD_SMWE#
X3 R578 0.1U_0402_16V4Z XD-GND MS-BS
24 XD-GND SD-GND 14
24.576MHz_16P_3XG-24576-43E1 VSSPLL 1K_0402_5% 17
2 SD-GND
42 1
1

+VCC_5IN1 N.C. MS-GND

18 N.C. MS-GND 10
18P_0402_50V8J C764 X_IN 47 SHIELD 7412@
48 SHIELD
1

R579
PIRQA R580 2 @ 1 0_0402_5% TAITW_R007-530-L3
+3VS PCI_PIRQE# 18
470_0805_5% PIRQB R581 2 @ 1 0_0402_5%
7412@ PIRQC R582 2 @ 1 0_0402_5%
PCI_PIRQF#
PCI_PIRQG#
18
18 Bottom Side, Normal Insertion
1 2

A PIRQD R583 @ 0_0402_5% A

D 2 1 PCI_PIRQH# 18
0.1U_0402_16V4Z
Q64 2 MC_PWRON#
1 G
S 2N7002_SOT23
3

7412@
C765 C766
2
4.7U_0805_10V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412/PCI/1394 CONN/CARD SLOT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3171P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 20 of 38
5 4 3 2 1
 5 4 3 2 1

CardBus Power Switch

U44 +S1_VCC 1 2
13 40mil C767 0.1U_0402_16V4Z
VCC
VCC 12
9 11 C768 0.1U_0402_16V4Z
12V VCC
1 2
+S1_VCC +3VS C769 10U_0805_10V4Z
+S1_VPP 1 2
D 0.1U_0402_16V4Z C770 0.01U_0402_16V7K D
+5VS
20mil
VPP 10 1 2
C771 1U_0603_10V4Z
0.1U_0402_16V4Z C772 5
0.1U_0402_16V4Z C773 C774 C775 C776 5V
6 5V
4.7U_0805_10V4Z C777
1 VCCD0#
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCCD0 VCCD1#
VCCD1 2
15 VPPD0
+3VS VPPD0 VPPD1
14

A15

P10
F12
F14
VPPD1

L14
J19

J14

P6
P8
F6
F9

L6
J6
U31A 0.1U_0402_16V4Z C778 3 3.3V
4 8

VCCB
VCCB

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3.3V OC

SHDN
S1_D10 C10 4.7U_0805_10V4Z C779

GND
S1_D9 CAD31/D10
A10 CAD30/D9

2
S1_D1 F11 B9 VPPD1
S1_D8 CAD29/D1 DATA/VD2/VPPD1 VCCD0# R584 TPS2211AIDBR_SSOP16
E11 A9

16
S1_D0 CAD28/D8 CLOCK/VD1/VCCD0# VPPD0 10K_0402_5%
C11 CAD27/D0 LATCH/VD3/VPPD0 C9
S1_A0 B13
S1_A1 CAD26/A0
C13

1
S1_A2 CAD25/A1 R585 0_0402_5%
A14 CAD24/A2
S1_A3 B14 2 1
CAD23/A3 PCM_DISABLE# 18
S1_A4 B15
S1_A5 CAD22/A4
E14 CAD21/A5
S1_A6 A16
S1_A25 CAD20/A6 ***
D19 CAD19/A25
S1_A7 E17 B10 S1_D2 JP8
S1_A24 CAD18/A7 RSVD/D2 VCCD1#
F15 CAD17/A24 RSVD/VD0/VCCD1# C4 GND 1
S1_A17 H19 D1 35
CAD16/A17 RSVD GND

2
S1_IOWR# J17 E1 2 S1_D3
S1_A9 CAD15/IOWR# RSVD +3VS R586 DATA3 S1_CD1#
J15 CAD14/A9 RSVD E2 CD1# 36
S1_IORD# J18 E3 43K_0402_5% 3 S1_D4
C S1_A11 CAD13/IORD# RSVD DATA4 S1_D11 C
K15 CAD12/A11 RSVD F2 DATA11 37
S1_OE# K17 F3 4 S1_D5

1
S1_CE2# CAD11/OE# RSVD R587 0_0402_5% DATA5 S1_D12
K18 CAD10/CE2# RSVD F5 DATA12 38
S1_A10 L15 G6 2 1 5 S1_D6
S1_D15 CAD9/A10 RSVD DATA6
L18 CAD8/D15 RSVD H17 S1_A18 DATA13 39 S1_D13
S1_D7 L19 M19 S1_D14 6 S1_D7
S1_D13 CAD7/D7 RSVD DATA7 S1_D14
M17 CAD6/D13 DATA14 40
S1_D6 M18 7 S1_CE1#
S1_D12 CAD5/D6 CE1# S1_D15
N19 CAD4/D12 NC A2 DATA15 41
S1_D5 M15 A17 8 S1_A10
S1_D11 CAD3/D5 NC ADD10 S1_CE2#
N17 CAD2/D11 NC A18 CE2# 42
S1_D4 N18 B1 9 S1_OE#
S1_D3 P19
CAD1/D4 NC
B2
Near to PCMCIA slot. OE#
43 S1_VS1
CAD0/D3 NC VS1# S1_A11
NC B3 ADD11 10
B17 44 S1_IORD#
S1_REG#
S1_A12
E13
E18
CC/BE3#/REG# PCI 7412 NC
NC B18
B19
+S1_VCC IORD#
ADD9 11
45
S1_A9
S1_IOWR#
S1_A8 CC/BE2#/A12 NC IOWR# S1_A8
H18 CC/BE1#/A8 NC C1 ADD8 12
S1_CE1# L17 C2 1 1 46 S1_A17
CC/BE0#/CE1# NC C780 C781 ADD17 S1_A13
NC C3 ADD13 13
S1_A13 H14 C16 47 S1_A18
S1_A23 CPAR/A13 NC 10U_0805_10V4Z 0.1U_0402_16V4Z ADD18 S1_A14
E19 CFRAME#/A23 NC C17 ADD14 14
S1_A22 2 2 S1_A19
G15 CTRDY#/A22 NC C18 ADD19 48
S1_A15 F17 C19 15 S1_WE#
S1_A20 CIRDY#/A15 NC WE# S1_A20
G18 CSTOP#/A20 NC D2 ADD20 49
S1_A21 F19 D3 16 S1_RDY#
S1_A19 CDEVSEL#/A21 NC READY S1_A21
H15 CBLOCK#/A19 NC D17 ADD21 50
S1_A14 G19 D18 17 +S1_VCC
CPERR#/A14 NC VCC +S1_VCC
S1_WAIT# C12 E5 51
S1_INPACK# CSERR#/WAIT# NC +S1_VPP VCC
C14 CREQ#/INPACK# NC N14 VPP 18
S1_WE# G17 P18 52 +S1_VPP
S1_BVD1 CGNT#/WE# NC VPP S1_A16_C +S1_VPP
A12 CSTSCHG/BVD1(STSCHG#/RI#) NC T3 ADD16 19
B R588 S1_WP S1_A22 B
A11 CCLKRUN#/WP(IOIS16#) NC T17 1 1 ADD22 53
S1_A16_C 1 2 S1_A16 F18 U1 C782 C783 20 S1_A15
33_0402_5% S1_RDY# CCLK/A16 NC ADD15 S1_A23
E12 CINT#/READY(IREQ#) NC U2 ADD23 54
U3 10U_0805_10V4Z 0.1U_0402_16V4Z 21 S1_A12
S1_RST NC 2 2 ADD12 S1_A24
C15 CRST#/RESET NC U4 ADD24 55
U12 22 S1_A7
S1_BVD2 NC ADD7 S1_A25
B12 CAUDIO/BVD2(SPKR#) NC U16 ADD25 56
U17 23 S1_A6
S1_CD1# NC ADD6 S1_VS2
N15 CCD1#/CD1# NC U18 VS2# 57
S1_CD2# B11 V1 24 S1_A5
S1_VS1 CCD2#/CD2# NC ADD5 S1_RST
A13 CVS1/VS1# NC V2 RESET 58
S1_VS2 B16 V3 25 S1_A4
CVS2/VS2# NC ADD4 S1_WAIT#
NC V4 WAIT# 59
V12 26 S1_A3
NC ADD3 S1_INPACK#
E10 A_USB_EN# NC V17 INPACK# 60
2 1 S1_CD1# V18 27 S1_A2
C784 100P_0402_50V8J NC ADD2 S1_REG#
NC V19 REG# 61
W2 28 S1_A1
NC ADD1 S1_BVD2
NC W3 BVD2 62
W12 29 S1_A0
S1_CD2# NC ADD0 S1_BVD1
2 1 W18 63
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C785 100P_0402_50V8J NC BVD1 S1_D0

DATA0 30
64 S1_D8
PCI7412ZHK_PBGA257 DATA8 S1_D1
31
F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

DATA1 S1_D9
69 GND DATA9 65
70 32 S1_D2
GND DATA2 S1_D10
DATA10 66
33 S1_WP
WP S1_CD2#
CD2# 67
GND 34
GND 68
A SANTA_130606-1_LT A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412/CB/CB SLOT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3171P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 21 of 38
5 4 3 2 1
 5 4 3 2 1

1 2 +3VALW
R33 +3VALW
3.6K_0402_5%
U5
U4
C85 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_P3 29 45 4 5 2
18 PCIE_PTX_C_IRX_P3 HSOP EEDO DO GND
47 3 6 C44 2 2 2 2
C86 EDDI/AUX DI NC
18 PCIE_PTX_C_IRX_N3 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_N3 30 HSON EESK 48 2 SK NC 7 C76 C51 C465 C63
EECS 44 1 CS VCC 8 +3VALW
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
18 PCIE_ITX_C_PRX_P3 23 HSIP AT93C46-10SI-2.7_SO8 1 1 1 1
18 PCIE_ITX_C_PRX_N3 24 HSIN
LED3 54
D D
LED2 55
26 56 LAN_LINK#
14 CLK_PCIE_LAN REFCLK_P LED1
57 LAN_ACTIVITY#
LED0
14 CLK_PCIE_LAN# 27 REFCLK_N +LAN_VDD18
20 3 LAN_MDI0+
7,16,18,25 PLT_RST# PERSTB MDIP0
4 LAN_MDI0- L12
MDIN0 LAN_MDI1+ +AVDD18
MDIP1 6 1 2
LAN_CTRL18 1 7 LAN_MDI1- BLM18AG601SN1D_0603
VCTRL18 MDIN1
2 2 2 2 2 2
LAN_CTRL15 63 9 LAN_MDI2+ C470 C474 C69 C475 C479 C93
VCTRL15 MDIP2 LAN_MDI2-
MDIN2 10
1 2 64 12 LAN_MDI3+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R285 100M@ 2K_0402_1% RSET MDIP3 LAN_MDI3- 1 1 1 1 1 1
MDIN3 13

25,26 EC_PME# 19 LANWAKEB

VDD15 15 +LAN_VDD15
VDD15 21
+3VS R300 1 2 1K_0402_1% 36 32
ISOLATEB VDD15
VDD15 33
38 +LAN_VDD15
LAN_X1 VDD15
60 CKXTAL1 VDD15 41
R301 43
LAN_X2 VDD15
61 CKXTAL2 VDD15 49
15K_0402_5% 52
VDD15
VDD15 58 2 2 2 2 2 2
62 C82 C464 C466 C52 C75 C486
GVDD
1 2 16 +3VALW 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C50 VDD33 1 1 1 1 1 1
65 EXPOSE_PAD VDD33 37
C48 53
1U_0603_10V4Z VDD33 +3VALW
0.1U_0402_16V4Z 25 EGND VDD33 46
C 2 1 L6 C
31 2 +AVDD33 1 2
EGND AVDD33 BLM18AG601SN1D_0603 +3VALW +3VALW
1 2
59 C49 C46
Y1
AVDD33 Mount for 8111B & 8100E
LAN_X1 LAN_X2 17 10U_0805_10V4Z 0.1U_0402_16V4Z
NC

3
18 5 +AVDD18 2 1
NC AVDD18
25MHZ_20P_6X25000017 35 NC AVDD18 8
1 1 34 11 LAN_CTRL18 1 Q4 LAN_CTRL15 1 Q3
C45 C47 NC AVDD18 MMJT9435T1G_SOT223 MMJT9435T1G_SOT223
39 NC AVDD18 14 40mil 40mil
40 1000M@ 1000M@
27P_0402_50V8J 27P_0402_50V8J NC
42

2
4

2
4
2 2 NC
50 NC EVDD18 22 +LAN_VDD18
51 NC
28 L13 100M@ 40mil L11 100M@ 40mil
EVDD18
1 2 +LAN_VDD18 1 2 +LAN_VDD15
1 BLM18AG601SN1D_0603 1 2 1 BLM18AG601SN1D_0603 1 2
RTL8111B_QFN64 1000M@ C100 C106 C71 C72
C102 C61
Mount for 8101E 10U_0805_10V4Z 22U_0805_6.3V6M 0.1U_0402_16V4Z 10U_0805_10V4Z 22U_0805_6.3V6M 0.1U_0402_16V4Z
100M@ 2 2 1 100M@ 2 2 1
Place Close to Chip
100M@
+LAN_VDD18 100M@ R15 2 1 49.9_0402_1% LAN_MDI0-
Mount for 8101E Mount for 8101E
C30 2 1 R14 2 1 49.9_0402_1% LAN_MDI0+
R678 0_0402_5%
0.01U_0402_16V7K 100M@
L45
100M@ 4 3
4 3
1

100M@ R17 2 1 49.9_0402_1% LAN_MDI1- RJ45_MIDI3- RJ45_MIDI3-_L

100M@ 100M@ C31 2 1 R16 2 1 49.9_0402_1% LAN_MDI1+ RJ45_MIDI3+ RJ45_MIDI3+_L
B R11 R10 B
1 2
0_0402_5% 0_0402_5% 0.01U_0402_16V7K 100M@
1 2
@ WCM2012F2S-900T04_0805
LAN Conn.
Place Close to Chip
2

R679 0_0402_5%
JP11
R680 0_0402_5% 12
+3VALW Amber LED+
U30 L46 LAN_ACTIVITY# 2 1 300_0402_5% 11
R256 Amber LED-
4 4 3 3 1 SHLD2 16
1 24 RJ45_MIDI2- RJ45_MIDI2-_L RJ45_MIDI3-_L 8
LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- RJ45_MIDI2+ RJ45_MIDI2+_L 68P_0402_50V8K C696 PR4-
2 TD1+ MX1+ 23 SHLD1 15
LAN_MDI3+ 3 22 RJ45_MIDI3+ 1 2 RJ45_MIDI3+_L 7
TD1- MX1- 1 2 2 PR4+
4 21 @ WCM2012F2S-900T04_0805 RJ45_MIDI1-_L 6
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- R681 0_0402_5% PR2-
5 TD2+ MX2+ 20
LAN_MDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI2-_L 5
TD2- MX2- R682 0_0402_5% PR3-
7 18 RJ45_MIDI2+_L 4
LAN_MDI1- TCT3 MCT3 RJ45_MIDI1- L47 PR3+
8 TD3+ MX3+ 17
LAN_MDI1+ 9 16 RJ45_MIDI1+ 4 3 RJ45_MIDI1+_L 3
TD3- MX3- RJ45_MIDI1- 4 3 RJ45_MIDI1-_L PR2+
10 15 RJ45_MIDI1+ RJ45_MIDI1+_L 2 RJ45_MIDI0-_L 2
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- PR1-
11 TD4+ MX4+ 14 1 1 2 2 SHLD2 14
LAN_MDI0+ 12 13 RJ45_MIDI0+ 68P_0402_50V8K C697 RJ45_MIDI0+_L 1
TD4- MX4- @ WCM2012F2S-900T04_0805 PR1+
SHLD1 13
R683 0_0402_5% LAN_LINK# 1
2 1 10 Green LED-
1

1 1 R257 300_0402_5%
NS892402 R261 R260 R684 0_0402_5% 9
C28 C26 1000M@ +3VALW Green LED+
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1% L48 C3 TYCO_3-440470-4
1

2 2 RJ45_GND LANGND
1 1 4 3 1 2
2

R259 R258 RJ45_MIDI0- 4 3 RJ45_MIDI0-_L 1 1

A C25 C27 RJ45_MIDI0+ RJ45_MIDI0+_L 1000P_1206_2KV7K C4 C5 A
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1% 1 2
2 2 1 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2

RJ45_GND @ WCM2012F2S-900T04_0805 2 2
R685 0_0402_5%

Place these components

colsed to LAN chip
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
GST5009 for GIGA LAN Issued Date 2006/10/03 Deciphered Date 2009/10/03
RTL8111B/8101E 10/100/1000 LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TST1284 for 10/100 LAN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
CustomIAKAA M/B LA-3401P
Rev
0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 22 of 38
5 4 3 2 1
 A B C D E F G H

HD Audio Codec
+AVDD_AC97 +3VS_DVDD +VDDA
L34
L24 1 2 0.1U_0402_16V4Z 680P_0402_50V7K 40mil 0.1U_0402_16V4Z 10U_0805_10V4Z 680P_0402_50V7K 1 2
+VDDA +3VS

1
FBM-L11-160808-800LMT_0603 1 1 1 1
C386 C382 C669 C700 1 FBM-L11-160808-800LMT_0603 R245
C391 20mil 1
C374
1
C373
1
C370 C606
C699 C607 10K_0402_5%
10U_0805_10V4Z
2 2 2 2

2
0.1U_0402_16V4Z 100P_0402_50V8J 2 2 2 2
100P_0402_50V8J 1 2
1 0.1U_0402_16V4Z 680P_0402_50V7K C377 1U_0402_6.3V4Z 1

1
25

38
@

9
U38 R239
10K_0402_5%
1 1
EC Beep

AVDD1

AVDD2

DVDD1

DVDD2
C388 C389
AMP_LHPIN 861_HP_L C367 1 R236
1 2 26 BEEP# 2 1 2

2
C811 2.2U_0603_6.3V6K 10P_0402_50V8J 10P_0402_50V8J 1U_0402_6.3V4Z 560_0402_5% C371
AMP_RHPIN 861_HP_R AMP_LEFT 2 2 MONO_IN
1 2 14 LINE2_L FRONT_OUT_L 35 AMP_LEFT 24 1 2
C812 2.2U_0603_6.3V6K
1 2 15 36 AMP_RIGHT 1U_0402_6.3V4Z
LINE2_R FRONT_OUT_R AMP_RIGHT 24 PCI Beep

1
C735 100P_0402_50V8J C 1 2
INT_MIC MIC2_L 268_HP_L AMP_LHPIN C375 1 R240 Q23
+MIC2_VREFO 1 2 1 2 16 MIC2_L SURR_OUT_L 39 1 2 AMP_LHPIN 24 18 SB_SPKR 2 1 2 1 2 2 R238
R545 4.7K_0402_5% MIC@ C729 1U_0402_6.3V4Z @ C793 2.2U_0603_6.3V6K 1U_0402_6.3V4Z 560_0402_5% B MMBT3904_SOT23 2.4K_0402_5%
MIC1 MIC@ 1 2 MIC2_R 17 41 268_HP_R 1 2 AMP_RHPIN R618 E
AMP_RHPIN 24

3
MIC@ C730 1U_0402_6.3V4Z MIC2_R SURR_OUT_R @ C792 2.2U_0603_6.3V6K 0_0402_5%
1
2 2 1 1 2 23 45
C731 MIC@ C736 100P_0402_50V8J LINE1_L SIDESURR_OUT_L CardBus Beep R235
WM-64PCY_2P 220P_0402_50V7K 1 2 24 46 C369 1 2 1 2
45MIC@ C702 1U_0402_6.3V4Z LINE1_R SIDESURR_OUT_R 20 PCM_SPK 1U_0402_6.3V4Z 560_0402_5%

1
1 2 18 43 2 D17
C703 100P_0402_50V8J CD_L CEN_OUT
20 44 C368 R241
CD_R LFE_OUT 10K_0402_5% RB751V_SOD323
0.01U_0402_16V7K
1
1 2 100P_0402_50V8J 19 1 2 ICH_BITCLK_AUDIO 17

2
C704 CD_GND R544 22_0402_5%
BIT_CLK 6
MIC1_L 1 2 1U_0402_6.3V4Z MIC1_C_L 21 2 R418 1 C591 1 2
24 MIC1_L MIC1_L

1
C379 @ 10_0402_5% @ 10P_0402_50V8J D
MIC1_R 1 2 1U_0402_6.3V4Z MIC1_C_R 22 8 1 2 ICH_AC_SDIN0 17 2
24 MIC1_R MIC1_R SDATA_IN 26 NSE_DPR
C381 R237 33_0402_5% G
1 2 100P_0402_50V8J MONO_IN 12 37 Q61 S

3
C705 PCBEEP NC 2N7002_SOT23
1 2 100P_0402_50V8J NC 29
2 C706 2
17 ICH_RST_AUDIO# 11 RESET#

1
31 R528 C
LINE2_VREFO Q62
17 ICH_SYNC_AUDIO 10 SYNC +S1_VCC 2
B
5
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
2.2K_0402_5% E
MMBT3904_SOT23
17 ICH_SDOUT_AUDIO

3
SDATA_OUT
SPK_SEL HIGH: HARMAN 2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
26 SPK_SEL_CODEC GPIO0
LOW: NO-BRAND SENSE_A
3 GPIO1 MIC2_VREFO 30 10mil +MIC2_VREFO
SENSE_B
13
34
SENSE A
27 ACZ_VREF 10mil 10U_0805_10V4Z
SENSE B VREF
1 1 100P_0402_50V8J
47 40 ACZ_JDREF 20K_0402_1% C390
24,26 EAPD EAPD JDREF C707

1
48 SPDIFO NC 33 1
C708 2 2
4 26 R246
DVSS1 AVSS1 100P_0402_50V8J
7 DVSS2 AVSS2 42
2

2
ALC861-GR REV D_LQFP48

DGND AGND Change R246 from 5.1Kto 20K_0402_1%

24 MIC_SENSE
R498
1 2
20K_0402_1%
SENSE_A Regulator for CODEC
24,26 NBA_PLUG 2 1 SENSE_B Adjustable Output
R620 39.2K_0402_1% +5VALW +5VALW_VDDA +VDDA
2 1 SENSE_A U29
3 R253 39.2K_0402_1% L37 1 +VDDA 3
2 4 VIN VOUT 5

4.7U_0805_10V4Z

0.1U_0402_16V4Z
@ FBM-L11-160808-800LMT_0603

4.7U_0805_10V4Z
2 DELAY SENSE or ADJ 6
R412

0.1U_0402_16V4Z
1 2 SENSE_B 7 1 69.8K_0603_1%
R673 MIC@ 20K_0402_1% C584 C585 ERROR CNOISE
Sense Pin Impedance Codec Signals 8 3

1
SD GND

39.2K PORT-A (PIN 39, 41) SI9182DH-AD_MSOP8

1
20K PORT-B (PIN 21, 22) R408

C588
SENSE A 24K _0402_1%
26,28,34 SYSON 2 1

C586
10K PORT-C (PIN 23, 24) R406 0_0402_5%

2
16,26,27,29,34,35 SUSP# 2 1
R409 @ 0_0402_5%
5.1K PORT-D (PIN 35, 36)

39.2K PORT-E (PIN 14, 15)

SENSE B
20K PORT-F (PIN 16, 17) Moat Bridge
10K PORT-G (PIN 43, 44) 1
R247
2
0_0805_5%
1 2
5.1K PORT-H (PIN 45, 46) R243 0_0805_5%
1 2
R244 0_0805_5%
4 4
1 2
R242 0_0805_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC861VD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 23 of 38
A B C D E F G H
 A B C D E

APA2056 SPK/HP Amplifier

+5VS +MIC1_VREFO_L +MIC1_VREFO_R
W=40mil MICROPHONE
10mil 10mil IN JACK

1
680P_0402_50V7K

0.1U_0402_16V4Z

1U_0402_6.3V4Z

10U_0805_10V4Z
1 2 1
C724 C677 C678 C679 R248 R249
JP29
4.7K_0402_5% 4.7K_0402_5% 5

2
2 1 2

23 MIC_SENSE 4
8
MIC1_R L21 MIC1_R_1

11

19

20
10
23 MIC1_R 1 2 3

1
1 U47 KC FBM-L11-160808-121LMT 0603 1
6
MIC1_L 1 2 L20 MIC1_L_1 2 7

CVDD

HVDD

PVDD
PVDD

VDD
23 MIC1_L
KC FBM-L11-160808-121LMT 0603 1

2
220P_0402_50V7K

220P_0402_50V7K
1 1

SM05_SOT23
23 AMP_RIGHT 1 2 AMPR FOX_JA6033L-5S1-TR
C790 0.22U_0402_6.3V6K 3 22 INTSPK_R1 C392 C393 @ AGND
INR_A ROUT+

1
23 AMP_LEFT 1 2 AMPL 5 INL_A ROUT- 21 INTSPK_R2
C791 0.22U_0402_6.3V6K 2 2 PJ16 PJ17

1
R589 1 2 100K_0402_5% AMP_EN#27 8 INTSPK_L1 JUMP_43X39 JUMP_43X39

1
/AMP EN LOUT+ INTSPK_L2 D38
LOUT- 9 @ @

2
+5VS R590 1 2 100K_0402_5% HP_EN 24 HP EN HP_R
17

2
AMP_RHPIN INR _H HP_R HP_L
23 AMP_RHPIN 1 R603 2 4 INR_H HP_L 18
AMP_LHPIN 24K_0402_5% 1 R602 2 6 INL_H
23 AMP_LHPIN INL_H
24K_0402_5%
+5VS R591 1 2 100K_0402_5% AMP_SD# 26
/SD CVSS
CVSS 15
1 2 AMP_BEEP 28 BEEP
C819 1U_0402_6.3V4Z 16
AMP_CP+ VSS
12 CP+
1 2 AMP_CP- 14 2 1
2.2U_0603_6.3V6K C804 CP- GND
PGND 23
2 1 AMP_BIAS 25 7 C796 HEADPHONE
C797 2.2U_0603_6.3V6K BIAS PGND
13 2.2U_0603_6.3V6K
2 1
CGND 2 OUT JACK
C801 0.1U_0402_16V4Z JP28
APA2056_TSSOP28 5

4
IN_A Gain = 10dB (Internal Speaker) R676 20_0402_5%
23,26 NBA_PLUG
8
HP_R L22 1 2 1 2 HPR 3
2 R619 1 HP_EN IN_H Gain = 0dB (Headphone) KC FBM-L11-160808-121LMT 0603 6
2 @ 0_0402_5% HP_L L23 1 HPL 2
1 2 1 2 20_0402_5% 2 7
KC FBM-L11-160808-121LMT 0603 1

10P_0402_50V8J

10P_0402_50V8J
C818 R677 1 1
1

2
D R597 R598 FOX_JA6033L-5S1-TR
0.1U_0402_16V4Z
2 0_0402_5% 0_0402_5% D39 AGND
2 @
G @ @ C399 C395 @
Q67 S 2 2
3

2
2N7002_SOT23 SM05_SOT23
Reserve for Test

1
26 EC_EAPD 2 R592 1 AMP_SD#
@ 0_0402_5% 1
C814
Right Speaker Connector SM05_SOT23 D5
2
0.1U_0402_16V4Z 1
2
@ 3
@ JP2
INTSPK_R1 L7 1 2 HLMA-160808-39NKT SPK_R1
INTSPK_R2 L10 1 HLMA-160808-39NKT SPK_R2 1
2 2
ACES_85204-0200

Left Speaker Connector JP34

INTSPK_L1 L8 1 2 HLMA-160808-39NKT SPK_L1
INTSPK_L2 L9 1 HLMA-160808-39NKT SPK_L2 1
2 2
3 ACES_85204-0200
1
3 3
2
@
SM05_SOT23 D4

Volume Control
+3VS

+3VS

1
R593
100K_0402_5%

1
0.1U_0402_16V4Z
R305 R255 +3VS 1 2

2
SW6 5 10K_0402_5% 10K_0402_5% C787 +3VS
1
DIP

1
0.1U_0402_16V4Z

2
C798

NC
A 2 1 2 2 A Y 4
R251 10K_0402_5% 2

G
74LVC1G14GW_SOT353-5 U45
1 U46 1 14

3
COM CD1# VCC
2 D1 CD2# 13
3 CP1 D2 12
3 1 2 4 11 C789
B SD1# CP2

0.1U_0402_16V4Z
R250 10K_0402_5% 5 10
Q1 SD2#
1 1 6 Q1# Q2 09 1

0.01U_0402_16V7K

0.01U_0402_16V7K
DIP

C788 C786 7 08
GND Q2#
SW_XRE094_3P 74LCX74MTC_TSSOP14
4

4 2 2 2 4

ENCODER_DIR 26
ENCODER_PULSE 26

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
AMP/VR/Audio Jack/MIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 24 of 38
A B C D E
Finger printer +3VS CIR
USB Board
1
C725

0.1U_0402_16V4Z ACES_85201-1205
2 JP32
1
+5VALW 1.4A +USB_VCCC
18 USB20_P2
12
11
U42 18 USB20_N2
2 C726 U41 10
18 USB20_N6 3 1 1 GND OUT 8 9
18 USB20_P6 4 1 GND 2 IN OUT 7 18 USB20_P0 8
4.7U_0805_10V4Z CIR@ 3 6 18 USB20_N0
5 IN OUT 7
2 GND 26,28 USB_EN# 4 EN# FLG 5 6

2
ACES_85201-0505 100_0805_5% CIR@ R540 2
1 1 5
D40 FP@ +5VALW 2 1 +5VALW_CIR 3 C727 G528_SO8 C728
@ SM05_SOT23 VCC 4
4.7U_0805_10V4Z 4.7U_0805_10V4Z 3
26 CIR_IN 4 ROUT 2
2 2
1 TSOP6238TR_4P Close to JP21 +USB_VCCC 1
CIR@ JP33

Mini-Express Card
+3VS +1.5VS
+3VALW KS@ ***
+3VS +1.5VS R422 0_0402_5% JP24
22,26 EC_PME# 2 1 MINI_WAKE# 1 1 2 2
27 WLAN_BT_DATA 3 3 4 4
27 WLAN_BT_CLK 5 5 6 6
1 1 1 1 1 1 1 14 MINI_CLKREQ# MINI_CLKREQ# 7 8
C262 C575 C327 C326 C572 C275 7 8
9 9 10 10
C570 CLK_PCIE_MCARD# 11 12
14 CLK_PCIE_MCARD# 11 12
0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z CLK_PCIE_MCARD 13 14
2 2 2 2 2 2 2 14 CLK_PCIE_MCARD 13 14
KS@ 15 16
15 16
17 17 18 18
KS@ KS@ KS@ KS@ KS@ KS@ 19 20 XMIT_OFF#
19 20 PLT_RST#
21 21 22 22 PLT_RST# 7,16,18,22
18 PCIE_PTX_C_IRX_N2 23 23 24 24 +3VALW
18 PCIE_PTX_C_IRX_P2 25 25 26 26
27 27 28 28 +1.5VS
29 29 30 30 ICH_SMBCLK 14,18
18 PCIE_ITX_C_PRX_N2 31 31 32 32 ICH_SMBDATA 14,18
+3VALW 18 PCIE_ITX_C_PRX_P2 33 33 34 34
35 36 USB20_5N R687 0_0402_5%
35 36 USB20_5P
37 37 38 38
39 39 40 40
@ WCM2012F2S-900T04_0805
14

41 41 42 42
U20D 43 44 1 2
D33 43 44 1 2 USB20_N5 18
WL_OFF# 12 45 46
P

26 WL_OFF# A 45 46
O 11 1 2 XMIT_OFF# 47 47 48 48 +1.5VS
KILL_SW# 13 RB751V_SOD323 KS@ 49 50 4 3
26,28 KILL_SW# B 49 50 4 3 USB20_P5 18
G

51 51 52 52 +3VS
SN74LVC08APW_TSSOP14 L49
7

53 GND1 GND2 54
R686 0_0402_5%

FOX_AS0B226-S40N-7F~D
KS@
Place close to pci-e connector

+3VALW

MDC 1.5 Conn.

1 1 1
+3VALW C314 C315 C313
JP25 TYCO_1-1775149-2~D +3VALW
1000P_0402_50V7K @ 4.7U_0805_10V4Z
2 2 2
14

1 GND1 RES0 2
U20B 17 ACZ_SDOUT_MDC ACZ_SDOUT_MDC 3 4 0.1U_0402_16V4Z
IAC_SDATA_OUT RES1
4 5 6
P

18 MDC_RST# A GND2 3.3V

6 MDC_RESET# 17 ACZ_SYNC_MDC ACZ_SYNC_MDC 7 8
ACZ_RST#_MDC O R209 1 ACZ_SDIN1_MDC IAC_SYNC GND3
17 ACZ_RST#_MDC 5 B 17 ACZ_SDIN1 2 9 IAC_SDATA_IN GND4 10
G

33_0402_5% MDC_RESET# 11 12 ACZ_BITCLK_MDC ACZ_BITCLK_MDC 17

SN74LVC08APW_TSSOP14 IAC_RESET# IAC_BITCLK
R419
7

2 1 1 2

GND
GND
GND
GND
GND
GND
10_0402_5% C592 22P_0402_50V8J

13
14
15
16
17
18
Connector for MDC Rev1.5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP/CIR/USB-B/MDC/Mini_Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 25 of 38
 5 4 3 2 1

+3VALW

KBA[0..19] KSI[0..7]
KBA[0..19] 27
R157 Change to 0 ohm
KSI[0..7] 28 For EC Tools
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 +3VALW KSO[0..15] JP23
ADB[0..7] 27 KSO[0..15] 28
1 1 C322 1 1 2 2 0_0603_5%
1 1 +5VALW
C320 1 2 E51_RXD
C303 C241 C263 C299 2 E51_TXD
3 3
1000P_0402_50V7K 1000P_0402_50V7K C254 1 1 4
L16 2 2 2 2 1 1 C323 C343 4

ECA GND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z @ ACES_85205-0400
1 2
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2
D D

123
136
157
166

161

159
16
34
45

95

96
U13 RSMRST circuit
LPC_AD0 15 R670

VCCA
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AGND

BATGND
VCCBAT
17,29 LPC_AD0 LAD0
C291 LPC_AD1 14 49 KSO0
17,29 LPC_AD1 LAD1 GPOK0/KSO0
@ 22P_0402_50V8J @ 33_0402_5% LPC_AD2 13 50 KSO1 0_0402_5%
17,29 LPC_AD2 LAD2 GPOK1/KSO1
2 1 R179 2 1 LPC_AD3 10 51 KSO2 1 2
17,29 LPC_AD3 LAD3 GPOK2/KSO2 KSO3
17,29 LPC_FRAME# 9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4 Q46
18,20,29 PCI_RST# 165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
KSO5 RSMRST#

C
14 CLK_PCI_EC 18 LCLK GPOK5/KSO5 56 3 1 EC_RSMRST# 18
KSO6

E
18,20,29 SIRQ 7 SERIRQ GPOK6/KSO6 57
+3VALW 25 58 KSO7 BAV99DW-7_SOT363 @ MMBT3906_SOT23
RP29 CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8

B
24 59

1 2
MODE# LPCPD#/GPIO0B * GPOK8/KSO8 KSO9
1 8 GPOK9/KSO9 60

2
2 7 F RD# F RD# 150 61 KSO10
27 FREAD# RD# GPOK10/KSO10
SELIO# F W R# KSO11 R671 D47B D47A

Internal Keyboard
3 6 27 FW R# 151 WR# GPOK11/KSO11 64
4 5 FSEL# FSEL# 173 65 KSO12 @ 2.2K_0402_5% @ @ BAV99DW-7_SOT363
27 FSEL# MEMCS# GPOK12/KSO12
SELIO# 152 66 KSO13
10K_0804_8P4R_5% ADB0 IOCS# GPOK13/KSO13 KSO14
138 67

1
ADB1 D0 GPOK14/KSO14 KSO15
139 68 R672

6
ADB2 D1 GPOK15/KSO15
140 D2 GPOK16/KSO16 153 1 2
ADB3 141 154 KSO17
+3VALW D3 GPOK17/KSO17 KSO17 28
ADB4 144 @ 2.2K_0402_5%
ADB5 D4 KSI0
145 D5 GPIK0/KSI0 71

X-BUS Interface
2 1 KBA1 ADB6 146 72 KSI1
@ 10K_0402_5% R185 ADB7 D6 GPIK1/KSI1 KSI2
147 D7 GPIK2/KSI2 73
2 1 KBA4 KBA0 124 74 KSI3
10K_0402_5% R187 KBA1 A0 GPIK3/KSI3 KSI4
125 A1/XIOP_TP GPIK4/KSI4 77
2 1 KBA5 KBA2 126 78 KSI5
10K_0402_5% R194 KBA3 A2 GPIK5/KSI5 KSI6 +3VALW
127 A3 GPIK6/KSI6 79
KBA4 128 80 KSI7
+3VALW KBA5 A4/DMRP_TP GPIK7/KSI7
131 A5/EMWB_TP
C KBA6 132 32 C
A6 GPOW0/PWM0 INVT_PWM 16

2
1 2 IE_BTN# KBA7 133 33
A7 GPOW1/PWM1 BEEP# 23
R172 10K_0402_5% KBA8 143 36 R173
A8 FAN2PWM/GPOW2/PWM2 PWR_SUSP_LED 28
1 2 EC_SMI# KBA9 142 37 100K_0402_5%
A9 GPOW3/PWM3 ACOFF 32
R140 10K_0402_5% KBA10 135 Pulse Width GPOW4/PWM4 38
A10 USB_EN# 25,28
1 2 EC_PME# KBA11 134 39 EC_ON 28

1
R420 10K_0402_5% KBA12 A11 GPOW5/PWM5
130 A12 GPOW6/PWM6 40 EC_LID_OUT# 18
KBA13 129 43 EC_EAPD
A13 FAN1PWM/GPOW7/PWM7 EC_EAPD 24
KBA14 121 D13
KBA15 A14
120 A15 GPWU0 2 ON/OFFBTN# 28
+5VS KBA16 113 26 2 1
A16 GPWU1 ACIN 18,28,30
RP27 KBA17 112 29 KILL_SW#
A17 GPWU2 KILL_SW# 25,28
1 8 KB_CLK KBA18 104 30 PM_SLP_S3#
A18 GPWU3 PM_SLP_S3# 18 RB751V_SOD323
2 7 KB_DATA KBA19 103 Wake Up Pin 44 PM_SLP_S5#
28 IE_BTN# A19 GPWU4 PM_SLP_S5# 18
3 6 PS_CLK IE_BTN# 108 76
A20/GPIO23 GPWU5 CIR_IN 25
4 5 PS_DATA +3VALW 2 1 EC_TINIT# 105 172 EC_PME#
E51CS#/GPIO20/ISPEN TIN1/GPWU6 EC_PME# 22,25
R171 @ 10K_0402_5% 176
TIN2/FANFB2/GPWU7 ENCODER_PULSE 24
4.7K_0804_8P4R_5% KB_CLK 110 2 1 ECAGND
+5VS KB_DATA PSCLK1 C240 0.01U_0402_16V7K
111 PSDAT1 GPIAD0/AD0 81 BATT_TEMPA 31
PS_CLK 114 82 BUTTON_ID
PSCLK2 GPIAD1/AD1 BUTTON_ID 28
2 1 TP_CLK PS_DATA 115 PSDAT2PS2 Interface GPIAD2/AD2 83 BATT_OVP 32
R360 4.7K_0402_5% TP_CLK 116 84
27 TP_CLK PSCLK3 GPIAD3/AD3
2 1 TP_DATA 27 TP_DATA
TP_DATA 117 PSDAT3 Analog To Digital GPIAD4/AD4 87 ALI/MH# 31,32
R362 4.7K_0402_5% 88 SKU_ID
EC_SMB_CK1 GPIAD5/AD5 AD_BID0
27,31 EC_SMB_CK1 163 SCL1 GPIAD6/AD6 89
+5VALW EC_SMB_DA1 164 90 1 2
27,31 EC_SMB_DA1 SDA1 GPIAD7/AD7 100K_0402_5% ADP_I 32
RP28 EC_SMB_CK2 169 SMBus R344
4,16 EC_SMB_CK2 SCL2
1 8 EC_SMB_CK1 EC_SMB_DA2 170 99 DAC_BRIG 1 2
4,16 EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG 16
2 7 EC_SMB_DA1 100 BT_PWR C248 0.22U_0603_10V7K
GPODA1/DA1 BT_PWR 27
3 6 EC_SMB_CK2 8 101 IR EF
GPIO04 GPODA2/DA2 IREF 32
4 5 EC_SMB_DA2 EC_SCI# 20 102 EN_DFAN1 EN_DFAN1
18 EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 4
BT_RST# 21 Digital To Analog 1
27 BT_RST# GPIO08 GPODA4/DA4 PWROK 7,18

2
4.7K_0804_8P4R_5% 22 42
B ENBKL GPIO09 GPODA5/DA5 R512 B
27 GPIO0D GPODA6/DA6 47
PM@ BKOFF# 28 174 1M_0402_5%
16 BKOFF# GPIO0E GPODA7/DA7
R151 1 2 0_0402_5% FSTCHG 48
16 VGA_ENBKL 32 FSTCHG GPIO10
EC_SMI# 62 85 POWER_LED#
18 EC_SMI# POWER_LED# 28

1
GM@ GPIO13 * GPIO18/XIO8CS# WL_BT_LED#
24 ENCODER_DIR 63 GPIO14 86 WL_BT_LED# 28
R167 1 2 0_0402_5% ENBKL 69 * GPIO19/XIO9CS# 91 HDD_LED#
9 GMCH_ENBKL 25 WL_OFF# GPIO15 *GPIO1A/XIOACS# HDD_LED# 28
70 GPIO 92 BATT_CHG_LOW_LED#
18 EC_SWI# GPIO16 * GPIO1B/XIOBCS# BATT_CHG_LOW_LED# 28
1 2 75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_FULL_LED#
23,24 NBA_PLUG GPIO17 BATT_FULL_LED# 28
R286 2.2K_0402_5% 109 94
23,24 EAPD GPIO24 * GPIO1D/XIODCS# VGATE 14,18,36
118 97 R527
28 LID_SW# GPIO25 * GPIO1E/XIOECS# NSE_DPR 23
MODE# 119 98 CB_PW R_OK 2 1 +S1_VCC
28 MODE# GPIO26 * GPIO1F/XIOFCS#
S YSON 148 10K_0402_5%
23,28,34 SYSON GPIO27
1 2 S YSON 16,23,27,29,34,35 SUSP#
SUSP# 149 GPIO28 GPIO2E/TOUT1/FANFB1 171 FAN_SPEED1 4
R375 100K_0402_5% 155 12 R365 1 2 4.7K_0402_5%
36 VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
1 2 SUSP# 156 GPIO2A FANTEST_TP/GPIO05/FAN3PWM 11 SPK_SELR368 1 2 4.7K_0402_5%
R374 100K_0402_5% BT_DETACH 162 R604 1 2 0_0402_5%
27 BT_DETACH GPIO2B SPK_SEL_CODEC 23
168 175 R605 1 2@ 0_0402_5% CRY1 1 R204 2 CRY2
18 PBTN_OUT# GPIO2D SPK_SEL_SB 18
Timer PinTOUT2/GPIO2F EC_THERM# 18
@ 20M_0603_5%
PADS_LED# 55 3 RSMRST#
28 PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00
C284 0.1U_0402_16V4Z CAPS_LED# 54 4
28 CAPS_LED# CapLock#/GPIO011 * E51IT1/GPIO01
2 1 NUM_LED# 23 106 E51_RXD
28 NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK E51_RXD 29
41 107 E51_TXD 1 C332 1 C324
17 PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT E51_TXD 29
+3VALW 2 1 19 ECRST# MISC 1 2

4
10P_0402_50V8J

10P_0402_50V8J
R177 47K_0402_5% 5 158 CRY2 R181 100K_0402_5%
17 GATEA20 GA20/GPIO02 XCLKI
6 160 CRY1 X2

IN

OUT
17 EC_KBRST# KBRST#/GPIO03 XCLKO 2 2
31
GND
GND
GND
GND
GND
GND

ECSCI#

KB910Q B4_LQFP176

NC

NC
17
35
46
122
137
167

3
SKU_ID 0:10(10E) 4:10J(10EJ) +3VALW
A 1:10C 5:10CJ A

2:10G 6:10GJ SKU_ID 2 1

R343 100K_0402_5% 32.768KHZ_12.5P_1TJS125BJ2A251
3:10GC 7:10GCJ 1 2
R342 GM@ 0_0402_5%
BUTTON_ID ID0:0 BUTTON
BUTTON_ID 2 1
ID2:2 BUTTON R340 100K_0402_5%
ID4:6 BUTTON
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
AD_BID0: Board ID AD_BID0 2
R141
1
100K_0402_5% ENE-KB910
ID = 1 (PCB REV 0.2) 1
Ra 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
R142 8.2K_0402_5% 0.3
* Rb DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 26 of 38
5 4 3 2 1
 5 4 3 2 1

TP CONN. +5VS
BlueTooth Interface
C130 ACES_85201-0605
0.1U_0402_16V4Z
1
SWR 2
SWL 3
4
26 TP_DATA 5 +5VS +3VS
26 TP_CLK 6

3
JP5

68P_0402_50V8K

68P_0402_50V8K

SM05_SOT23

2
2 2 D41
D C526 C527 R112 C225 D

@ 1M_0402_5% 0.1U_0402_16V4Z
BT@ BT@

3
1 1
S
R433

1
G
1 3 1 3 1 2 2
!!Confirm Pin BT@ 100K_0402_5% Q15
BT@AO3413_SOT23
2 4 2 4 2
D

1
SW4 SW5 Direction C218 1000P_0402_50V7K

6
5

6
5
SMT1-05_4P SMT1-05_4P BT@
+BT_VCC

1
D 1
Left Right 26 BT_PWR 2
G 2N7002_SOT23
S Q14

3
BT@

BT@
MARU_00-6210-320-340-800_20P
Module ID
Indication for polarity of reset 20
Reset input High Active --> Low , BT_DET# 19
18 BT_DET# 18
Reset input Low Active --> Open
17
16
15
BT_RST# 14
26 BT_RST# 13
12
11
C 10 C
9
26 BT_DETACH 8
25 WLAN_BT_CLK 7
6
18 USB20_P3 5
18 USB20_N3 4
25 WLAN_BT_DATA 3
1 1 2
+BT_VCC 1
C670 C671
22P_0402_50V8J 22P_0402_50V8J (MAX=200mA)
1
BT@ 2 2
BT@ C216 C215 JP7
BT@ BT@ (Top Contact)
10U_0805_10V4Z 0.1U_0402_16V4Z
2
Bluetooth Connector

KBA[0..19]
26 KBA[0..19]
ADB[0..7]
26 ADB[0..7]

1MBU22Flash ROM +3VALW

KBA0 21 31
KBA1 A0 VCC0 +3VALW
20 A1 VCC1 30 1 C376
KBA2 19
KBA3 A2 C358
18 A3 1 2
KBA4 ADB0

14
17 A4 D0 25 0.1U_0402_16V4Z
B KBA5 ADB1 2 U24A B
16 A5 D1 26 0.1U_0402_16V4Z
KBA6 15 27 ADB2 1
1MB ROM Socket FSEL# 26

P
KBA7 A6 D2 ADB3 INT_FSEL# A
14 A7 D3 28 3 O
KBA8 8 32 ADB4 2 INT_FLASH_EN#
A8 D4 B

G
KBA9 7 33 ADB5 JP30
KBA10 A9 D5 ADB6 KBA16 KBA17 SN74LVC32APWLE_TSSOP14
36 34

7
KBA11 A10 D6 ADB7 KBA15 1 2
6 A11 D7 35 3 4 2 1 R401
KBA12 5 KBA14 100K_0402_5%
KBA13 A12 KBA13 5 6 KBA19
4 A13 7 8
KBA14 3 10 RESET# 1 2 +3VALW KBA12 KBA10
KBA15 A14 RP# R219 100K_0402_5% KBA11 9 10 ADB7
2 A15 NC 11 11 12
KBA16 1 12 KBA9 ADB6
KBA17 A16 READY/BUSY# KBA8 13 14 ADB5
40 A17 NC0 29 15 16
KBA18 13 38 FWE# ADB4
KBA19 A18 NC1 RESET# 17 18
37 A19 19 20 +3VALW
INT_FLASH_EN#
INT_FSEL# SB_INT_FLASH_SEL# 21 22
22 CE# 18 SB_INT_FLASH_SEL# 23 24
FREAD# 24 23 KBA18 ADB3
26 FREAD# FWE# OE# GND0 KBA7 25 26 ADB2
9 WE# GND1 39 27 28
KBA6 ADB1
KBA5 29 30 ADB0 +3VALW
SST39VF080-70_TSOP40 KBA4 31 32 FREAD#
33 34

20K_0402_5%
KBA3
35 36

1
KBA2 FSEL# +3VALW
KBA1 37 38 KBA0 R233
39 40 SUSP# 16,23,26,29,34,35

2
+3VALW +3VALW @ SUYIN_80065AR-040G2T Q22

G
14
U24B 2N7002_SOT23

2
4 1 3

P
A EC_FLASH# 18
1

FWE# 6

S
O
1 2 C360 R222
B 5

G
0.1U_0402_16V4Z 100K_0402_5%
A SN74LVC32APWLE_TSSOP14 A

7
U23 FWR# 26
2

8 VCC A0 1
7 WP A1 2
26,31 EC_SMB_CK1 6 SCL A2 3
26,31 EC_SMB_DA1 5 SDA GND 4

AT24C16N-10SI-2.7_SO8
Security Classification Compal Secret Data Compal Electronics, Inc.
1 R221 2 Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS/TP-PAD/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 27 of 38
5 4 3 2 1
 5 4 3 2 1

+3VALW

Lid SW ON/OFF BUTTON

2
+3VALW
+3VALW R46
for debug only Kill SWITCH

1
100K_0402_5%
R254 BTN TOP D6

1
U27 47K_0402_5% 2 SW3 KS@
ON/OFFBTN# 26
A3212EEH_MLP6 1 3 1 3 ON/OFF 1 3
51_ON# 3
3 51_ON# 30

2
5 1 LID_SW# 2 4 2 4 2 R413
VDD OUTPUT LID_SW# 26 2
DAN202U_SC70 +3VALW 1 2
SW2 SW1 100K_0402_5%

6
5

6
5
0.1U_0402_16V4Z

10P_0402_50V8J
1 4 NC NC 2 1 1 1 KILL_SW# 25,26

1
D C405 C406 SMT1-05_4P SMT1-05_4P D
1

GND
D8 3 +3VALW
C123 RLZ20A_LL34 1BS003-1211L_3P 1
2 2 Q5 0.01U_0402_25V7K 2
3

1
D 2 D34

2
2 @ DAN217_SC59
26 EC_ON G

2
S 2N7002_SOT23

3
R49
10K_0402_5%

1
WL&BT LED SW/LED Connector
D35 KS@ +5VALW
+5VALW 1 2 2 1 WL_BT_LED# 26 2 MODE# 26 2 IE_BTN# 26
R414 KS@300_0402_5% HT-191UD_AMBER_0603 SYSON SYSON 23,26,34 MODEBTN# 1 IEBTN# 1
47K

3
Q35 3 51_ON# 3 51_ON#

2
2N7002_SOT23

G
POWER/SUSPEND LED 10K
D30 D31
D15 2 1 3 DAN202U_SC70 DAN202U_SC70
PWR_SUSPLED1# PWR_SUSP_LED 26
2 1

S
HT-191UD_AMBER_0603
D21
PWR_LED_0# 2 1 Q36 KSO17 C508 1 2@ 220P_0402_50V7K
C HT-191NB_BLUE_0603 DTA114YKA_SOT23 C

1
R392 1 2 300_0402_5% PW R_SUSPLED# ON/OFF C506 1 2@ 220P_0402_50V7K
R393 1 2 300_0402_5% PWR_SUSPLED1# JP3
BATT CHARGE/FULL LED 1
PWR_LED_1# PWR_LED_1# C510 1 2@ 220P_0402_50V7K
D16 PW R_SUSPLED#
BATT_CHG_LOW_LED# 2 ON/OFF PW R_SUSPLED# C509 1
+5VALW 1 2 2 1 BATT_CHG_LOW_LED# 26 3 2@ 220P_0402_50V7K
R399 300_0402_5% HT-191UD_AMBER_0603 +5VALW IEBTN#
D22 4 KSO17 IEBTN# C504 1
5 KSO17 26 2@ 220P_0402_50V7K
1 2 2 1 BATT_FULL_LED# BATT_FULL_LED# 26 SYSON MODEBTN#
47K 6

3
R398 120_0402_5% HT-191NB_BLUE_0603 EC_PLAYBTN# MODEBTN# C502 1 2@ 220P_0402_50V7K
7 KSI0 26

2
Q33 EC_STOPBTN#

G
2N7002_SOT23 8 EC_FRDBTN# KSI1 26 EC_REVBTN# C489 1 2@ 220P_0402_50V7K
HDD LED 10K 2 1 3 POWER_LED# 26
9
10
EC_REVBTN# KSI3
KSI2
26
26
D19 BUTTON_ID EC_FRDBTN# C490 1 2@ 220P_0402_50V7K

S
11 BUTTON_ID 26
+5VS 1 2 2 1 HDD_LED# 26 12
R397 120_0402_5% HT-191NB_BLUE_0603 EC_PLAYBTN# C500 1 2@ 220P_0402_50V7K
Q34 ACES_85201-1205
AC IN LED DTA114YKA_SOT23 EC_STOPBTN# C499 1 2@ 220P_0402_50V7K
1

D18 R391 1 2 120_0402_5% PWR_LED_0#

R390 1 2 120_0402_5% PWR_LED_1# BUTTON_ID C810 1 2@ 220P_0402_50V7K
D

+5VALW 1 2 2 1 1 3
R400 120_0402_5% HT-191NB_BLUE_0603 Q37
2N7002_SOT23
For EMI Request
G
2

ACIN 18,26,30

USB CONN. 1 (In Back Side) USB CONN. 2 (In Left Side) KEYBOARD CONN.
R690 0_0402_5%
+USB_VCCB

SUYIN_020167MR004S511ZR
R691 0_0402_5% JP6 KSI[0..7]
B +USB_VCCA KSI[0..7] 26 B
NUM_LED#
@ WCM2012F2S-900T04_0805 1 NUM_LED# 26
SUYIN_020173MR004G565ZR

JP21 PADS_LED# KSO[0..15]

@ WCM2012F2S-900T04_0805 2 PADS_LED# 26 KSO[0..15] 26
JP12 1 2 1 CAPS_LED#
1 2 VBUS 3 CAPS_LED# 26
1 2 1 USB20_4N 2 2 1 +3VS
1 2 VCC 18 USB20_N4 D- 4
USB20_1N 2 USB20_4P 3 KSO15 R88 300_0402_5%
18 USB20_N1 D- 18 USB20_P4 D+ 5
USB20_1P 3 4 3 4 KSO14
18 USB20_P1 D+ 4 3 GND 6
4 3 4 5 KSO10
4 3 GND L50 GND 7 KSO11
6 GND 8 2 1PADS_LED# NUM_LED# 1 2
L51 5 7 KSO8 100P_0402_50V8J C193 C194 100P_0402_50V8J
GND1 R688 0_0402_5% GND 9 KSO9
6 GND2 8 GND 10 2 1 KSO14 CAPS_LED# 1 2
R689 0_0402_5% 7 KSO13 100P_0402_50V8J C191 C195 100P_0402_50V8J
GND3 11 KSI7
8 GND4 12 2 1 KSO11 KSO15 1 2
KSO3 100P_0402_50V8J C189 C192 100P_0402_50V8J
Place close to USB connector 13 KSO7 1 KSO9 KSO10
Place close to USB connector +USB_VCCB 14 KSO12
2
100P_0402_50V8J C187 C190
1 2
100P_0402_50V8J
+USB_VCCA 15 KSI4 KSI7 KSO8
W=60mils 16 KSI6
2
100P_0402_50V8J
1
C185 C188
1 2
100P_0402_50V8J
17 KSI5
1 18 2 1 KSO7 KSO13 1 2
1 1 1 KSO6 100P_0402_50V8J C183 C186 100P_0402_50V8J
C551 + C232 C233 19 KSO5 KSI4 KSO3
C408 + C410
1
C409
W=60mils
1
150U_D2_6.3VM 20 KSI3
2
100P_0402_50V8J
1
C181 C184
1 2
100P_0402_50V8J
150U_D2_6.3VM 0.1U_0402_16V4Z 1000P_0402_50V7K 21 KSI0 KSI5 KSO12
22 2 1 1 2
0.1U_0402_16V4Z 1000P_0402_50V7K 2 2 2 KSO0 100P_0402_50V8J C179 C182 100P_0402_50V8J
2 2 2 23 KSO1
24 2 1 KSO5 KSI6 1 2
KSI1 100P_0402_50V8J C196 C180 100P_0402_50V8J
25 KSI2 KSI0 KSO6
26 2 1 1 2
+USB_VCCB KSO2 100P_0402_50V8J C201 C178 100P_0402_50V8J
U12 27 KSO4
28 2 1 KSO1 KSI3 1 2
1 8 2 1 +3VS 100P_0402_50V8J C199 C198 100P_0402_50V8J
+USB_VCCA GND OUT 29 R91 300_0402_5% KSI2 KSO0
+5VALW 2 IN OUT 7 30 2 1 1 2
U28 3 6 100P_0402_50V8J C176 C200 100P_0402_50V8J
USB_EN# IN OUT 31
1 GND OUT 8 4 EN# FLG 5 32 2 1 KSO4 KSI1 1 2
A 100P_0402_50V8J C174 C177 100P_0402_50V8J A
+5VALW 2 IN OUT 7 33
3 6 +5VALW G528_SOP8 1 2 KSO2 1 2
25,26 USB_EN#
USB_EN# 4
IN
EN#
OUT
FLG 5 1.4A 34 R90 300_0402_5%
+3VS
C175 100P_0402_50V8J
1 ACES_88170-3400
C412 G528_SOP8
C816 C817 C245 Close to JP21 For EMI Request
1.4A
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z 1 1 1
2
Close to JP12 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/LID/KS/KB/LED/SW-B Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 28 of 38
5 4 3 2 1
 A B C D E

H10 H1 H3 H5 H_C157BC276D157 H7
H_S315D118 H_S315D118 H_S315D118 H_S394BS315D118 H24 H_C276D197

@ @ @ @ @ @

New LPC Debug Pad ---- MB side

1
R502
@ 0_0402_5% H27 H28 H26 H13 H14 H19 H_C157BC276D157
H30
1 2 E51_TXD E51_TXD 26 H_S315D118 H_S315D118 H_S315D118 H_R354BR354X315D118 H_C295D165 H_C295D165 H22
R503 +3VALW
@ 0_0402_5% @ @ @ @ @ @ @
26 E51_RXD E51_RXD 1 2 6 5 1 2 LPC_DRQ#1 LPC_DRQ#1 17

1
1 R504 1
0_0402_5%
18,20,26 SIRQ SIRQ 1 2 7 4 PCI_RST# PCI_RST# 18,20,26 H15 H16
R505 H11 H2 H4 H21 H_C295D165 H_C276BC157D157 H25
0_0402_5% H_C256D126 H_C256D126 H_S394BS315D118 H_S315D118 H_S315D118
17,26 LPC_AD3 LPC_AD3 8 3 LPC_AD2 LPC_AD2 17,26 @ @
@ @ @ @ @

1
1

1
17,26 LPC_AD1 LPC_AD1 9 2 LPC_AD0 LPC_AD0 17,26
H8
17,26 LPC_FRAME# LPC_FRAME# 10 1 CLK_PCI_SIO2 CLK_PCI_SIO2 14 H_C276BC157D157 M1 M3 M7 H18 M4 H17
H_O150X126D150X126N H_C59D59N H_C122D122N H_C295D165 H_O276X177D276X177N H_C169D169N
@
R537 C711
@ @ @ @ @ @

1
@ 1 2 1 2
DEBUG_PAD

1
Under DDR ME Assigment Area 10_0402_5% 10P_0402_50V8J

Keep Resistor near Debug Pad and in the same side

FD4 FD6 FD5 FD2 FD1 FD3
Reverse side DIMM ---- Pin 1 keep away DIMM @ @ @ @ @ @

1
CF4 CF8 CF2 CF7 CF1 CF5 CF10 CF3 CF9
1 1 1 1 1 1 1 1 1
@ @ @ @ @ @ @ @ @
2 2

H44 H34 H35 H36 H37 H38 H31

H_C236BC160D157 H_C197D91 H_C197D91 H_C197D91 H_C256D126 H_C315D315N H_C256BC160D157

@ @ @ @ @ @ @

1
H33 H40 H41 H42 H32
H_C276BC157D157 H_R354x315D118 H_S315D118 H_C236BC256D118 H_C256BC160D157

@ @ @ @ @

1
+5VALW to +5VS Transfer +1.8V to +1.8VS Transfer (Place close to VGA-Connector) +3VALW to +3VS Transfer
3 +1.8V 3
+1.8VS
+5VALW +5VS U3 0.1U_0402_16V4Z
8 D S 1
U19 0.1U_0402_16V4Z 1 7 2 +3VALW
D S

1
10U_0805_10V4Z

8 1 C29 6 3 1 1 +3VS
D S 10U_0805_10V4Z D S C32 C33 R26 U21 0.1U_0402_16V4Z
1 7 D S 2 5 D G 4
+VSB 6 3 PM@ PM@ 8 1
D S 1 1 D S
1

2 AO4456_SO8 10U_0805_10V4Z 470_0805_5%

5 D G 4 1 7 D S 2

1
+VSB 2 PM@ 2
340K_0402_1%

C317 C349 C345 R218 PM@ PM@ C355 6 3 1 1

2
D S
1

2 AO4422_SO8 10U_0805_10V4Z 10U_0805_10V4Z C346 C335 R339

5 D G 4
2 2 470_0805_5%
1

1
R195 D 2 AO4422_SO8 10U_0805_10V4Z 470_0805_5%
2

R613 SUSP Q2 2 2
2

2
820K_0402_1% G
2

1 R196 2 RUNON PM@ 2N7002_SOT23 S PM@

3
1

1
D D
2
1
10M_0402_5%

0.033U_0603_25V7K

0_0402_5% 2 Q32 2 SUSP 1 R614 2 1.8VS_ON RUNON SUSP 2 Q31

1

D R513 G PM@ 0_0402_5% G

1
10M_0402_5%

0.033U_0603_25V7K

SUSP 2 Q20 C316 S 2 2N7002_SOT23 S

3

3
1

G 2N7002_SOT23 D R615
1 SUSP Q66 PM@ C813
S 2
3

2N7002_SOT23 G PM@
S PM@ 1
3

2N7002_SOT23

Discharge Circuit
+2.5VS +1.5VS +VCCP +0.9VS +5VALW

4 4
1

R27 R72 R93 R70 R184

470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 10K_0402_5%

2

2
2N7002_SOT23

SUSP
SUSP 35
2N7002_SOT23

2N7002_SOT23

2N7002_SOT23

2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.

1

D Q1 D Q8 D Q11 D Q7 D Q18
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 2006/10/03 2009/10/03 Title
G G G G G
SUSP# 16,23,26,27,34,35 Issued Date Deciphered Date
S S S S S DC/DC I/F_Debug I/F_Screw
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 29 of 38
A B C D E
 A B C D

VS
PR1
VIN VIN 1M_0402_1%
PL1 1 2
PF1 FBMA-L18-453215-900LMA90T_1812
DC301001M80

1
DC_IN_S1 1 2 DC_IN_S2 1 2

1
VS PR2
PJP1 7A_24VDC_429007.WRML PR3 5.6K_0402_5% PR4
1 84.5K_0402_1% 10K_0402_1%
+
1 2

2
ACIN 18,26,28

1
2 PR5

2
+

8
PC1 PC2 PC3 PC4 22K_0402_1% PU1A
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

P
2

2
- + PACIN
1 O 1 PACIN 32,33 1

- 4 2 -

G
1

1
@ SINGA_2DW-0005-B03 PR6 LM393M_SO8

4
PC5 20K_0402_1% PC6 PR7
0.068U_0402_10V6K 0.1U_0402_16V7K PD1 10K_0402_1%

2
RLZ4.3B_LL34

2
2
PR8
1 RTCVREF Vin Detector
10K_0402_1%
VIN 3.3V
High 18.384 17.901 17.430

2
PD2
RLS4148_LLDS2
Low 17.728 17.257 16.976

1
PD3
BATT+ 2 1

1
RLS4148_LLDS2 PR9 PR10
68_1206_5% 68_1206_5%
PQ1 1 2
PR12 TP0610K-T1-E3_SOT23 PR11

2
200_0603_5% 1K_1206_5%
CHGRTCP 1 2 N1 3 1 VS
PD4
1

2 1 N3 1 2
VIN B+
1

1
PC8 PR13
2 PR14 PC7 0.1U_0603_25V7K RLS4148_LLDS2 1K_1206_5% 2

100K_0402_1% 0.22U_1206_25V7K
2

2
2

28 51_ON# 1 2 1 2
PR15 PR16
22K_0402_1% 1K_1206_5%

RTCVREF
1

PR18 PR19
PR17 100K_0402_1% 2.2M_0402_5%

1
PU2 200_0603_5% 1 2 2 1
PR21 PR22 G920AT24U_SOT89 VL PR20
560_0603_5% 560_0603_5% 3.3V 499K_0402_1%
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN PU1B

2
1

8
PD6 LM393M_SO8
1

GND PD5 2 5

P
PC9 PC10 RLZ16B_LL34 31,33 MAINPWON 1 7
+
10U_0805_10V4Z 1 1U_0805_25V4Z O
3 6 2 1 VL
32 ACON
2

1
2

1
RB715F_SOT323 PR23 PR24

4
1

1
34K_0402_1% 499K_0402_1% PC11

1
PC12 PR26 1000P_0402_50V7K

2
1000P_0402_50V7K PC13 PR25 191K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
3 3

PJ2
PJ1 +1.8VP 2 1 +1.8V PR27
2 1

1
+3VALWP 2 1 +3VALW PQ2 D 47K_0402_1%
2 1 @ JUMP_43X118 PACIN
2 2 1
@ JUMP_43X118 PJ15 RHU002N06_SOT323
G
(5A,200mils ,Via NO.= 10) 2 1 1 Precharge detector S

3
2
PJ3 @ JUMP_43X118
15.97V/14.84V FOR

1
+5VALWP 2 2 1 1 +5VALW (8A,320mils ,Via NO.= 16)
@ JUMP_43X118
ADAPTOR PQ3
DTC115EUA_SC70
PJ4
(5A,200mils ,Via NO.= 10)
PJ5 +2.5VSP 2 2 1 1 +2.5VS 2 +5VALWP

+VSBP 2 1 +VSB @ JUMP_43X39

2 1
(0.35A,40mils ,Via NO.=2)
@ JUMP_43X39

3
(120mA,40mils ,Via NO.= 2) PJ6
+0.9VSP 2 2 1 1 +0.9VS
@ JUMP_43X79
PJ7 (2A,80mils ,Via NO.= 4)
+1.05VSP 2 2 1 1 +VCCP
@ JUMP_43X118 PJ8
(5A,200mils ,Via NO.= 10) +1.5VSP 2 1 +1.5VS
2 1
@ JUMP_43X118
(4.5A,180mils ,Via NO.= 9)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 30 of 38
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 87(86) degree C
Recovery at 48(47) degree C

VL VS VL

2
VMB
PF2 PL2 PR28

1
1
PJP2 12A_65VDC_451012 FBMA-L18-453215-900LMA90T_1812 47K_0402_1% 1

1 BATT_S1 1 2 1 2 PH1 PC14

BATT+ BATT+ MAINPWON 30,33
PR29 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR31

1
1K_0402_1% 47K_0402_1%

1
2 ALI/NIMH# 1 2 1 2 1 2
+3VALWP

2
ID AB/I PR30 PR32
B/I 3

8
4 TS_A 47K_0402_1% 13.7K_0402_1%
TS EC_SMDA PC15 PC16 PU3A
5 1 2 3

P
SMD +

1
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 1 2 1 2 PQ4

2
SMC PR33 TM_REF1 O DTC115EUA_SC70
GND 7 2 -

G
1K_0402_1% PD7
@ SUYIN_250005MR007G132ZR LM393M_SO8 1SS355_SOD323

4
2

3
2

0.22U_0805_16V7K
PR35

20K_0402_1%
PR34 100_0402_5%

1
PC17
100_0402_5%

1000P_0402_50V7K
PR36
ALI/MH# 26,32
1

2 1 VL

PC18
PR38 PR37

2
6.49K_0402_1% 100K_0402_1%

2
2 1 +3VALWP

1
PR39
100K_0402_1%
1

2
PR40
1K_0402_1%
2

2 2

PH2 near main Battery CONN :

BATT_TEMPA 26
BAT. thermal protection at 79 degree C
EC_SMB_DA1 26,27 Recovery at 45 degree C
EC_SMB_CK1 26,27

VL VL

2
PR41
PH2 47K_0402_1%
100K_0603_1%_TH11-4H104FT PR42
47K_0402_1%

1
1 2

PR43

8
10.7K_0402_1% PU3B
PQ5 1 2 5

P
TP0610K-T1-E3_SOT23 +
O 7 2 1
TM_REF1 6 -

G
B+ 3 1 +VSBP PD8

1
3 LM393M_SO8 1SS355_SOD323 3

4
0.22U_1206_25V7K

0.1U_0603_25V7K

PC19 PR44
1

100K_0402_1%

0.22U_0805_16V7K 22K_0402_1%

2
1

1
PR45

PC20

PC21

2
2

PR46 @ @
2

22K_0402_1%
VL 1 2
100K_0402_1%
2
PR47

PR48
1

0_0402_5% D
1 2 2
33 POK G
0.1U_0402_16V7K

S PQ6
3
1

PC22

RHU002N06_SOT323
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 31 of 38
A B C D
 A B C D

Iadp=0~3.125A B+ 65W/75W Iadp=0~3.125A PR49=0.02_2512_1% PR55=30K_0402_1% PQ7

P2 P3 AO4407_SO8
90W Iadp=0~4.2A PR49=0.015_2512_1% PR55=29.4K_0402_1% 1 8
PQ8 PQ9
2 7
AO4407_SO8 AO4407_SO8 3 6
8 1 1 8 1 4 PL12 5
VIN
7 2 2 7 FBMA-L18-453215-900LMA90T_1812
6 3 3 6 2 3 1 2 B++

4
5 5

1
PR49 PC137

1
0.02_2512_1% 330P_0402_50V7K PC23 PC24 PC25

4
PC138 4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

2
330P_0402_50V7K

2
1
1 1

PR50
1

3
200K_0402_1% PR52
PR51 47K_0402_1%

2
47K

1
47K_0402_1% 1 2 VIN
2 PC26 26 ADP_I PU4
47K

2
0.1U_0603_25V7K 1 24
2

2
-INC2 +INC2

3
2
1
PR53
PQ11 10K_0402_1%
PQ10 2 1 2 23 AO4407_SO8
OUTC2 GND
1

DTA144EUA_SC70 PR54 PC27 4 ACOFF#

1

1
100K_0402_1% 0.022U_0402_16V7K
3 22 CS 1 2
+INE2 CS

1
2

1
4 -INE2 VCC(o) 21 1 2

1
PQ12 PR55 PR57

5
6
7
8
1
DTC115EUA_SC70 PC29 30K_0402_1% 10K_0402_1% PC28 2 ACOFF 26
1

PQ14 D 0.1U_0402_16V7K PR56 0.1U_0603_25V7K DH_CHG

1 2 1 2 5 20
3

PR58 10K_0402_1% FB2 OUT PQ13

2

2
G RHU002N06_SOT323 150K_0402_1% PC30 DTC115EUA_SC70

2
S 4700P_0402_25V7K 6 19 1 2 LX_CHG
3

3
PR59 VREF VH PC31
2

1
PC32 1K_0402_1% 0.1U_0603_25V7K
0.1U_0402_16V7K 1 2 1 2 7 18 1 2
ACOFF#1 FB1 VCC PC34
2 CC=0.6~3A
2
PC33 0.1U_0603_25V7K
PD9 1000P_0402_50V7K 8 17 1 2
1SS355_SOD323 -INE1 RT PR60 CV=12.6V(6 CELLS LI-ION)
68K_0402_5%
CV=16.8V(8 CELLS LI-ION)
1

PQ15 D PL3
26 IREF 1 2 9 +INE1 -INE3 16
2 PACIN 1 2 2 PR61 PR64 PR65 16UH_D104C-919AS-160M_3.7A_20% 2
30,33 PACIN
PR62 G RHU002N06_SOT323 162K_0402_1% 10K_0402_1% 47K_0402_1% 1 2 1 4 BATT+
3K_0402_1% S 2 1 10 15 1 2 1 2
3

1 OUTC1 FB3
2 3

1
PC35

1
ACON PR66 PC36 11 14 ACON 1500P_0402_50V7K PR63
30 ACON OUTD CTL

1
100K_0402_1% 0.1U_0402_16V7K PD14 0.02_2512_1% PC39
2

@ EC31QS04 PD10 PC37 4.7U_1206_25V6K

2

12 13 EC31QS04 4.7U_1206_25V6K

2
-INC1 +INC1 PC38
IREF=1.31*Icharge

2
4.7U_1206_25V6K
MB3887PFV-ERE1_SSOP24
IREF=0.6V~3.144V
ISE_CHG+
+3VALWP
CS
4.2V
1

2 1 2 1
1

PR69
47K_0402_1% PQ16 PR67 PR68
DTC115EUA_SC70 150K_0603_0.1% PQ17 300K_0603_0.1%
2

D
2 3 1 RHU002N06_SOT323
2 1
1

PR70
300K_0603_0.1%

G
2
3

VL 1 2
26 FSTCHG 2
PR71 1
3 PQ18 100K_0402_1% 3

DTC115EUA_SC70
3

2
26,31 ALI/MH# BATT Type ALI/MH# Charge Current IREF
VMB PQ19
DTC115EUA_SC70
OVP voltage : LI 8 CELL 0V 3A 3.144V
3
1

4S2P : 18V--> BATT_OVP= 2V

3S2P : 13.5V--> BATT_OVP= 1.5V PR72
340K_0402_1% 6 CELL 3.3V 3A 3.144V
(BAT_OVP=0.1111 *VMB)
1 2

VS

PR73
499K_0402_1%
2
8

PU5A
3
P

+
1
26 BATT_OVP 0
2
-
G

LM358DT_SO8
4
1

PR74
1

2.2K_0402_5%
1

PC40
PR75 0.01U_0402_25V7K
2

105K_0402_1%
2

4 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 32 of 38
A B C D
 5 4 3 2 1

+3.3VALWP/+5VALWP
BST_5V BST_3V

3
PD11
D DAP202U_SOT323 D

B+++ B+++
PJ10 VL

1
B+ 1 1 2 2

B+++

5
6
7
8
2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
@ JUMP_43X118

D
D
D
D
1

8
7
6
5
PC44

PC45

PC41

PC42
2
10_1206_5%

10_1206_5%

47_0402_5%
PC43

PQ21 PQ20

D
D
D
D

2
1

1
SI4800BDY-T1-E3_SO8 SI4800BDY-T1-E3_SO8
2

G
S
S
S
PR77

PR78

PR76
PC46
0.1U_0402_16V7K

4
3
2
1
G
S
S
S
DH_3V

0.1U_0603_25V7K 1
1
2
3
4

2
PR79

2.2U_0805_25V6K

2.2U_0805_25V6K
0_0603_5%

5
6
7
8
DH_5V 1 2 VL
2VREF_8734

D
D
D
D
1

PC48

200K_0402_1%

200K_0402_1%
4.7U_0805_6.3V6K

PC134

PC47
PQ22
8
7
6
5

2
SI4810BDY-T1-E3_SO8

G
S
S
S
PR80

PR81
1U_0603_6.3V6M
PQ23
D
D
D
D

SI4810BDY-T1-E3_SO8

4
3
2
1
1
PC49
DH_5V-1

PC50

1
G
S
S
S

2
1
2
3
4

1
1

PC51

18

20

13

17

2
340K_0402_1%

340K_0402_1%
PL4 0.1U_0603_25V7K PU6

2
PR83
C 4.7U_LF919AS-4R7M-P3_5.2A_20% PR82 1 BST_5V-1 C
2 1 2 14

TON

VCC
LD05

V+
BST5

PR84
0_0603_5% 5 ILIM3 PR85
ILIM3 0_0603_5%
16
+5VALWP DH5
2

1
LX_5V 15

1
DL_5V LX5 ILIM5 PC52
19 DL5 ILIM5 11
21 0.1U_0603_25V7K
OUT5

1
FB5 9 28 BST_3V-1 2 PR86 1 2 1
FB5 BST3 DH_3V-1 0_0603_5%
PD12 1 N.C. DH3 26
10.5K_0402_1%

PR87 24 DL_3V
DL3 LX_3V PL5
VS 1 2 1 2 6 SHDN# LX3 27
2

4 22 4.7U_LF919AS-4R7M-P3_5.2A_20%
ON5 OUT3
2.2U_0805_25V6K
PR88

47K_0402_1% 3

2
RLZ5.1B_LL34 PR89 ON3 FB3
FB3 7
150U_V_6.3VM_R18

1
30,32 PACIN
1 2 12 SKIP# PGOOD 2 +3VALWP
1

PC54

@ 10K_0402_1%
1

6.81K_0402_1%
PC53

PRO#
LDO3
8

GND
REF

2
PR90
2VREF_8734
2

PR91
100K_0402_1% POK 31
2
1
2

23

25

2 10
@ 1 2 MAX8734AEEI+_QSOP28
2

6.81K_0402_1%

4.7U_0805_6.3V6K
+ PC55

1
0.22U_0603_10V7K
PR92

PR188 150U_V_6.3VM_R18

1
PC57
0_0402_5% PR93
VL

2
2
0_0402_5%
PC56
1

10K_0402_1%
PR94
2

1
806K_0603_1%
1

1
PR95

B B
2

PR96
0_0402_5%
2 1
30,31 MAINPWON
1

PC58
0.047U_0603_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
+5V/+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IAKAA M/B LA-3401P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 33 of 38
5 4 3 2 1
 A B C D

PL13
FBMA-L18-453215-900LMA90T_1812
1 2 B+

1
1

1
PC59 PC60 PR97

1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5% PC139
PC61 330P_0402_50V7K

2
4.7U_1206_25V6K PC62

2
+5VALWP 4.7U_1206_25V6K
1 1

2
PC63

1
4.7U_0805_6.3V6K PC64 PR98 PC65
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
PD13

1
DAP202U_SOT323

3
8
7
6
5
BST_1.5V-1

D
D
D
D
+1.8V PQ24

BST_1.8V-1
SI4800BDY-T1-E3_SO8
PC66 PC67

14

28
G
S
S
S
+1.8VP 0.01U_0402_25V7K PU7 0.01U_0402_25V7K

5
6
7
8
PL6 2 1 12 SOFT1 17 2 1

VIN

VCC
1
2
3
4
1.8U_D104C-919AS-1R8N_9.5A_30% DH_1.8V-2 SOFT2

D
D
D
D
1 2 LX_1.8V PC68 PC69 PQ25
0.1U_0402_16V7K 0.1U_0402_16V7K SI4800BDY-T1-E3_SO8
1 2 1 1 2BST_1.8V-2 6 23 BST_1.5V-2
1 2 2 1
BOOT1 BOOT2
+1.5V
2

G
S
S
S
PR99 PR100
+ PC70 PR101 0_0603_5% 0_0603_5%

4
3
2
1
8
7
6
5
220U_6.3V_M_R13 @ 4.7_1206_5%
1 2 DH_1.8V-1 5 24 DH_1.5V-1 1 2 DH_1.5V-2 PL7 +1.5VSP

D
D
D
D
2
1
PR102 UGATE1 UGATE2 PR103 1.8U_D104C-919AS-1R8N_9.5A_30%
1

PQ26 0_0603_5% 4 25 0_0603_5% LX_1.5V 1 2

PHASE1 PHASE2
1

PR104 PC71 SI4810BDY-T1-E3_SO8

2

2
S
S
S
10.2K_0402_1% 0.01U_0402_25V7K PR106 PR107

5
6
7
8
PC72 2K_0402_1% 2K_0402_1% PR105
2

1
2
3
4
2

2 @ 680P_0603_50V8J 1 2 ISE_1.8V 7 22 ISE_1.5V 1 2 @ 4.7_1206_5% 1 2

D
D
D
D
2

ISEN1 ISEN2

1
PR108 DL_1.8V 2 27 PQ27 PR109 + PC73

2 1
LGATE1 LGATE2

1
0_0402_5% SI4810BDY-T1-E3_SO8 0_0402_5% PC74 PR110 220U_6.3V_M_R13

G
S
S
S
PC75 0.01U_0402_25V7K 6.81K_0402_1%
1

@ 680P_0603_50V8J 2

4
3
2
1

2
3 26

1
PGND1 PGND2 DL_1.5V

9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.5V
VSEN1 VSEN2
1 2 8 EN1 EN2 21 1 2
23,26,28 SYSON PR111 15 16 PR112 SUSP# 16,23,26,27,29,35
0_0402_5% PG1 PG2/REF 24K_0402_1%

GND

DDR
11 OCSET1 OCSET2 18
1

1
2

1
PR113 ISL6227CAZ-T_SSOP28 PR114 PR115

13
1

1
10K_0402_1% PR116 PC76 @ 0_0402_5% 10K_0402_1%
@ 0_0402_5% @ 0.1U_0402_16V7K PR118 PR117 PC77
100K_0402_1% 100K_0402_1% 0.1U_0402_16V7K
2

2
1

2
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V / 1.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 34 of 38
A B C D
 5 4 3 2 1

PL14
1 2 6269_B+
B+
FBMA-L18-453215-900LMA90T_1812 6269_VCC

1
PHASE_VCCPP

1
PC140 PR119 UG_VCCPP_1
680P_0402_50V7K PC78 PC79 1K_0402_1%
10U_1206_25VAK 10U_1206_25VAK PR120 PC80

2
1 2 1 2

2
36 PGD_IN 0_0603_5% 0.1U_0603_25V7K
+5VALW PR121
D D
0_0603_5%

1
BOOT_VCCPP
PR122

1
0_0603_5%

5
6
7
8
17

16

15

14

13
PU8 PQ28

D
D
D
D
2
1 PR123 2 6269_VCC

PHASE
GND

PGOOD

UG

BOOT
4.7_0603_5%

G
S
S
S
1 VIN PVCC 12 1 2
SI4800BDY-T1-E3_SO8

4
3
2
1
6269_VCC PC81
2.2U_0603_6.3V6K UG_VCCPP_2

1
LG_VCCPP PL8
PC82 PR124
2 VCC LG 11 +1.05V
1.8U_D104C-919AS-1R8N_9.5A_30%
2.2U_0603_6.3V6K @ 0_0402_5% 1 2 +1.05VSP
2
PR125
0_0402_5% 3 10 1

2
FCCM PGND

5
6
7
8

1
1 2 PQ29
PR187 + PC83

D
D
D
D
PR127 SI4810BDY-T1-E3_SO8 @4.7_1206_5% 220U_D2_4VM_R15
SUSP# 1 2 4 9 ISEN_VCCPP
1 2
16,23,26,27,29,34 SUSP# EN ISEN 2

2
COMP

G
S
S
S
PR126 8.25K_0402_1%

FSET
1

24K_0402_1%

VO
FB

4
3
2
1

1
PC84
0.1U_0402_16V7K PC136
2

8
ISL6269ACRZ-T_QFN16_4X4 @680P_0603_50V8J

2
C C

57.6K_0402_1%

1
PR129
1
PC86 PR128 PC85
22P_0402_50V8J 49.9K_0402_1% 0.01U_0402_25V7K

2
2

2
1 PC87
6800P_0402_25V7K PR130
2
2.26K_0402_1%
1 2

1
PR131
3K_0402_1%
2

+1.8V

1
PJ13

1
@ JUMP_43X79

2
PU9

2
1 VIN VCNTL 6 +3VALW
B B
2 GND NC 5

1
+3VALW

1
PC88 3 7 PC89
10U_1206_6.3V7K PR132 VREF NC 1U_0603_6.3V6M

2
1K_0402_1% 4 8
+5VALW VOUT NC
1

2
PJ14 TP
1

@ JUMP_43X79 APL5331KAC-TRL_SO8
1

1
2

PC90 PR134 +0.9VSP

1
0_0402_5% PQ30 D PR133
2

1U_0603_6.3V6M SUSP 1 2 2 1K_0402_1% PC91

2

1
G 0.1U_0402_16V7K

2
1
S PC92

2
6

PU10 PC93 RHU002N06_SOT323 10U_1206_6.3V7K

2
5 PC94 @ 0.1U_0402_16V7K
VCNTL

2
VIN 22U_1206_6.3V6M
7
2

POK
VOUT 4
PR135
VOUT 3 +2.5VSP
@ 0_0402_5% 1
1

SUSP# 1 2 8 2
EN FB
1

22U_1206_6.3V6M

PR136 + PC96
GND

PC95

9 PC97 @ 150U_D_6.3VM
2

VIN
1

2.15K_0402_1%
2

PC98 2
1

@ 0.01U_0402_25V7K
2

APL5912-KAC-TRL_SO8
1

0.01U_0402_25V7K

PR186 PR137
1

A 11K_0402_1% D 1K_0402_1% A
1 2 2 PQ37
2

29 SUSP G
S RHU002N06_SOT323
3
1

PC132
0.1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5V / 0.9V / 1.05V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 35 of 38
5 4 3 2 1
 5 4 3 2 1

+5VS

2
CPU_VID6

CPU_VID5
CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
5

5
PR138 +CPU_B+
PL9

VR_ON

26
1_0603_5%
FBMA-L18-453215-900LMA90T_1812
1 2 B+

10U_1206_25VAK

10U_1206_25VAK
1

10U_1206_25VAK

1
PC100

PC101

PC102
D PR139 499_0402_1% + PC135 PC141 D

1
7,18 DPRSLPVR 1 2 PC104 PC99 680P_0603_50V8J 3300P_0402_50V7K
PC103 2.2U_0603_6.3V6K 220U_25V_M

2
PR140 0_0402_5% 0.022U_0402_16V7K 2

2
PR142

PR143

PR144

PR145

PR146

PR147

PR148
PR149
4,17 H_DPRSTP# 1 2

5
PR141 0_0402_5% PQ31
14 CLK_ENABLE# 1 2 SI7840DP-T1-E3_SO8

1
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR150 0_0402_5%
+3VS 1 2 UGATE_CPU1-2 4

+3VS

1U_0603_6.3V6M

2
2
1.91K_0402_1%
0_0603_5% 0.22U_0603_10V7K

1
PC107
PR151 PC108 0.36UH_MPC1040LR36_24A_20%

3
2
1
1
BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

6.8_1206_5%
PR152

PR153

5
6
7
8

5
6
7
8

1
10K_0402_1%
3.65K_0805_1%
PL10

PR155

PR156

PR157
499_0402_1% PR158

49

48

47

46

45

44

43

42

41

40

39

38

37
1 2
1_0603_5% 1_0402_5%
2

PR154 PQ32

GND

VR_ON
3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1

680P_0603_50V8J
PQ33

1 2

2
1 36 4 4 PR159 @ 0_0603_5%
14,18,26 VGATE PGOOD BOOT1

PC109
1 2
5 H_PSI# 2 35 UGATE_CPU1-1 VSUM PC110
PSI# UGATE1
1 2

2
35 PGD_IN 3 34 PHASE_CPU1 VCC_PRM

3
2
1

3
2
1
PR160 147K_0402_1% PGD_IN PHASE1 ISEN1
1 2 4 33 0.22U_0603_10V7K
RBIAS PGND1 IRF8113PBF_SO8 IRF8113PBF_SO8
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25VAK

10U_1206_25VAK
PR161 @ 4.22K_0402_1% PH3

1
C C
1 2 1 2 6 NTC PVCC 31

PC111

PC112
PQ34
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7840DP-T1-E3_SO8

2
SOFT LGATE2
1 2
@ 0.015U_0402_16V7K PC113 8 29
0.022U_0603_25V7K PC114 OCSET ISL6262CRZ-T_QFN48 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PR162
PR163 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2 0.36UH_MPC1040LR36_24A_20%
COMP UGATE2 1_0603_5%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR164 PL11
1 2

5
6
7
8

5
6
7
8

1
1000P_0402_50V7K PC116 0_0603_5% PC115
DROOP

12 FB2 NC 25

1
VDIFF

VSUM

ISEN2

ISEN1

10K_0402_1%
VSEN

PR166 4.42K_0402_1% 0.22U_0603_10V7K PR165

GND

VDD
RTN

DFB

1
3.65K_0805_1%
VIN

PR167
PQ35 PQ36 6.8_1206_5% PR169
VO

1 2

PR168
1 2 PU11
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4 4 1_0402_5%

2
PC117 47P_0402_50V8J

2
ISEN1 PC118 PR170 @ 0_0603_5%
ISEN2 680P_0603_50V8J 1 2

2
2

PR172 61.9K_0402_1% PC119 0.033U_0402_16V7K 1 2 +5VS

3
2
1

3
2
1
1

1 2 2 1 PR173 VSUM PC120

1

@ 0_0402_5% PR171 1_0603_5% 1 2

PR174 PC121
1 2 1U_0402_6.3V4Z
1

@ 0_0402_5% IRF8113PBF_SO8 IRF8113PBF_SO8 0.22U_0603_10V7K

2

PC122 390P_0402_50V7K VCC_PRM

PR176 ISEN2
3.4K_0402_1% PC123 470P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+
1

B PR1751 PC124 B
2
0.1U_0603_25V7K
PR177 1.82K_0402_1%
2

PC125 0.018U_0603_50V7J
5 VCCSENSE 1 2 1 2
VSUM
1

PR178 0_0402_5%
1

2.61K_0402_1%

PC126 PC127
PR180

+CPU_CORE 1 2 0.018U_0603_50V7J 0.018U_0603_50V7J

2

PR179 @ 20_0402_5% 1 2
5 VSSSENSE PR181 0_0402_5%
2
1

11K_0402_1%

PC128 180P_0402_50V8J
PR183

PR182 1 2
2

10KB_0603_5%_ERTJ1VR103J
@ 20_0402_5% 1 2 1 2 PH4
2

PR184 1K_0402_1% PR185 4.42K_0402_1%

PC129 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC131 0.22U_0402_6.3V6K
PC130 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 36 of 38
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record) FOR ISPD

IAKAA LA-3401P SCHEMATIC CHANGE LIST U5

REVISION CHANGE: 0.1 TO 0.2 LAN

NO DATE PAGE MODIFICATION LIST PURPOSE RTL8101E
100M@
---------------------------------------------------------------------------------------------------------------------
U30 R285
1 0803 23 CHANGE Q25,Q44,R252,R499 TO RESERVED TO COMPATIBLE WITH NORMAL OPEN AUDIO JACK
D D
CHANGE R611,R612 TO POP
2 0810 23 CHANGE C792,C793 TO RESERVE AND MOVE TO PAGE 23 TO RESERVE HP PATH FOR ALC268
TRANSFORMER
NS892404 2.49K_0402_1%
ADD C811 BETWEEB AMP_LHPIN AND 861_HP_L TO CHANGE HP PATH FOR ALC861 100M@ 1000M@
ADD C812 BETWEEB AMP_RHPIN AND 861_HP_R ZZZ1
3 0814 23 ADD R618_1K_0402 BETWEEN Q23.2 AND R240.2 TO BYPASS BEEP SOUND BEFORE CODEC INITIAL
24 ADD CONNECTION BEEP_MIX FROM Q23.2 TO Q67.2 PCB
ADD CONNECTION EAPD TO Q67.3 PCB ZKU LA-3401P REV0
CONNECT Q67.1,R616.1,C815.1 TOGETHER
PULL HIGH R616_20K_0402 TO +VDDA U31

CONNECT C815.2, R599.2 TOGETHER

REMOVE Q65 Card BUS
RESERVE C814 BETWEEN AMP_SD# & GND 4512
4512@
4 0816 14 CHANGE R121,R506,R99 TO 39_0402 FOR EMI REQUEST
5 0816 15 CHANGE L1,L2,L3 TO 120OHM BEAD FOR EMI REQUEST U16
6 0816 28 CHANGE U12,U28 FROM G528 TO G548 FOR INCREASE USB PORT CURRENT RATING
25 CHANGE U42 FROM G528 TO G548 SB
C ICH7 C

IAKAA LA-3401P SCHEMATIC CHANGE LIST ICH7R1@

REVISION CHANGE: 0.2 TO 0.3

U6 U6 U6

NO DATE PAGE MODIFICATION LIST PURPOSE NB

---------------------------------------------------------------------------------------------------------------------
1 0919 16 CONNECT INVPWR_B+ TO JP1.26 INCREASE 1 MORE B+ PIN FOR SUPPORT 2 LAMP LCD 945GM 945GM 945PM
GMR3@ GMR1@ PMR1@
2 0919 23 CONNECT R673_20K_0402 PULL DOWN ON SENSE_B TO SENSE INTERNAL MIC EXIST OR NOT
3 0919 04 CHANGE U48 TO PU5 TO COST DOWN 1 OP AMP R342
4 0919 26 RESERVE Q46,D47,R671 FOR RSMRST# SIGNAL TO MEET INTEL REQUIREMENT
5 0919 23 CHANGE R253 TO RESERVE TO CHANGE HEADPHONE SENSE PIN FROM SENSE_A TO SENSE_B SKU ID
CONNECT R620 BETWEEN Q25.1,SENSE_B 18K_0402_5%
6 0919 23 ADD R676,R677 TO 20OHM FIX MONO HEADPHONE NOISE ISSUE PM@

7 0926 23 CHANGE C811,C812,C792,C793 TO 2.2uF IMPROVE HP FREQENCE RESPONSE

8 0926 24 DEL R520,R521,C681,C683 CHANGE C790,C791 TO 0.22uF CHNAGE SPEAKER HIGHPASS -3dB POINT TO 100HZ PJP1

9 0926 24 CHANGE C804 TO 2.2uF IMPROVE CHARGE PUMP QUALITY

10 0926 24 DEL R616,R617,R599,C815 ADD C819 NOT TO USE AMP BEEP FUNCTION DC-JACK
B 11 0926 24 ADD Q67 IMPROVE BOOT BO SOUND SINGA_2DW-0005-B03 B
45@
12 0926 24 CHANGE C596 TO 22uF IMPROVE FAN NOISE
13 0926 24 ADD D48 IMPROVE ESD
C22 C20 C17
14 1003 22 ADD R678,R679,RESERVE L45 ADD R680,R681,RESERVE L46 FOR EMI REQUIREMENT
ADD R682,R683,RESERVE L47 ADD R684,R685,RESERVE L48 CRT EMI
ADD NET RJ45_MIDI0+_L,RJ45_MIDI0-_L BETWEEN L45,JP11 SOLUTION
RJ45_MIDI1+_L,RJ45_MIDI1-_L BETWEEN L46,JP11 10P_0402_50V8J
PM@
10P_0402_50V8J
PM@
10P_0402_50V8J
PM@
RJ45_MIDI2+_L,RJ45_MIDI2-_L BETWEEN L47,JP11
RJ45_MIDI3+_L,RJ45_MIDI3-_L BETWEEN L48,JP11
25 ADD R686,R687,RESERVE L49 FOR EMI REQUIREMENT
ADD NET USB20_5P,USB20_5N BETWEEN L49,JP24
28 ADD R688,R690,RESERVE L50 ADD R689,R691,RESERVE L51 RESERVE FOR USB EMI SOLUTION
ADD NET USB20_1N,USB20_1P BETWEEN L51,JP12
USB20_4N,USB20_4P BETWEEN L50,JP21

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
ISPD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IAKAA M/B LA-3401P
Date: Thursday, October 05, 2006 Sheet 37 of 38
5 4 3 2 1
 POWER PIR LIST
page Reason for change Modify list

35 Change +1.05V IC Change PU8 to ISL6269A(SA00000GU80), add PR122 (0ohm, SD013000080)

DVT
36 For EMI team request to add snubber and gate resistor Add snuber PR155,PR165(6.8ohm_SD011680B80), PC109,PC118(680p_SE024681J80) and gate resistor PR154,PR162(1ohm_SD013100B80)
Modify the CUP CORE load line and compensation Change PC103 to 0.022u(SE076223K80), PC104 to 2.2u(SE107225K80), PR185 to 4.42K(SD000004J80),
PC129 to 0.1u(SE076104K80, add PC126 (0.018U_SE025183J80), delete PC105 and PC106

31 Modify the CPU OTP point from 84 degC to 87 degC Change PR36 from 22K to 20K(SD034200280)
for thermal team request

32,34,
PVT 35,36 For EMI team request to add bead to reduce board band Add PL12,PL13,PL14(SM010020720);PC137,PC138,PC139(330p_SE074331K80);PC140(680p_SE074681K80);PC141(3300p_SE074332K80)

33 Reduce the power consumption on S3/S4 Add PR188(0_0402_5%) and unpop PR89
36 Solve the high frequency noise. Change PC99 from 100U to 220U(SF22004M210)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/03 Deciphered Date 2009/10/03 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HAWAA(LA3141) 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 05, 2006 Sheet 38 of 38