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  • Graphical Method: Virendra Singh

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    Tejas Pagare
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    This document discusses a lecture on logic optimization and function minimization using the Karnaugh map method. It was presented by Professor Virendra Singh of the Indian Institute of Technology Bombay. The lecture covers the Karnaugh map technique developed by American physicist Maurice Karnaugh in the 1950s for simplifying Boolean functions and designing combinational logic circuits. Diagrams and examples are provided to illustrate how to use K-maps to minimize logic functions.

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    Lecture17A-EE224

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    This document discusses a lecture on logic optimization and function minimization using the Karnaugh map method. It was presented by Professor Virendra Singh of the Indian Institute of Technology Bombay. The lecture covers the Karnaugh map technique developed by American physicist Maurice Karnaugh in the 1950s for simplifying Boolean functions and designing combinational logic circuits. Diagrams and examples are provided to illustrate how to use K-maps to minimize logic functions.

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    © All Rights Reserved
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    33 views9 pages

    Graphical Method: Virendra Singh

    Uploaded by

    Tejas Pagare
    This document discusses a lecture on logic optimization and function minimization using the Karnaugh map method. It was presented by Professor Virendra Singh of the Indian Institute of Technology Bombay. The lecture covers the Karnaugh map technique developed by American physicist Maurice Karnaugh in the 1950s for simplifying Boolean functions and designing combinational logic circuits. Diagrams and examples are provided to illustrate how to use K-maps to minimize logic functions.

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    of 9

    Logic Optimization:

    Graphical Method
    Virendra Singh
    Professor
    Computer Architecture and Dependable Systems Lab
    Department of Electrical Engineering
    Indian Institute of Technology Bombay
    http://www.ee.iitb.ac.in/~viren/
    E-mail: viren@ee.iitb.ac.in
    EE-224: Digital Systems
    Lecture 17-A: 18 October 2020 CADSL
    Function Minimization

    18 Oct 2020 EE-224@IITB 2 CADSL


    Function Minimization

    18 Oct 2020 EE-224@IITB 3 CADSL


    Graphical Method: Karnaugh Map
    Maurice Karnaugh
    • American Physicist
    • Bell Lab (1952 – 66)
    • Developed K-Map in 1954

    Maurice Karnaugh
    Born: 4 October 1924

    Karnaugh, Maurice (November 1953), "The Map Method for Synthesis of


    Combinational Logic Circuits" . Transactions of the American Institute of
    Electrical Engineers, Part I: Communication and Electronics. 72(5): 593–599

    18 Oct 2020 EE-224@IITB 4 CADSL


    Function Minimization: K-Map

    18 Oct 2020 EE-224@IITB 5 CADSL


    Function Minimization: K-Map

    18 Oct 2020 EE-224@IITB 6 CADSL


    Function Minimization: K-Map

    18 Oct 2020 EE-224@IITB 7 CADSL


    Function Minimization: K-Map

    18 Oct 2020 EE-224@IITB 8 CADSL


    Thank You

    18 Oct 2020 EE-224@IITB 9 CADSL

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