UNIT-1

Basic Structure of Computers

COURSE CONTENT:

1. Basic Computer Instruction

2. Addressing Modes
3. Memory based Vs Register based addressing modes
4. Von Neumann architecture
5. Interaction of a Program with Hardware
6. Simplified Instructional Computer (SIC)
7. Instruction Set used in simplified instructional Computer
(SIC)
8. Instruction Set used in SIC/XE
9. RISC and CISC
Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Basic functional units of a computer.

Information Handled by a Computer
• Instructions/machine instructions
Govern the transfer of information within a computer as well as between the
computer and its I/O devices
Specify the arithmetic and logic operations to be performed
Program
• Data
Used as operands by the instructions
Source program
• Encoded in binary code – 0 and 1
Memory Unit
• Store programs and data
• Two classes of storage
Primary storage
Fast
Programs must be stored in memory while they are being executed
Large number of semiconductor storage cells
Processed in words
Address
RAM and memory access time
Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
Arithmetic and Logic Unit (ALU)
• Most computer operations are executed in ALU of the processor.
• Load the operands into memory – bring them to the processor – perform operation
in ALU – store the result back to memory or retain in the processor.
• Registers
• Fast control of ALU
Control Unit
• All computer operations are controlled by the control unit.
• The timing signals that govern the I/O transfers are also generated by the control
unit.
• Control unit is usually distributed throughout the machine instead of standing
alone.
• Operations of a computer:
Accept information in the form of programs and data through an input unit and
store it in the memory
Fetch the information stored in the memory, under program control, into an ALU,
where the information is processed
Output the processed information through an output unit
Control all activities inside the machine through a control unit
 Control

PC R0

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

Connection Between the Processor and the

Figure 1.2. Connections between the processor and the memory.

Memory
Registers
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)
Typical Operating Steps
• Programs reside in the memory through input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
Typical Operating Steps (Cont’)
• Get operands for ALU
General-purpose register
Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to the next instruction
Addressing Modes
Prerequisite - Introduction to
parts of CPU
• Arithmetic and Logic Unit (ALU)
It performs all the arithmetic and logical micro
CU operations.
• Floating Point Unit (FPU)

REGISTERS
It performs operations on floating point numbers.
ALU
• Memory Unit (MU)
It stores the set of instructions.
FPU • Control Unit (CU)
It supervises the sequence of micro operations.
MU • Registers
Temporary storage area, which holds the data during
the execution of an instruction.
Prerequisite - Registers inside CPU
Accumulator Flag Register / Program Status Word (PSW)
S = Sign, Z = Zero, CY = Carry,
A C
A (8-bit) S Z C P Y AC = Auxiliary Carry, P = Parity,

B (8-bit) C (8-bit)

D (8-bit) E (8-bit) General Purpose

Registers
H (8-bit) L (8-bit)

PC (16-bit)
Index
SP (16-bit) Registers
 Addressing Modes
• Microprocessor executes the instructions stored in memory
(RAM).
• It executes one instruction at a time.
• Each of the instruction contains operations and operands.
• Operation specifies the type of action to be performed.
• For example: ADD, SUB, MOV, INC, LOAD, STORE
• Operands are the data on which the operation is to be
performed.

Here MOV is operation and (B & A) are operands.

MOV B, A
ADD B Here ADD is operation and (B) is operand.
 Addressing Modes
• Operand can be place either in one of the processor register
or in memory.

• There are different ways to get the operands.

• The way in which the operand is taken from register or

memory is named as addressing mode.
 Addressing Modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Implied Addressing Mode
7. Relative Addressing Mode
8. Indexed Addressing Mode
9. Base Register Addressing Mode
10. Autoincrement or Autodecrement
Addressing Mode
1. Immediate Addressing Mode
• The operand is specified with in the instruction.
• Operand itself is provided in the instruction rather
than its address.
Move Immediate

MVI A , 15h A ← 15h Here 15h is the immediate

operand

Add Immediate
ADI 3Eh A ← A + 3Eh Here 3Eh is the immediate
operand
2. Register Addressing Mode

• The operand is specified with in one of the

processor register.
• Instruction specifies the register in which the
operand is stored.

Move
Here A is the operand specified in register
MOV C , A C ← A

Add
ADD B A ← A + B Here B is the operand specified in register
3. Register Indirect Addressing Mode
• The instruction specifies the register in which the
memory address of operand is placed.
• It do not specify the operand itself but its location with
in the memory where operand is placed.

Move
MOV A , M A ← [[H][L]]

It moves the data from memory location specified by HL register pair toA.
 3. Register Indirect Addressing Mode
• MOV A , M A ← [[H][L]]
• It moves the data from memory location specified by HL register pair
toA.
2807
2807
• Before 2806 After
2806
• A 2805 A9 A A9
2805 A9
H 28 2804 H 28
2804
2803
L 05 L 05 2803
2802
2802
A ← [2805] 2801 A ← A9
2801
2800
2800
 4. Direct Addressing Mode
• The instruction specifies the direct address of
the operand.
• The memory address is specified where the
actual operand is.
• Load Accumulator
LDA 2805h A ← [2805]
It loads the data from memory location 2805 to A.
Store Accumulator
STA 2803h [2803] ← A
It stores the data from A to memory location 2803.
 4. Direct Addressing Mode
LDA 2805h A ← [2805]
It loads the data from memory location
2805 to A.
2807 2807
Before After
2806 2806

2805 5C 2805 5C
A A 5C
2804 2804

A ← [2805] 2803 A ← 5C 2803

2802 2802

2801 2801

2800 2800
 4. Direct Addressing Mode
STA 2803h [2803] ← A
It stores the data from A to memory
location 2803.

Before After
2807 2807

2806 2806
A 9B A 9B
2805 2805

2804 2804
[2803] ← A [2803] ← 9B
2803 2803 9B

2802 2802

2801 2801

2800 2800
5. Indirect Addressing Mode

• The instruction specifies the indirect address where the

effective address of the operand is placed.
• The memory address is specified where the actual
address of operand is placed.

Move
MOV A, 2802h A ← [[2802]]

It moves the data from memory location specified by the location 2802 to A.
5. Indirect Addressing Mode

MOV A, 2802h A ← [[2802]]

It moves the data from memory location specified
by the location 2802 to A.
Before After

A 2807 A FF 2807
2806 FF 2806 FF
2805 2805
A ← [[2802]] 2804 A ← FF 2804
2803 2803
2802 2806 2802 2806
2801 2801
2800 2800
 6. Implied Addressing Mode
• It is also called inherent addressing mode.
• The operand is implied by the instruction.
• The operand is hidden/fixed inside the instruction.

Complement Accumulator CMA

(Here accumulator A is implied by the instruction)

Complement Carry Flag CMC

(Here Flags register is implied by the instruction)

Set Carry Flag STC

(Here Flags register is implied by the instruction)
7. Relative Addressing Mode

• In relative addressing mode, contents of Program Counter

PC is added to address part of instruction to obtain effective
address.

• The address part of the instruction is called as offset and it

can +ve or –ve.

• When the offset is added to the PC the resultant number is

the memory location where the operand will be placed.
7. Relative Addressing Mode

2807 22 2807 22
2806 FF 2806 FF Actual
Offset = 04h
2805 6D 2805 6D Operand
2804 59 2804 59
PC 2801 2803 08 2803 08
2802 2E 2802 2E
2801 F3 2801 F3
2800 9F 2800 9F

Effective address of operand = PC + 01 + offset

Effective address of operand = 2801 + 01 + 04
Effective address of operand = 2806h
 7. Relative Addressing Mode

2807 22 2807 22 Actual

2806 FF 2806 FF Operand
Offset = 03h
2805 6D 2805 6D
2804 59 2804 59
PC 2803 2803 08 2803 08
2802 2E 2802 2E
2801 F3 2801 F3
2800 9F 2800 9F

Effective address of operand = PC + 01 + offset

Effective address of operand = 2803 + 01 + 03
Effective address of operand = 2807h
 8. Indexed Addressing Mode
• In index addressing mode, contents of Index register is added
to address part of instruction to obtain effective address.

• The address part of instruction holds the beginning/base

address and is called as base.

• The index register hold the index value, which is +ve.

• Base remains same, the index changes.

• When the base is added to the index register the resultant

number is the memory location where the operand will be
placed.
8. Indexed Addressing Mode
Base = 2800h
Effective address of operand = Base + IX
2807 22 2807 22 2807 22 2807 22
2806 FF 2806 FF 2806 FF 2806 FF
2805 6D 2805 6D 2805 6D 2805 6D
2804 59 2804 59 2804 59 2804 59
2803 08 2803 08 2803 08 2803 08
2802 2E 2802 2E 2802 2E 2802 2E
2801 F3 2801 F3 2801 F3 2801 F3
2800 9F 2800 9F 2800 9F 2800 9F

I 0000 I 0001 I 0002 I 0003

X X X X
2800h + 0000h = 2800h + 0001h = 2800h + 0002h = 2800h + 0003h =
2800h 2801h 2802h 2803h
8. Indexed Addressing Mode
Base = 2802h
Effective address of operand = Base + IX
2807 22 2807 22 2807 22 2807 22
2806 FF 2806 FF 2806 FF 2806 FF
2805 6D 2805 6D 2805 6D 2805 6D
2804 59 2804 59 2804 59 2804 59
2803 08 2803 08 2803 08 2803 08
2802 2E 2802 2E 2802 2E 2802 2E
2801 F3 2801 F3 2801 F3 2801 F3
2800 9F 2800 9F 2800 9F 2800 9F

I 0000 I 0001 I 0002 I 0003

X X X X
2802h + 0000h = 2802h + 0001h = 2802h + 0002h = 2802h + 0003h =
2802h 2803h 2804h 2805h
9. Base Register Addressing Mode
• In base register addressing mode, contents of base register is
added to address part of instruction to obtain effective
address.

• It is similar to the indexed addressing mode except the

register now is called as base instead of index.

• The base register hold the beginning/base address.

• The address part of instruction holds the offset.

• Offset remains same, the base changes.

• When the offset is added to the base register the resultant

number is the memory location where the operand will be
placed.
9. Base Register Addressing Mode
Offset= 0001h
Effective address of operand = Base Register + offset

2807 22 2807 22 2807 22

2807 22
2806 FF 2806 FF 2806 FF
2806 FF
2805 6D 2805 6D 2805 6D
2805 6D
2804 59 2804 59 2804 59
2804 59
2803 08 2803 08 2803 08
2803 08
2802 2E 2802 2E 2802 2E
2802 2E
2801 F3 2801 F3 2801 F3
2801 F3
2800 9F 2800 9F 2800 9F
2800 9F

Base 2800 Base 2801 Base 2802 Base 2803

2800h + 0001h = 2801h + 0001h = 2802h + 0001h = 2803h + 0001h =

2801h 2802h 2803h 2804h
9. Base Register Addressing Mode
Offset= 0003h
Effective address of operand = Base Register + offset
2807 22 2807 22 2807 22 2807 22
2806 FF 2806 FF 2806 FF 2806 FF
2805 6D 2805 6D 2805 6D 2805 6D
2804 59 2804 59 2804 59 2804 59
2803 08 2803 08 2803 08 2803 08
2802 2E 2802 2E 2802 2E 2802 2E
2801 F3 2801 F3 2801 F3 2801 F3
2800 9F 2800 9F 2800 9F 2800 9F

Base 2800 Base 2801 Base 2802 Base 2803

2800h + 0003h = 2802h + 0003h = 2803h + 0003h =

2801h + 0003h =
2803h 2805h 2806h
2804h
10. Autoincrement or Autodecrement
Addressing Mode

• It is similar to register indirect addressing mode.

• Here the register is incremented or decremented before or

after its value is used.
10. Autoincrement or Autodecrement
Addressing Mode
HL pair incremented after its value is used

At H 2802
start: L

2807 22 2807 22 2807 22 2807 22

2806 FF 2806 FF 2806 FF 2806 FF
2805 6D 2805 6D 2805 6D 2805 6D
2804 59 2804 59 2804 59 2804 59
2803 08 2803 08 2803 08 2803 08
2802 2E 2802 2E 2802 2E 2802 2E
2801 F3 2801 F3 2801 F3 2801 F3
2800 9F 2800 9F 2800 9F 2800 9F

H 2802 H 2803 H 2804 H 2805

L L L L
1st 2nd 3rd 4th
Time Time Time Time
10. Autoincrement or Autodecrement
Addressing Mode
HL pair incremented before its value is used
At H 2803
start: L

2807 22 2807 22 2807 22 2807 22

2806 FF 2806 FF 2806 FF 2806 FF
2805 6D 2805 6D 2805 6D 2805 6D
2804 59 2804 59 2804 59 2804 59
2803 08 2803 08 2803 08 2803 08
2802 2E 2802 2E 2802 2E 2802 2E
2801 F3 2801 F3 2801 F3 2801 F3
2800 9F 2800 9F 2800 9F 2800 9F

H 2804 H 2805 H 2806 H 2807

L L L L
1st 2nd 3rd 4th
Time Time Time Time
Von Neumann
Architecture
 Introduction

• The Von Neumann Architecture which is also known as the Von Neumann
Model and Princeton Architecture, is a design model for stored programs.
• The most important feature is the memory that can holds both data and
program.
• In 1945, the mathematician and physician John Von Neumann wrote a
report on the stored program concept, known as the First Draft of a Report
on EDVAC.
• The new idea was that not only the data should be stored in memory but
the program processing that data should also be stored in the same
memory.
Components:
 Input / Output Subsystem:
• This Architecture handles devices that allow the computer
system to communicate and interact with the outside world.
• Inputs are the signals or data received by the system and
outputs are the signals or data sent from it.
• I/O system includes two basic components.
• I/O module is normally connected to the computer system.
• I/O device is connected to I/O module of the computer
called peripheral device.
Input / Output Subsystem:
• I/O module gets data from peripherals while CPU
does other work. I/O module interrupts CPU. CPU
requests for data. I/O module transfers data.
• Speed of I/O devices are slower as compared to
CPU. i.e. Suppose a benchmark executes in 100 sec
• .
• CPU 90%
• I/O 10%

• For instance, a keyboard, mouse, or scanner are the

input devices for a computer, while monitor, printer
or LED are the output devices.
 Central Processing Unit:
• CPU is the abbreviation for central processing unit. Sometimes referred to
simply as the central processor, but more commonly called processor.
• CPU is the brains of the computer where all computations take place. In
terms of computing power, the CPU is the most important element of a
computer system.
• It is a set of electronic circuitry that executes the stored program instructions.
• The four primary functions of a processor are fetch, decode, execute and
write back.
• Components of CPU are ALU (Airthematic and Logic Unit) and CU (Control
Unit).
 Airthematic and Logic Unit:

• ALU is a digital circuit used to perform arithmetic and logic operations.

• Most of the operations of a CPU are performed by one or more ALUs,
which load data from input registers.
• ALU perform basic arithmetic and logic operations. Addition,
subtraction, multiplication and division come under Airthematic
operations while Logical AND, OR and XOR come under logical
operations. Logic operations can be accomplished by connecting
multiple transistors.
 Control Unit
• This section is the boss of the CPU and coordinates all activity within the
CPU.
• It act as a traffic signal directing the flow of data through the CPU as well
as to and from other devices.
• The control unit controls the computer by repeating four operations called
machine cycle. These four operations are;
• Fetching program instructions from memory.
• Decoding the instructions into commands.
• Executing the commands.
• Storing the results in the memory.
 Main Memory
• In Computing, Memory refers to a physical memory used to store programs
or data on the temporary or permanent basis for use in a computer.
• Main memory is divided into two parts RAM and ROM
• The computer is able to change data that is in random access memory but it
is a volatile memory and don’t retains its contents when the power is lost.
• ROM contains pre-recorded data that can be read but not modified or
deleted but it is a non-volatile memory and so retains its contents when the
power is removed.
 Advantage and Disadvantage:
• Easy memory organization for the user
• Data from memory and from devices are accessed in the same way.
• It is better for desktop computers, laptops, workstations and high
performance computers.
• The programs can be optimized in smaller size.
• Only handles one task at a time.
• Bottlenecking is an issue because it take more time to execute.
SIMPLIFIED INSTRUCTIONAL COMPUTER
(SIC)
and
SIC/XE (extra equipments)
SIC ARCHITECTURE

• Two versions: SIC and SIC/XE (extra equipments). SIC program can be
executed on SIC/XE.
• Memory consists of 8-bit bytes. 3 consecutive bytes form a word (24 bits)
• In total, there are 2^15 bytes in the memory.
• There are 5 registers. Each is 24 bits in length.
Five Registers
DATA FORMAT

• Integers are stored as 24-bit binary numbers; 2’s complement

representation is used for negative numbers.
• Characters are store using their 8-bit ASCII codes.
• There is no floating-point hardware on SIC.
INSTRUCTION FORMAT

• All machine instructions on SIC has the following

24-bit format.

X is used to indicate indexed-addressing mode.

Addressing Modes

• Only two modes are supported:

• Direct
• Indexed

() are used to indicate the content of a register.

Instruction Set
• Load and store registers (LDA, LDX, STA, STX)
• Integer arithmetic (ADD, SUB, MUL, DIV), all involve register A and a
word in memory.
• Comparison (COMP), involve register A and a word in memory.
• Conditional jump (JLE, JEQ, JGT, etc.)
• Subroutine linkage (JSUB, RSUB)
Input and Output
• One byte at a time to or from the rightmost 8 bits of
register A.
• Each device has a unique 8-bit ID code.
• Test device (TD): test if a device is ready to send or
receive a byte of data.
• Read data (RD): read a byte from the device to register A
• Write data (WD): write a byte from register A to the
device.
SIC/XE Architecture
• Memory: 1 megabytes (2^20 bytes)

Additional Registers
Data Format

• The same as that of SIC.

• There is a floating-point data type with the
following format:
Between 0 and 1

Must be 1

• The value represented by the above format is

(-1)^s * f * 2 ^(e – 1024)
Instruction Formats

e=0

e=1
 Addressing Mode
• Two additional modes are introduced for format 3:

In format 3, if both bits b and p are set to 0, the disp (or address) is taken as the
target address. This is called direct addressing mode.

Both modes can be combined with indexed addressing – if bit x is set to 1, the
value of register X is added in the target Address calculation.
 Addressing Modes

For format 3 and 4:

• (i =1, n = 0): immediate addressing mode. The target address is used as the
operand.
• (i = 0, n = 1): indirect addressing mode. The word at the location given by
the target address is fetched; the value contained in this word is then used
as the address of the operand value.
• (i = 0, n = 0) used by SIC, (i=1, n=1) used by SIC/XE: simple addressing
mode. The target address is taken as the location of the operand.

Indexing mode cannot be used with immediate or indirect modes.

Example

All of these instructions are LDA.

 INSTRUCTION SET

• LDB and STB

• Floating-point operations (ADDF, SUBF, MULF, DIVF)
• Register move (RMO)
• Register-to-register operations (ADDR, SUBR, MULR, DIVR)
• Supervisor call (SVC) for generating system calls into the operating system.
• I/O channel operation (SIO: start, TIO: test, HIO: halt), similar to DMA.
COMPLETE INSTRUCTION SET

P: privileged instruction

X: available Only on XE
F: floating- Point Instruction
C: condition code CC set to
indicate result of operation
INTERACTION OF A PROGRAM WITH HARDWARE
RISC and CISC
What is CISC?
• CISC is an acronym for Complex Instruction Set Computer and are chips
that are easy to program and which make efficient use of memory. Since the
earliest machines were programmed in assembly language and memory was
slow and expensive, the CISC philosophy made sense
• CISC was developed to make compiler development simpler. It shifts most
of the burden of generating machine instructions to the processor. For
example, instead of having to make a compiler write long machine
instructions to calculate a square-root, a CISC processor would have a built-
in ability to do this.
Most CISC hardware architectures have several characteristics in common:
• Complex instruction-decoding logic, driven by the need for a single
instruction to support multiple addressing modes.
• A small number of general purpose registers. This is the direct result of
having instructions which can operate directly on memory and the limited
amount of chip space not dedicated to instruction decoding, execution,
and microcode storage.
• Several special purpose registers. Many CTSC designs set aside special
registers for the stack pointer, interrupt handling, and so on. This can
simplify the hardware design somewhat, at the expense of making the
instruction set more complex.
• A 'Condition code" register which is set as a side-effect of most
instructions. This register reflects whether the result of the last operation
is less than, equal to, or greater than zero and records if certain error
conditions occur.
 What is RISC?
• RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor
architecture that utilizes a small, highly-optimized set of instructions, rather
than a more specialized set of instructions often found in other types of
architectures.
• History
The first RISC projects came from IBM, Certain design features have been
characteristic of most RISC processors:
• one cycle execution time: RISC processors have a CPI (clock per
instruction) of one cycle. This is due to the optimization of each
instruction on the CPU and a technique called PIPELINING
• pipelining: a technique that allows for simultaneous execution of parts, or
stages, of instructions to more efficiently process instructions;
• large number of registers: the RISC design philosophy generally
incorporates a larger number of registers to prevent in large amounts of
interactions with memory
 RISC Attributes
The main characteristics of CISC microprocessors are:
• Extensive instructions.
• Complex and efficient machine instructions.
• Microencoding of the machine instructions.
• Extensive addressing capabilities for memory operations.
• Relatively few registers.
In comparison, RISC processors are more or less the opposite of the above:
• Reduced instruction set.
• Less complex, simple instructions.
• Hardwired control unit and machine instructions.
• Few addressing schemes for memory operands with only two basic instructions, LOAD
and STORE
• Many symmetric registers which are organized into a register file.
CISC versus RISC
CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clock Single-clock,
complex instructions reduced instruction only

Memory-to-memory: Register to register:

"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions

Small code sizes, high cycles per large code sizes, Low cycles per
second second

Transistors used for storing Spends more transistors

complex instructions on memory registers