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Driver/Receiver
EIA 232–E and CCITT V.28
(Formerly RS–232–D)
Drivers
• ± 5 V to ±12 V Supply Range
• 300–Ω Power–Off Source Impedance CROSS REFERENCE/ORDERING INFORMATION
PACKAGE MOTOROLA LANSDALE
• Output Current Limiting
P DIP 16 MC145406P ML145406EP
• TTL Compatible SO 16W MC145406DW ML145406-6P
• Maximum Slew Rate = 30 V/µs
Receivers
Note: Lansdale lead free (Pb) product, as it
• ± 25 V Input Voltage Range When VDD = 12 V, VSS = – 12 V becomes available, will be identified by a part
• 3 to 7 kΩ Input Impedance number prefix change from ML to MLE.
• Hysteresis on Input Switchpoint
BLOCK DIAGRAM
1.8 V 5 12
Tx2 D DI2
HYSTERESIS
6 11
VDD Rx3 R DO3
DRIVER
VCC 7 10
Tx3 D DI3
300 + DI GND
LEVEL VSS 8 9
Tx
SHIFT – 1.4 V
D = DRIVER
R = RECEIVER
VSS
*Protection circuit
* This is the range of input voltages as specified by EIA 232–E to cause a receiver to be in the high or low logic state.
PIN DESCRIPTIONS
1 16 VDD
VDD VCC Positive Power Supply (Pin 1)
14 3
DI1 Tx1 The most positive power supply pin, which is typically + 5
to +12V.
12 DI2 Tx2 5 Vin = ± 2 V VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
10
DI3 Tx3
7 to –12 V.
VCC
VSS GND Vin Digital Power Supply (Pin 16)
Rout =
8 9 I The digital supply pin, which is connected to the logic power sup-
ply (maximum +5.5 V). VCC must be less than or equal to VDD.
GND
Figure 1. Power–Off Source Resistance (Drivers) Ground (Pin 9)
Ground return pin is typically connected to the signal ground
pin of the EIA 232–E connector (Pin 7) as well as to the logic
power supply ground.
DRIVERS
3V
Rx1, Rx2, Rx3
DI1–DI3
Receive Data Input (Pins 2, 4, 6)
50%
0V These are the EIA 232–E receive signal inputs whose volt-
ages can range from (VDD + 15 V) to (VSS – 15 V). A volt-
tf tr age between +3 and (VDD + 15 V) is decoded as a space and
VOH causes the corresponding DO pin to swing to ground (0V); a
90%
Tx1–Tx3 voltage between – 3 and (VDD – 15 V) is decoded as a mark
10% and causes the DO pin to swing up to VCC. The actual turn–on
VOL
tPHL tPLH input switch point is typically biased at 1.8 V above ground,
and includes 800mV of hysteresis for noise rejection. The
nominal input impedance is 5 kΩ. An open or grounded input
RECEIVERS
pin is interpreted as a mark, forcing the DO pin to VCC.
+3V
Rx1–Rx3 50%
DO1, DO2, DO3
0V
Data Output (Pins 11, 13, 15)
tPHL tPLH These are the receiver digital output pins, which swing from
VOH
VCC to GND. A space on the Rx pin causes DO to produce a
90%
50% logic 0; a mark produces a logic 1. Each output pin is capable
DO1–DO3 of driving one LSTTL input load.
10%
VOL
tf tr DI1, DI2, DI3
Data Input (Pins 10, 12,14)
Figure 2. Switching Characteristics These are the high–impedance digital input pins to the driv-
ers. TTL compatibility is accomplished by biasing the input
switchpoint at 1.4 V above GND. However, 5V CMOS compat-
ibility is maintained as well. Input voltage levels on these pins
must be between VCC and GND.
The ML145406 has been designed to meet the electrical- forces the appropriate DO pin to a logic 1 when its Rx input is
specifications of standards EIA 232–E and CCITT V.28. EIA open or grounded as called for in the EIA 232–E specification.
232–E defines the electrical and physical interface between Notice that TTL logic levels can be applied to the Rx inputs in
Data Communication Equipment (DCE) and DataTerminal lieu of normal EIA 232–E signal levels. This might be helpful
Equipment (DTE). A DCE is connected to a DTE using a cable in situations where access to the modem or computer through
that typically carries up to 25 leads. These leads, referred to as the EIA 232–E connector is necessary with TTL devices.
interchange circuits, allow the transfer of timing, data, control, However, it is important not to connect the EIA 232–E outputs
and test signals. Electrically this transfer requires level shifting (Tx1–Tx3) to TTL inputs since TTL operates off + 5 V only,
between the TTL/CMOS logic levels of the computer or and may be damaged by the high output voltage of the
modem and the high voltage levels of EIA 232–E, which can ML145406.
range from ±3 to ±25 V. The ML145406 provides the neces- The DO outputs are to be connected to a TTL or CMOS
sary level shifting as well as meeting other aspects of the EIA input (such as an input to a modem chip). These outputs will
232–E specification. swing from VCC to ground, allowing the designer to operate
the DO and DI pins from digital power supply. The Tx and Rx
DRIVERS sections are independently powered by VDD andVSS so that
As defined by the specification, an EIA 232–E driver pres- one may run logic at + 5 V and the EIA 232–E signals at ±12V.
ents a voltage of between ±5 to ±15 V into a load of between 3
to 7 kΩ. A logic 1 at the driver input results in a voltage of POWER SUPPLY CONSIDERATIONS
between –5 to – 15 V. A logic 0 results in a voltage between + Figure 4 shows a technique to guard against excessive device
5 to + 15V. When operating VDD and VSS at ±7 to ±12 V, the current.
ML145406 meets this requirement. When operating at ±5 V, The diode D1 prevents excessive current from flowing
the ML145406 drivers produce less than ±5 V at the output through an internal diode from the VCC pin to the VDD pin
(when terminated), which does not meet EIA 232–E specifica- when VDD < VCC by approximately 0.6 V. This high current
tion. However, the output voltages when using a ±5 V power condition can exist for a short period of time during
supply are high enough (around ±4 V) to permit proper recep- powerup/down. Additionally, if the + 12 V supply is switched
tion by an EIA 232–E receiver, and can be used in applications off while the + 5 V is on and the off supply is a low impedance
where strict compliance to EIA 232–E is not required. to ground, the diode D1 will prevent current flow through the
Another requirement of the ML145406 drivers is that they internal diode.
withstand a short to another driver in the EIA 232–E cable. The diode D2 is used as a voltage clamp, to prevent VSS
The worst–case condition that is permitted by EIA 232–E is a from drifting positive to VCC, in the event that power is
±15V source that is current limited to 500 mA. The ML145406 removed from VSS (Pin 12). If VSS power is removed, and the
drivers can withstand this condition momentarily. In most short impedance from the VSS pin to ground is greater than approxi-
circuit conditions the source driver will have a series 300 Ω mately 3 kΩ, this pin will be pulled to VCC by internal circuit-
output impedance needed to satisfy the EIA 232–E driver ry causing excessive current in the VCC pin.
requirements. This will reduce the short circuit current to If by design, neither of the above conditions are allowed to
under 40 mA which is an acceptable level for the ML145406 exist, then the diodes D1 and D2 are not required.
to withstand.
Unlike some other drivers, the ML145406 drivers feature an ESD PROTECTION
internally–limited output slew–rate that does not exceed 30 V ESD protection on IC devices that have their pins accessible
per µs. to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or indi-
RECEIVERS rectly can cause damage to gate oxides and transistor junctions
The job of an EIA 232–E receiver is to level–shift voltages by coupling a portion of the energy from the I/O pin to the
in the range of – 25 to + 25 V down to TTL/CMOS logic lev- power supply buses of the IC. This coupling will usually occur
els (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1 through the internal ESD protection diodes. The key to protect-
is defined as a mark and produces a logic 1 at DO1. A voltage ing the IC is to shunt as much of the energy to ground as pos-
between + 3 and + 25 V is a space and produces a logic zero. sible before it enters the IC. Figure 4 shows a technique which
While receiving these signals, the Rx inputs must present a will clamp the ESD voltage at approximately ±15 V using the
resistance between 3 and 7 kΩ. Nominally, the input resistance MMVZ15VDLT1. Any residual voltage which appears on the
of the Rx1–Rx3 inputs is 5.4 kΩ. supply pins is shunted to ground through the capacitors
The input threshold of the Rx1–Rx3 inputs is typically C1–C3. This scheme has provided protection to the interface
biased at 1.8 V above ground (GND) with typically 800 mV of part up to ±10kV, using the human body model test.
hysteresis included to improve noise immunity. The 1.8 V bias
VDD
MMBZ15VDLT × 6 D1 IN4001 VCC
0.1 µF 0.1 µF
C1 C2
1 16
RxI 2 15
TxO 3 14
TO RxI 4 13
CONNECTOR
ML145406
TxO 5 12
RxI 6 11
TxO 7 10
8 9
C3 IN5818 D2
VSS 0.1 µF
+ 5V
0.1 µF
20 kΩ 6 0.1 µF 1 16
VDD 9 VDD VCC
TLA Xin
RDSI CDSI RTLA** 3.579 ML145406
DTMF 1 DSI ML145442/3 MHz
INPUT 8 14 3
20 kΩ 17 TxA Xout DI1 Tx1 8
0.1 µF 3
15 RxA2 CD
11 15 2
TxD DO1 Rx1 2
RTx 5
600 RxD
10 kΩ 10 kΩ 12 5 3 EIA 232–E
10 µF + 16 DI2 Tx2
TIP RxA1 DB–25
14 CONNECTOR
SQT 4
* 600:600 NC 13 DO2 Rx2 7
10 kΩ
RING
18 2 10
VDD ExI LB DI3 Tx3 7 NC
CFB
10 10 k 10 kΩ
0.1 µF FB 6
13 NC 11 DO3 Rx3
VDD BYPASS 0.1 µF 19 MODE
VAG
4 7
CDT GND CDA CCDA** VSS GND
0.1 µF 0.1 µF 12 0.1 µF 8 9
VSS BYPASS CCDT
0.1 µF
1 2 3
MC34119 MC145412/13/16
SPEAKER 4 5 6
PULSE/TONE HOOKSWITCH
DRIVER 7 8 9
DIALER 0 #
*
RINGING LINE
ML145503 INTERFACE
FILTER/ MC145426 (TRANSFORMER
CODEC UDLT AND
PROTECTION) TWISTED
PAIR
SYNC
MC34129
CONNECTION ML145406 ML145428 +5V SWITCHING
TO EXTERNAL RS–232 DATA LINE
GND POWER
TERMINAL DRIVER SET FILTER
SUPPLY
OR PC RECEIVER INTERFACE –5V
(ISOLATED)
Figure 6. Line–Powered Voice/Data Telephone with Electrically Isolated EIA 232–E Interface
Page 9 of 10
NC NC NC
1 4 3 4 5
14 R1 S1 5 2.048 MHz 1 Q1 Q2 Q3
VCC VCC Q1 Ca a a a 11
6 VCC 14 NC
0.1 µF MC74HC74 Q1
Q1 2 V CC Q1 b
7 GND D1 8 0.1 µF MC74HC393
V DD Q
Q2 NC 10
9 0.1 µF 2 Q2 b NC
Q2 NC 7
Ra
10 NC NC NC G ND 9
S2 11 12 Q3 b NC
C2 NC 8 9 14 7 Q2 b
12 2 0 pF
R5 NC D2
R2 C1 OUT4 IN4 Q4a Qb Q4b
4 VDD VSS IN1 1
13 3 OUT2 6 13 8
NC 5 10 M
6 I N3 MC14069UB 2 4.096
DSR 6 OUT3 OUT1
3 MHz
1 V 9 OUT6 OUT5 IN6 IN5 I N2 2 0 pF
DB-25 V DD DD GND
12 10 13 11
ML 145406 C14 12 5 128 kHz
8 16 8 M Hz
2 VSS VSS V CC V CC 2 R xS BC
Tx 2 15 TxD 4.096 MHz
Rx1 DO1 13
4 4 Rx2 DO2 ML 145428
RTS 6 11 3 ST N C ST
Rx3 DO3 ST DL TxS 1 NC
8 3 14 11 16 9 8 5 4
CD Tx 1 DI1 NC
4 BRCLK RESET 19 ST
5 5 Tx2 12 DCO 18 18 Rx PD CCI SO2 SI2 VD LB
CTS 3 7 DI2 10 19 21
Rx Tx3 DI3
11 RxD DOE 17 RE1 LO1
17 20
7 DC 1 5 TDC/RDC ML 145422 LO2
www.lansdale.com
SG ST 6 BR1 DIE 14 14 TE 1
7 BR2 12 1000
ST MSI 220 pF * 220
8 BR3 13 15
ST 9 SB DCI 16 TxSO1 SI1 L1 SE VDD Vref VSS SIE
ST 10 V C M 7 6 3 10 22 2 1 13
SS VDD 20 V CC
8 9
0.1 µ F 0.1 µF 1 TI P
7 2
D1 T1 1.0 µ F**
TR1
0.1 µF 10 k
6 3
4 RING
D2
5 10
ST — STRAP
*For optional filtering. NC — NO CONNECTION
NC NC
**TR1 should be cut when this capacitor is used.
Figure 7. 80–kbps Limited Distance Modem with EIA 232–E Interface (Master)
VCC = 5 V
GND = 0 V
VDD AND VSS ARE DISCUSSED IN THE EIA-232-D SECTION
LANSDALE Semiconductor, Inc.
Issue A
ML145406 LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
(ML145406EP)
CASE 648–08
-A- NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
-T- PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
SOG 16 = -5P
(ML145406-5P)
CASE 751G–02
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16 9 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
-B- P 8 PL MOLD PROTRUSION.
0.25 (0.010) M B M 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
G 14 PL J (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
R X 45° D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
C
J 0.25 0.32 0.010 0.012
-T- K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
K SEATING M
D 16 PL PLANE P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
0.25 (0.010) M T A S B S
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.