EXPERIMENT NO.

Aim: To study and verify the operation of AND gate using CMOS technology.

Software Required: Tanner EDA

Theory:
The AND gate is a basic digital logic gate that implements logical conjunction.
A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1).
If none or not all inputs to the AND gate are HIGH, a LOW output results. The
function can be extended to any number of inputs.
C = A.B = A AND B

INPUT OUTPUT
A B C
0 0 0
0 1 0
1 0 0
1 1 1

Circuit Diagram:

Using S-Edit:-
T-Spice:-

Output Waveform:

W-Edit:-
Layout Of AND Gate:

L-Edit:-

Result:
AND Gate using CMOS Technology is successfully implemented using Tanner
EDA.
 EXPERIMENT NO.2

Aim: To study and verify the operation of OR gate using CMOS technology.

Software Required: Tanner EDA

Theory:
The OR gate is a digital logic gate that implements logical disjunction. A HIGH
output (1) results if one or both the inputs to the gate are HIGH (1). If neither
input is high, a LOW output (0) results. In another sense, the function of OR
effectively finds the maximum between two binary digits, just as the
complementary AND function finds the minimum.
C = A+B = A OR B

INPUT OUTPUT
A B C
0 0 0
0 1 1
1 0 1
1 1 1

Circuit Diagram:

Using S-Edit:-
T-Spice:-

Output Waveform:

W-Edit:-
Layout Of OR Gate:

L-Edit:-

Result:
OR Gate using CMOS Technology is successfully implemented using Tanner
EDA.

EXPERIMENT NO.3

Aim: To design and study DC characteristics of CMOS using CMOS

technology.

Software Required: Tanner EDA

Theory:
Complementary Metal Oxide Semiconductor (CMOS): CMOS technology is used
in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS
technology is also used for several analog circuits such as image sensors (CMOS
sensor), data converters, and highly integrated transceivers for many types of communication.
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–
semiconductor (COS-MOS). The words "complementary-symmetry" refer to the typical
design style with CMOS using complementary and symmetrical pairs of p-type and n-
type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two
important characteristics of CMOS devices are high noise immunity and low static power
consumption. Since one transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor–transistor logic (TTL) or N-type metal-oxide-semiconductor logic
(NMOS) logic, which normally have some standing current even when not changing state.
CMOS also allows a high density of logic functions on a chip. It was primarily for this reason
that CMOS became the most used technology to be implemented in very-large-scale
integration (VLSI) chips.

Circuit Diagram:

Using S-Edit:-
T-Spice:-

Output Waveform:

W-Edit:-
Result:
DC characteristics of CMOS are successfully designed and studied using
Tanner EDA.