SIMULATION 2

RESULTS

Logic gate Input Output

A B X
NAND 0 0 1
0 1 1
1 0 1
1 1 0
NOR 0 0 1
0 1 0
1 0 0
1 1 0

GATE CONVERSION

Input Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

TABLE 2.2

Input Output
A B C
0 0 0
0 1 0
1 0 0
1 1 1

TABLE 2.3